1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * arch/m68k/q40/config.c 4 * 5 * Copyright (C) 1999 Richard Zidlicky 6 * 7 * originally based on: 8 * 9 * linux/bvme/config.c 10 */ 11 12 #include <linux/errno.h> 13 #include <linux/types.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/console.h> 17 #include <linux/linkage.h> 18 #include <linux/init.h> 19 #include <linux/major.h> 20 #include <linux/serial_reg.h> 21 #include <linux/rtc.h> 22 #include <linux/bcd.h> 23 #include <linux/platform_device.h> 24 25 #include <asm/io.h> 26 #include <asm/bootinfo.h> 27 #include <asm/setup.h> 28 #include <asm/irq.h> 29 #include <asm/traps.h> 30 #include <asm/machdep.h> 31 #include <asm/q40_master.h> 32 #include <asm/config.h> 33 34 #include "q40.h" 35 36 static void q40_get_model(char *model); 37 38 static int q40_hwclk(int, struct rtc_time *); 39 static int q40_get_rtc_pll(struct rtc_pll_info *pll); 40 static int q40_set_rtc_pll(struct rtc_pll_info *pll); 41 42 static void q40_mem_console_write(struct console *co, const char *b, 43 unsigned int count); 44 45 extern int ql_ticks; 46 47 static struct console q40_console_driver = { 48 .name = "debug", 49 .write = q40_mem_console_write, 50 .flags = CON_PRINTBUFFER, 51 .index = -1, 52 }; 53 54 55 /* early debugging function:*/ 56 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 57 static int _cpleft; 58 59 static void q40_mem_console_write(struct console *co, const char *s, 60 unsigned int count) 61 { 62 const char *p = s; 63 64 if (count < _cpleft) { 65 while (count-- > 0) { 66 *q40_mem_cptr = *p++; 67 q40_mem_cptr += 4; 68 _cpleft--; 69 } 70 } 71 } 72 73 static int __init q40_debug_setup(char *arg) 74 { 75 /* useful for early debugging stages - writes kernel messages into SRAM */ 76 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) { 77 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ 78 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; 79 register_console(&q40_console_driver); 80 } 81 return 0; 82 } 83 84 early_param("debug", q40_debug_setup); 85 86 #if 0 87 void printq40(char *str) 88 { 89 int l = strlen(str); 90 char *p = q40_mem_cptr; 91 92 while (l-- > 0 && _cpleft-- > 0) { 93 *p = *str++; 94 p += 4; 95 } 96 q40_mem_cptr = p; 97 } 98 #endif 99 100 static int halted; 101 102 #ifdef CONFIG_HEARTBEAT 103 static void q40_heartbeat(int on) 104 { 105 if (halted) 106 return; 107 108 if (on) 109 Q40_LED_ON(); 110 else 111 Q40_LED_OFF(); 112 } 113 #endif 114 115 static void q40_reset(void) 116 { 117 halted = 1; 118 pr_info("*******************************************\n" 119 "Called q40_reset : press the RESET button!!\n" 120 "*******************************************\n"); 121 Q40_LED_ON(); 122 while (1) 123 ; 124 } 125 126 static void q40_halt(void) 127 { 128 halted = 1; 129 pr_info("*******************\n" 130 " Called q40_halt\n" 131 "*******************\n"); 132 Q40_LED_ON(); 133 while (1) 134 ; 135 } 136 137 static void q40_get_model(char *model) 138 { 139 sprintf(model, "Q40"); 140 } 141 142 static unsigned int serports[] = 143 { 144 0x3f8,0x2f8,0x3e8,0x2e8,0 145 }; 146 147 static void __init q40_disable_irqs(void) 148 { 149 unsigned i, j; 150 151 j = 0; 152 while ((i = serports[j++])) 153 outb(0, i + UART_IER); 154 master_outb(0, EXT_ENABLE_REG); 155 master_outb(0, KEY_IRQ_ENABLE_REG); 156 } 157 158 void __init config_q40(void) 159 { 160 mach_sched_init = q40_sched_init; 161 162 mach_init_IRQ = q40_init_IRQ; 163 mach_hwclk = q40_hwclk; 164 mach_get_rtc_pll = q40_get_rtc_pll; 165 mach_set_rtc_pll = q40_set_rtc_pll; 166 167 mach_reset = q40_reset; 168 mach_get_model = q40_get_model; 169 170 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) 171 mach_beep = q40_mksound; 172 #endif 173 #ifdef CONFIG_HEARTBEAT 174 mach_heartbeat = q40_heartbeat; 175 #endif 176 mach_halt = q40_halt; 177 178 /* disable a few things that SMSQ might have left enabled */ 179 q40_disable_irqs(); 180 } 181 182 183 int __init q40_parse_bootinfo(const struct bi_record *rec) 184 { 185 return 1; 186 } 187 188 /* 189 * Looks like op is non-zero for setting the clock, and zero for 190 * reading the clock. 191 * 192 * struct hwclk_time { 193 * unsigned sec; 0..59 194 * unsigned min; 0..59 195 * unsigned hour; 0..23 196 * unsigned day; 1..31 197 * unsigned mon; 0..11 198 * unsigned year; 00... 199 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 200 * }; 201 */ 202 203 static int q40_hwclk(int op, struct rtc_time *t) 204 { 205 if (op) { 206 /* Write.... */ 207 Q40_RTC_CTRL |= Q40_RTC_WRITE; 208 209 Q40_RTC_SECS = bin2bcd(t->tm_sec); 210 Q40_RTC_MINS = bin2bcd(t->tm_min); 211 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 212 Q40_RTC_DATE = bin2bcd(t->tm_mday); 213 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 214 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 215 if (t->tm_wday >= 0) 216 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 217 218 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 219 } else { 220 /* Read.... */ 221 Q40_RTC_CTRL |= Q40_RTC_READ; 222 223 t->tm_year = bcd2bin (Q40_RTC_YEAR); 224 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 225 t->tm_mday = bcd2bin (Q40_RTC_DATE); 226 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 227 t->tm_min = bcd2bin (Q40_RTC_MINS); 228 t->tm_sec = bcd2bin (Q40_RTC_SECS); 229 230 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 231 232 if (t->tm_year < 70) 233 t->tm_year += 100; 234 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 235 } 236 237 return 0; 238 } 239 240 /* get and set PLL calibration of RTC clock */ 241 #define Q40_RTC_PLL_MASK ((1<<5)-1) 242 #define Q40_RTC_PLL_SIGN (1<<5) 243 244 static int q40_get_rtc_pll(struct rtc_pll_info *pll) 245 { 246 int tmp = Q40_RTC_CTRL; 247 248 pll->pll_ctrl = 0; 249 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 250 if (tmp & Q40_RTC_PLL_SIGN) 251 pll->pll_value = -pll->pll_value; 252 pll->pll_max = 31; 253 pll->pll_min = -31; 254 pll->pll_posmult = 512; 255 pll->pll_negmult = 256; 256 pll->pll_clock = 125829120; 257 258 return 0; 259 } 260 261 static int q40_set_rtc_pll(struct rtc_pll_info *pll) 262 { 263 if (!pll->pll_ctrl) { 264 /* the docs are a bit unclear so I am doublesetting */ 265 /* RTC_WRITE here ... */ 266 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 267 Q40_RTC_WRITE; 268 Q40_RTC_CTRL |= Q40_RTC_WRITE; 269 Q40_RTC_CTRL = tmp; 270 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 271 return 0; 272 } else 273 return -EINVAL; 274 } 275 276 #define PCIDE_BASE1 0x1f0 277 #define PCIDE_BASE2 0x170 278 #define PCIDE_CTL 0x206 279 280 static const struct resource q40_pata_rsrc_0[] __initconst = { 281 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38), 282 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2), 283 DEFINE_RES_IO(PCIDE_BASE1, 8), 284 DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1), 285 DEFINE_RES_IRQ(14), 286 }; 287 288 static const struct resource q40_pata_rsrc_1[] __initconst = { 289 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38), 290 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2), 291 DEFINE_RES_IO(PCIDE_BASE2, 8), 292 DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1), 293 DEFINE_RES_IRQ(15), 294 }; 295 296 static __init int q40_platform_init(void) 297 { 298 if (!MACH_IS_Q40) 299 return -ENODEV; 300 301 platform_device_register_simple("q40kbd", -1, NULL, 0); 302 303 platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0, 304 ARRAY_SIZE(q40_pata_rsrc_0)); 305 306 platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1, 307 ARRAY_SIZE(q40_pata_rsrc_1)); 308 309 return 0; 310 } 311 arch_initcall(q40_platform_init); 312