1 /* 2 * arch/m68k/mvme16x/config.c 3 * 4 * Copyright (C) 1995 Richard Hirst [richard@sleepie.demon.co.uk] 5 * 6 * Based on: 7 * 8 * linux/amiga/config.c 9 * 10 * Copyright (C) 1993 Hamish Macdonald 11 * 12 * This file is subject to the terms and conditions of the GNU General Public 13 * License. See the file README.legal in the main directory of this archive 14 * for more details. 15 */ 16 17 #include <linux/types.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/seq_file.h> 21 #include <linux/tty.h> 22 #include <linux/clocksource.h> 23 #include <linux/console.h> 24 #include <linux/linkage.h> 25 #include <linux/init.h> 26 #include <linux/major.h> 27 #include <linux/rtc.h> 28 #include <linux/interrupt.h> 29 #include <linux/module.h> 30 31 #include <asm/bootinfo.h> 32 #include <asm/bootinfo-vme.h> 33 #include <asm/byteorder.h> 34 #include <asm/setup.h> 35 #include <asm/irq.h> 36 #include <asm/traps.h> 37 #include <asm/machdep.h> 38 #include <asm/mvme16xhw.h> 39 40 extern t_bdid mvme_bdid; 41 42 static MK48T08ptr_t volatile rtc = (MK48T08ptr_t)MVME_RTC_BASE; 43 44 static void mvme16x_get_model(char *model); 45 extern void mvme16x_sched_init(void); 46 extern int mvme16x_hwclk (int, struct rtc_time *); 47 extern void mvme16x_reset (void); 48 49 int bcd2int (unsigned char b); 50 51 52 unsigned short mvme16x_config; 53 EXPORT_SYMBOL(mvme16x_config); 54 55 56 int __init mvme16x_parse_bootinfo(const struct bi_record *bi) 57 { 58 uint16_t tag = be16_to_cpu(bi->tag); 59 if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO) 60 return 0; 61 else 62 return 1; 63 } 64 65 void mvme16x_reset(void) 66 { 67 pr_info("\r\n\nCalled mvme16x_reset\r\n" 68 "\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r"); 69 /* The string of returns is to delay the reset until the whole 70 * message is output. Assert reset bit in GCSR */ 71 *(volatile char *)0xfff40107 = 0x80; 72 } 73 74 static void mvme16x_get_model(char *model) 75 { 76 p_bdid p = &mvme_bdid; 77 char suf[4]; 78 79 suf[1] = p->brdsuffix[0]; 80 suf[2] = p->brdsuffix[1]; 81 suf[3] = '\0'; 82 suf[0] = suf[1] ? '-' : '\0'; 83 84 sprintf(model, "Motorola MVME%x%s", be16_to_cpu(p->brdno), suf); 85 } 86 87 88 static void mvme16x_get_hardware_list(struct seq_file *m) 89 { 90 uint16_t brdno = be16_to_cpu(mvme_bdid.brdno); 91 92 if (brdno == 0x0162 || brdno == 0x0172) 93 { 94 unsigned char rev = *(unsigned char *)MVME162_VERSION_REG; 95 96 seq_printf (m, "VMEchip2 %spresent\n", 97 rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : ""); 98 seq_printf (m, "SCSI interface %spresent\n", 99 rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : ""); 100 seq_printf (m, "Ethernet i/f %spresent\n", 101 rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : ""); 102 } 103 } 104 105 /* 106 * This function is called during kernel startup to initialize 107 * the mvme16x IRQ handling routines. Should probably ensure 108 * that the base vectors for the VMEChip2 and PCCChip2 are valid. 109 */ 110 111 static void __init mvme16x_init_IRQ (void) 112 { 113 m68k_setup_user_interrupt(VEC_USER, 192); 114 } 115 116 #define PCC2CHIP (0xfff42000) 117 #define PCCSCCMICR (PCC2CHIP + 0x1d) 118 #define PCCSCCTICR (PCC2CHIP + 0x1e) 119 #define PCCSCCRICR (PCC2CHIP + 0x1f) 120 #define PCCTPIACKR (PCC2CHIP + 0x25) 121 122 #ifdef CONFIG_EARLY_PRINTK 123 124 /**** cd2401 registers ****/ 125 #define CD2401_ADDR (0xfff45000) 126 127 #define CyGFRCR (0x81) 128 #define CyCCR (0x13) 129 #define CyCLR_CHAN (0x40) 130 #define CyINIT_CHAN (0x20) 131 #define CyCHIP_RESET (0x10) 132 #define CyENB_XMTR (0x08) 133 #define CyDIS_XMTR (0x04) 134 #define CyENB_RCVR (0x02) 135 #define CyDIS_RCVR (0x01) 136 #define CyCAR (0xee) 137 #define CyIER (0x11) 138 #define CyMdmCh (0x80) 139 #define CyRxExc (0x20) 140 #define CyRxData (0x08) 141 #define CyTxMpty (0x02) 142 #define CyTxRdy (0x01) 143 #define CyLICR (0x26) 144 #define CyRISR (0x89) 145 #define CyTIMEOUT (0x80) 146 #define CySPECHAR (0x70) 147 #define CyOVERRUN (0x08) 148 #define CyPARITY (0x04) 149 #define CyFRAME (0x02) 150 #define CyBREAK (0x01) 151 #define CyREOIR (0x84) 152 #define CyTEOIR (0x85) 153 #define CyMEOIR (0x86) 154 #define CyNOTRANS (0x08) 155 #define CyRFOC (0x30) 156 #define CyRDR (0xf8) 157 #define CyTDR (0xf8) 158 #define CyMISR (0x8b) 159 #define CyRISR (0x89) 160 #define CyTISR (0x8a) 161 #define CyMSVR1 (0xde) 162 #define CyMSVR2 (0xdf) 163 #define CyDSR (0x80) 164 #define CyDCD (0x40) 165 #define CyCTS (0x20) 166 #define CyDTR (0x02) 167 #define CyRTS (0x01) 168 #define CyRTPRL (0x25) 169 #define CyRTPRH (0x24) 170 #define CyCOR1 (0x10) 171 #define CyPARITY_NONE (0x00) 172 #define CyPARITY_E (0x40) 173 #define CyPARITY_O (0xC0) 174 #define Cy_5_BITS (0x04) 175 #define Cy_6_BITS (0x05) 176 #define Cy_7_BITS (0x06) 177 #define Cy_8_BITS (0x07) 178 #define CyCOR2 (0x17) 179 #define CyETC (0x20) 180 #define CyCtsAE (0x02) 181 #define CyCOR3 (0x16) 182 #define Cy_1_STOP (0x02) 183 #define Cy_2_STOP (0x04) 184 #define CyCOR4 (0x15) 185 #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */ 186 #define CyCOR5 (0x14) 187 #define CyCOR6 (0x18) 188 #define CyCOR7 (0x07) 189 #define CyRBPR (0xcb) 190 #define CyRCOR (0xc8) 191 #define CyTBPR (0xc3) 192 #define CyTCOR (0xc0) 193 #define CySCHR1 (0x1f) 194 #define CySCHR2 (0x1e) 195 #define CyTPR (0xda) 196 #define CyPILR1 (0xe3) 197 #define CyPILR2 (0xe0) 198 #define CyPILR3 (0xe1) 199 #define CyCMR (0x1b) 200 #define CyASYNC (0x02) 201 #define CyLICR (0x26) 202 #define CyLIVR (0x09) 203 #define CySCRL (0x23) 204 #define CySCRH (0x22) 205 #define CyTFTC (0x80) 206 207 void mvme16x_cons_write(struct console *co, const char *str, unsigned count) 208 { 209 volatile unsigned char *base_addr = (u_char *)CD2401_ADDR; 210 volatile u_char sink; 211 u_char ier; 212 int port; 213 u_char do_lf = 0; 214 int i = 0; 215 216 /* Ensure transmitter is enabled! */ 217 218 port = 0; 219 base_addr[CyCAR] = (u_char)port; 220 while (base_addr[CyCCR]) 221 ; 222 base_addr[CyCCR] = CyENB_XMTR; 223 224 ier = base_addr[CyIER]; 225 base_addr[CyIER] = CyTxMpty; 226 227 while (1) { 228 if (in_8(PCCSCCTICR) & 0x20) 229 { 230 /* We have a Tx int. Acknowledge it */ 231 sink = in_8(PCCTPIACKR); 232 if ((base_addr[CyLICR] >> 2) == port) { 233 if (i == count) { 234 /* Last char of string is now output */ 235 base_addr[CyTEOIR] = CyNOTRANS; 236 break; 237 } 238 if (do_lf) { 239 base_addr[CyTDR] = '\n'; 240 str++; 241 i++; 242 do_lf = 0; 243 } 244 else if (*str == '\n') { 245 base_addr[CyTDR] = '\r'; 246 do_lf = 1; 247 } 248 else { 249 base_addr[CyTDR] = *str++; 250 i++; 251 } 252 base_addr[CyTEOIR] = 0; 253 } 254 else 255 base_addr[CyTEOIR] = CyNOTRANS; 256 } 257 } 258 259 base_addr[CyIER] = ier; 260 } 261 262 #endif 263 264 void __init config_mvme16x(void) 265 { 266 p_bdid p = &mvme_bdid; 267 char id[40]; 268 uint16_t brdno = be16_to_cpu(p->brdno); 269 270 mach_sched_init = mvme16x_sched_init; 271 mach_init_IRQ = mvme16x_init_IRQ; 272 mach_hwclk = mvme16x_hwclk; 273 mach_reset = mvme16x_reset; 274 mach_get_model = mvme16x_get_model; 275 mach_get_hardware_list = mvme16x_get_hardware_list; 276 277 /* Report board revision */ 278 279 if (strncmp("BDID", p->bdid, 4)) 280 { 281 pr_crit("Bug call .BRD_ID returned garbage - giving up\n"); 282 while (1) 283 ; 284 } 285 /* Board type is only set by newer versions of vmelilo/tftplilo */ 286 if (vme_brdtype == 0) 287 vme_brdtype = brdno; 288 289 mvme16x_get_model(id); 290 pr_info("BRD_ID: %s BUG %x.%x %02x/%02x/%02x\n", id, p->rev >> 4, 291 p->rev & 0xf, p->yr, p->mth, p->day); 292 if (brdno == 0x0162 || brdno == 0x172) 293 { 294 unsigned char rev = *(unsigned char *)MVME162_VERSION_REG; 295 296 mvme16x_config = rev | MVME16x_CONFIG_GOT_SCCA; 297 298 pr_info("MVME%x Hardware status:\n", brdno); 299 pr_info(" CPU Type 68%s040\n", 300 rev & MVME16x_CONFIG_GOT_FPU ? "" : "LC"); 301 pr_info(" CPU clock %dMHz\n", 302 rev & MVME16x_CONFIG_SPEED_32 ? 32 : 25); 303 pr_info(" VMEchip2 %spresent\n", 304 rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : ""); 305 pr_info(" SCSI interface %spresent\n", 306 rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : ""); 307 pr_info(" Ethernet interface %spresent\n", 308 rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : ""); 309 } 310 else 311 { 312 mvme16x_config = MVME16x_CONFIG_GOT_LP | MVME16x_CONFIG_GOT_CD2401; 313 } 314 } 315 316 static irqreturn_t mvme16x_abort_int (int irq, void *dev_id) 317 { 318 unsigned long *new = (unsigned long *)vectors; 319 unsigned long *old = (unsigned long *)0xffe00000; 320 volatile unsigned char uc, *ucp; 321 uint16_t brdno = be16_to_cpu(mvme_bdid.brdno); 322 323 if (brdno == 0x0162 || brdno == 0x172) 324 { 325 ucp = (volatile unsigned char *)0xfff42043; 326 uc = *ucp | 8; 327 *ucp = uc; 328 } 329 else 330 { 331 *(volatile unsigned long *)0xfff40074 = 0x40000000; 332 } 333 *(new+4) = *(old+4); /* Illegal instruction */ 334 *(new+9) = *(old+9); /* Trace */ 335 *(new+47) = *(old+47); /* Trap #15 */ 336 337 if (brdno == 0x0162 || brdno == 0x172) 338 *(new+0x5e) = *(old+0x5e); /* ABORT switch */ 339 else 340 *(new+0x6e) = *(old+0x6e); /* ABORT switch */ 341 return IRQ_HANDLED; 342 } 343 344 static u64 mvme16x_read_clk(struct clocksource *cs); 345 346 static struct clocksource mvme16x_clk = { 347 .name = "pcc", 348 .rating = 250, 349 .read = mvme16x_read_clk, 350 .mask = CLOCKSOURCE_MASK(32), 351 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 352 }; 353 354 static u32 clk_total; 355 356 #define PCC_TIMER_CLOCK_FREQ 1000000 357 #define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ) 358 359 #define PCCTCMP1 (PCC2CHIP + 0x04) 360 #define PCCTCNT1 (PCC2CHIP + 0x08) 361 #define PCCTOVR1 (PCC2CHIP + 0x17) 362 #define PCCTIC1 (PCC2CHIP + 0x1b) 363 364 #define PCCTOVR1_TIC_EN 0x01 365 #define PCCTOVR1_COC_EN 0x02 366 #define PCCTOVR1_OVR_CLR 0x04 367 368 #define PCCTIC1_INT_LEVEL 6 369 #define PCCTIC1_INT_CLR 0x08 370 #define PCCTIC1_INT_EN 0x10 371 372 static irqreturn_t mvme16x_timer_int (int irq, void *dev_id) 373 { 374 unsigned long flags; 375 376 local_irq_save(flags); 377 out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN); 378 out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL); 379 clk_total += PCC_TIMER_CYCLES; 380 legacy_timer_tick(1); 381 local_irq_restore(flags); 382 383 return IRQ_HANDLED; 384 } 385 386 void mvme16x_sched_init(void) 387 { 388 uint16_t brdno = be16_to_cpu(mvme_bdid.brdno); 389 int irq; 390 391 /* Using PCCchip2 or MC2 chip tick timer 1 */ 392 if (request_irq(MVME16x_IRQ_TIMER, mvme16x_timer_int, IRQF_TIMER, "timer", 393 NULL)) 394 panic ("Couldn't register timer int"); 395 396 out_be32(PCCTCNT1, 0); 397 out_be32(PCCTCMP1, PCC_TIMER_CYCLES); 398 out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN); 399 out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL); 400 401 clocksource_register_hz(&mvme16x_clk, PCC_TIMER_CLOCK_FREQ); 402 403 if (brdno == 0x0162 || brdno == 0x172) 404 irq = MVME162_IRQ_ABORT; 405 else 406 irq = MVME167_IRQ_ABORT; 407 if (request_irq(irq, mvme16x_abort_int, 0, 408 "abort", mvme16x_abort_int)) 409 panic ("Couldn't register abort int"); 410 } 411 412 static u64 mvme16x_read_clk(struct clocksource *cs) 413 { 414 unsigned long flags; 415 u8 overflow, tmp; 416 u32 ticks; 417 418 local_irq_save(flags); 419 tmp = in_8(PCCTOVR1) >> 4; 420 ticks = in_be32(PCCTCNT1); 421 overflow = in_8(PCCTOVR1) >> 4; 422 if (overflow != tmp) 423 ticks = in_be32(PCCTCNT1); 424 ticks += overflow * PCC_TIMER_CYCLES; 425 ticks += clk_total; 426 local_irq_restore(flags); 427 428 return ticks; 429 } 430 431 int bcd2int (unsigned char b) 432 { 433 return ((b>>4)*10 + (b&15)); 434 } 435 436 int mvme16x_hwclk(int op, struct rtc_time *t) 437 { 438 if (!op) { 439 rtc->ctrl = RTC_READ; 440 t->tm_year = bcd2int (rtc->bcd_year); 441 t->tm_mon = bcd2int(rtc->bcd_mth) - 1; 442 t->tm_mday = bcd2int (rtc->bcd_dom); 443 t->tm_hour = bcd2int (rtc->bcd_hr); 444 t->tm_min = bcd2int (rtc->bcd_min); 445 t->tm_sec = bcd2int (rtc->bcd_sec); 446 rtc->ctrl = 0; 447 if (t->tm_year < 70) 448 t->tm_year += 100; 449 } else { 450 /* FIXME Setting the time is not yet supported */ 451 return -EOPNOTSUPP; 452 } 453 return 0; 454 } 455