1*49148020SSam Ravnborg /* 2*49148020SSam Ravnborg * Q40 master Chip Control 3*49148020SSam Ravnborg * RTC stuff merged for compactnes.. 4*49148020SSam Ravnborg */ 5*49148020SSam Ravnborg 6*49148020SSam Ravnborg #ifndef _Q40_MASTER_H 7*49148020SSam Ravnborg #define _Q40_MASTER_H 8*49148020SSam Ravnborg 9*49148020SSam Ravnborg #include <asm/raw_io.h> 10*49148020SSam Ravnborg 11*49148020SSam Ravnborg 12*49148020SSam Ravnborg #define q40_master_addr 0xff000000 13*49148020SSam Ravnborg 14*49148020SSam Ravnborg #define IIRQ_REG 0x0 /* internal IRQ reg */ 15*49148020SSam Ravnborg #define EIRQ_REG 0x4 /* external ... */ 16*49148020SSam Ravnborg #define KEYCODE_REG 0x1c /* value of received scancode */ 17*49148020SSam Ravnborg #define DISPLAY_CONTROL_REG 0x18 18*49148020SSam Ravnborg #define FRAME_CLEAR_REG 0x24 19*49148020SSam Ravnborg #define LED_REG 0x30 20*49148020SSam Ravnborg 21*49148020SSam Ravnborg #define Q40_LED_ON() master_outb(1,LED_REG) 22*49148020SSam Ravnborg #define Q40_LED_OFF() master_outb(0,LED_REG) 23*49148020SSam Ravnborg 24*49148020SSam Ravnborg #define INTERRUPT_REG IIRQ_REG /* "native" ints */ 25*49148020SSam Ravnborg #define KEY_IRQ_ENABLE_REG 0x08 /**/ 26*49148020SSam Ravnborg #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */ 27*49148020SSam Ravnborg 28*49148020SSam Ravnborg #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */ 29*49148020SSam Ravnborg #define SAMPLE_RATE_REG 0x2c 30*49148020SSam Ravnborg #define SAMPLE_CLEAR_REG 0x28 31*49148020SSam Ravnborg #define SAMPLE_LOW 0x00 32*49148020SSam Ravnborg #define SAMPLE_HIGH 0x01 33*49148020SSam Ravnborg 34*49148020SSam Ravnborg #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */ 35*49148020SSam Ravnborg 36*49148020SSam Ravnborg #if 0 37*49148020SSam Ravnborg #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */ 38*49148020SSam Ravnborg #endif 39*49148020SSam Ravnborg #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */ 40*49148020SSam Ravnborg 41*49148020SSam Ravnborg 42*49148020SSam Ravnborg #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_) 43*49148020SSam Ravnborg #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_) 44*49148020SSam Ravnborg 45*49148020SSam Ravnborg /* RTC defines */ 46*49148020SSam Ravnborg 47*49148020SSam Ravnborg #define Q40_RTC_BASE (0xff021ffc) 48*49148020SSam Ravnborg 49*49148020SSam Ravnborg #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0)) 50*49148020SSam Ravnborg #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4)) 51*49148020SSam Ravnborg #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8)) 52*49148020SSam Ravnborg #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12)) 53*49148020SSam Ravnborg #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16)) 54*49148020SSam Ravnborg #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20)) 55*49148020SSam Ravnborg #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24)) 56*49148020SSam Ravnborg #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28)) 57*49148020SSam Ravnborg 58*49148020SSam Ravnborg /* some control bits */ 59*49148020SSam Ravnborg #define Q40_RTC_READ 64 /* prepare for reading */ 60*49148020SSam Ravnborg #define Q40_RTC_WRITE 128 61*49148020SSam Ravnborg 62*49148020SSam Ravnborg /* define some Q40 specific ints */ 63*49148020SSam Ravnborg #include "q40ints.h" 64*49148020SSam Ravnborg 65*49148020SSam Ravnborg /* misc defs */ 66*49148020SSam Ravnborg #define DAC_LEFT ((unsigned char *)0xff008000) 67*49148020SSam Ravnborg #define DAC_RIGHT ((unsigned char *)0xff008004) 68*49148020SSam Ravnborg 69*49148020SSam Ravnborg #endif /* _Q40_MASTER_H */ 70