1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _MVME147HW_H_ 3 #define _MVME147HW_H_ 4 5 #include <asm/irq.h> 6 7 #define MVME147_RTC_BASE 0xfffe0000 8 9 struct pcc_regs { 10 volatile u_long dma_tadr; 11 volatile u_long dma_dadr; 12 volatile u_long dma_bcr; 13 volatile u_long dma_hr; 14 volatile u_short t1_preload; 15 volatile u_short t1_count; 16 volatile u_short t2_preload; 17 volatile u_short t2_count; 18 volatile u_char t1_int_cntrl; 19 volatile u_char t1_cntrl; 20 volatile u_char t2_int_cntrl; 21 volatile u_char t2_cntrl; 22 volatile u_char ac_fail; 23 volatile u_char watchdog; 24 volatile u_char lpt_intr; 25 volatile u_char lpt_cntrl; 26 volatile u_char dma_intr; 27 volatile u_char dma_cntrl; 28 volatile u_char bus_error; 29 volatile u_char dma_status; 30 volatile u_char abort; 31 volatile u_char ta_fnctl; 32 volatile u_char serial_cntrl; 33 volatile u_char general_cntrl; 34 volatile u_char lan_cntrl; 35 volatile u_char general_status; 36 volatile u_char scsi_interrupt; 37 volatile u_char slave; 38 volatile u_char soft1_cntrl; 39 volatile u_char int_base; 40 volatile u_char soft2_cntrl; 41 volatile u_char revision_level; 42 volatile u_char lpt_data; 43 volatile u_char lpt_status; 44 }; 45 46 #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000) 47 48 49 #define PCC_INT_ENAB 0x08 50 51 #define PCC_TIMER_INT_CLR 0x80 52 53 #define PCC_TIMER_TIC_EN 0x01 54 #define PCC_TIMER_COC_EN 0x02 55 #define PCC_TIMER_CLR_OVF 0x04 56 57 #define PCC_LEVEL_ABORT 0x07 58 #define PCC_LEVEL_SERIAL 0x04 59 #define PCC_LEVEL_ETH 0x04 60 #define PCC_LEVEL_TIMER1 0x04 61 #define PCC_LEVEL_SCSI_PORT 0x04 62 #define PCC_LEVEL_SCSI_DMA 0x04 63 64 #define PCC_IRQ_AC_FAIL (IRQ_USER+0) 65 #define PCC_IRQ_BERR (IRQ_USER+1) 66 #define PCC_IRQ_ABORT (IRQ_USER+2) 67 /* #define PCC_IRQ_SERIAL (IRQ_USER+3) */ 68 #define PCC_IRQ_PRINTER (IRQ_USER+7) 69 #define PCC_IRQ_TIMER1 (IRQ_USER+8) 70 #define PCC_IRQ_TIMER2 (IRQ_USER+9) 71 #define PCC_IRQ_SOFTWARE1 (IRQ_USER+10) 72 #define PCC_IRQ_SOFTWARE2 (IRQ_USER+11) 73 74 75 #define M147_SCC_A_ADDR 0xfffe3002 76 #define M147_SCC_B_ADDR 0xfffe3000 77 #define M147_SCC_PCLK 5000000 78 79 #define MVME147_IRQ_SCSI_PORT (IRQ_USER + 5) 80 #define MVME147_IRQ_SCSI_DMA (IRQ_USER + 6) 81 82 /* SCC interrupts, for MVME147 */ 83 84 #define MVME147_IRQ_TYPE_PRIO 0 85 #define MVME147_IRQ_SCC_BASE (IRQ_USER+32) 86 #define MVME147_IRQ_SCCB_TX (IRQ_USER+32) 87 #define MVME147_IRQ_SCCB_STAT (IRQ_USER+34) 88 #define MVME147_IRQ_SCCB_RX (IRQ_USER+36) 89 #define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38) 90 #define MVME147_IRQ_SCCA_TX (IRQ_USER+40) 91 #define MVME147_IRQ_SCCA_STAT (IRQ_USER+42) 92 #define MVME147_IRQ_SCCA_RX (IRQ_USER+44) 93 #define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46) 94 95 #define MVME147_LANCE_BASE 0xfffe1800 96 #define MVME147_LANCE_IRQ (IRQ_USER+4) 97 98 #define ETHERNET_ADDRESS 0xfffe0778 99 100 #endif 101