1 /****************************************************************************/ 2 3 /* 4 * mcfuart.h -- ColdFire internal UART support defines. 5 * 6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 */ 9 10 /****************************************************************************/ 11 #ifndef mcfuart_h 12 #define mcfuart_h 13 /****************************************************************************/ 14 15 #include <linux/serial_core.h> 16 #include <linux/platform_device.h> 17 18 struct mcf_platform_uart { 19 unsigned long mapbase; /* Physical address base */ 20 void __iomem *membase; /* Virtual address if mapped */ 21 unsigned int irq; /* Interrupt vector */ 22 unsigned int uartclk; /* UART clock rate */ 23 }; 24 25 /* 26 * Define the ColdFire UART register set addresses. 27 */ 28 #define MCFUART_UMR 0x00 /* Mode register (r/w) */ 29 #define MCFUART_USR 0x04 /* Status register (r) */ 30 #define MCFUART_UCSR 0x04 /* Clock Select (w) */ 31 #define MCFUART_UCR 0x08 /* Command register (w) */ 32 #define MCFUART_URB 0x0c /* Receiver Buffer (r) */ 33 #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ 34 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ 35 #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ 36 #define MCFUART_UISR 0x14 /* Interrupt Status (r) */ 37 #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ 38 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ 39 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ 40 #ifdef CONFIG_M5272 41 #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 42 #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 43 #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 44 #endif 45 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 46 defined(CONFIG_M5249) || defined(CONFIG_M5307) || \ 47 defined(CONFIG_M5407) 48 #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 49 #endif 50 #define MCFUART_UIPR 0x34 /* Input Port (r) */ 51 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ 52 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ 53 54 55 /* 56 * Define bit flags in Mode Register 1 (MR1). 57 */ 58 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ 59 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ 60 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ 61 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ 62 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ 63 64 #define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ 65 #define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ 66 #define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ 67 #define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ 68 #define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ 69 70 #define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ 71 #define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ 72 #define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ 73 #define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ 74 75 /* 76 * Define bit flags in Mode Register 2 (MR2). 77 */ 78 #define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ 79 #define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ 80 #define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ 81 #define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ 82 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ 83 84 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ 85 #define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ 86 #define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ 87 88 /* 89 * Define bit flags in Status Register (USR). 90 */ 91 #define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ 92 #define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ 93 #define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ 94 #define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ 95 #define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ 96 #define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ 97 #define MCFUART_USR_RXFULL 0x02 /* Receiver full */ 98 #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ 99 100 #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ 101 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) 102 103 /* 104 * Define bit flags in Clock Select Register (UCSR). 105 */ 106 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ 107 #define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ 108 #define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ 109 110 #define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ 111 #define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ 112 #define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ 113 114 /* 115 * Define bit flags in Command Register (UCR). 116 */ 117 #define MCFUART_UCR_CMDNULL 0x00 /* No command */ 118 #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ 119 #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ 120 #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ 121 #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ 122 #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ 123 #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ 124 #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ 125 126 #define MCFUART_UCR_TXNULL 0x00 /* No TX command */ 127 #define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ 128 #define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ 129 #define MCFUART_UCR_RXNULL 0x00 /* No RX command */ 130 #define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ 131 #define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ 132 133 /* 134 * Define bit flags in Input Port Change Register (UIPCR). 135 */ 136 #define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ 137 #define MCFUART_UIPCR_CTS 0x01 /* CTS value */ 138 139 /* 140 * Define bit flags in Input Port Register (UIP). 141 */ 142 #define MCFUART_UIPR_CTS 0x01 /* CTS value */ 143 144 /* 145 * Define bit flags in Output Port Registers (UOP). 146 * Clear bit by writing to UOP0, set by writing to UOP1. 147 */ 148 #define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ 149 150 /* 151 * Define bit flags in the Auxiliary Control Register (UACR). 152 */ 153 #define MCFUART_UACR_IEC 0x01 /* Input enable control */ 154 155 /* 156 * Define bit flags in Interrupt Status Register (UISR). 157 * These same bits are used for the Interrupt Mask Register (UIMR). 158 */ 159 #define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ 160 #define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ 161 #define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ 162 #define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ 163 164 #ifdef CONFIG_M5272 165 /* 166 * Define bit flags in the Transmitter FIFO Register (UTF). 167 */ 168 #define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ 169 #define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ 170 #define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ 171 172 /* 173 * Define bit flags in the Receiver FIFO Register (URF). 174 */ 175 #define MCFUART_URF_RXB 0x1f /* Receiver data level */ 176 #define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ 177 #define MCFUART_URF_RXS 0xc0 /* Receiver status */ 178 #endif 179 180 #if defined(CONFIG_M54xx) 181 #define MCFUART_TXFIFOSIZE 512 182 #elif defined(CONFIG_M5272) 183 #define MCFUART_TXFIFOSIZE 25 184 #else 185 #define MCFUART_TXFIFOSIZE 1 186 #endif 187 /****************************************************************************/ 188 #endif /* mcfuart_h */ 189