149148020SSam Ravnborg /* 249148020SSam Ravnborg ** macints.h -- Macintosh Linux interrupt handling structs and prototypes 349148020SSam Ravnborg ** 449148020SSam Ravnborg ** Copyright 1997 by Michael Schmitz 549148020SSam Ravnborg ** 649148020SSam Ravnborg ** This file is subject to the terms and conditions of the GNU General Public 749148020SSam Ravnborg ** License. See the file COPYING in the main directory of this archive 849148020SSam Ravnborg ** for more details. 949148020SSam Ravnborg ** 1049148020SSam Ravnborg */ 1149148020SSam Ravnborg 1249148020SSam Ravnborg #ifndef _ASM_MACINTS_H_ 1349148020SSam Ravnborg #define _ASM_MACINTS_H_ 1449148020SSam Ravnborg 1549148020SSam Ravnborg #include <asm/irq.h> 1649148020SSam Ravnborg 1749148020SSam Ravnborg /* 1849148020SSam Ravnborg * Base IRQ number for all Mac68K interrupt sources. Each source 1949148020SSam Ravnborg * has eight indexes (base -> base+7). 2049148020SSam Ravnborg */ 2149148020SSam Ravnborg 2249148020SSam Ravnborg #define VIA1_SOURCE_BASE 8 2349148020SSam Ravnborg #define VIA2_SOURCE_BASE 16 2449148020SSam Ravnborg #define PSC3_SOURCE_BASE 24 2549148020SSam Ravnborg #define PSC4_SOURCE_BASE 32 2649148020SSam Ravnborg #define PSC5_SOURCE_BASE 40 2749148020SSam Ravnborg #define PSC6_SOURCE_BASE 48 2849148020SSam Ravnborg #define NUBUS_SOURCE_BASE 56 2949148020SSam Ravnborg #define BABOON_SOURCE_BASE 64 3049148020SSam Ravnborg 3149148020SSam Ravnborg /* 3249148020SSam Ravnborg * Maximum IRQ number is BABOON_SOURCE_BASE + 7, 3349148020SSam Ravnborg * giving us IRQs up through 71 3449148020SSam Ravnborg */ 3549148020SSam Ravnborg 3649148020SSam Ravnborg #define NUM_MAC_SOURCES 72 3749148020SSam Ravnborg 3849148020SSam Ravnborg /* 3949148020SSam Ravnborg * clean way to separate IRQ into its source and index 4049148020SSam Ravnborg */ 4149148020SSam Ravnborg 4249148020SSam Ravnborg #define IRQ_SRC(irq) (irq >> 3) 4349148020SSam Ravnborg #define IRQ_IDX(irq) (irq & 7) 4449148020SSam Ravnborg 4549148020SSam Ravnborg /* VIA1 interrupts */ 4649148020SSam Ravnborg #define IRQ_VIA1_0 (8) /* one second int. */ 4749148020SSam Ravnborg #define IRQ_VIA1_1 (9) /* VBlank int. */ 4849148020SSam Ravnborg #define IRQ_MAC_VBL IRQ_VIA1_1 4949148020SSam Ravnborg #define IRQ_VIA1_2 (10) /* ADB SR shifts complete */ 5049148020SSam Ravnborg #define IRQ_MAC_ADB IRQ_VIA1_2 5149148020SSam Ravnborg #define IRQ_MAC_ADB_SR IRQ_VIA1_2 5249148020SSam Ravnborg #define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */ 5349148020SSam Ravnborg #define IRQ_MAC_ADB_SD IRQ_VIA1_3 5449148020SSam Ravnborg #define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */ 5549148020SSam Ravnborg #define IRQ_MAC_ADB_CL IRQ_VIA1_4 5649148020SSam Ravnborg #define IRQ_VIA1_5 (13) 5749148020SSam Ravnborg #define IRQ_MAC_TIMER_2 IRQ_VIA1_5 5849148020SSam Ravnborg #define IRQ_VIA1_6 (14) 5949148020SSam Ravnborg #define IRQ_MAC_TIMER_1 IRQ_VIA1_6 6049148020SSam Ravnborg #define IRQ_VIA1_7 (15) 6149148020SSam Ravnborg 6249148020SSam Ravnborg /* VIA2/RBV interrupts */ 6349148020SSam Ravnborg #define IRQ_VIA2_0 (16) 6449148020SSam Ravnborg #define IRQ_MAC_SCSIDRQ IRQ_VIA2_0 6549148020SSam Ravnborg #define IRQ_VIA2_1 (17) 6649148020SSam Ravnborg #define IRQ_MAC_NUBUS IRQ_VIA2_1 6749148020SSam Ravnborg #define IRQ_VIA2_2 (18) 6849148020SSam Ravnborg #define IRQ_VIA2_3 (19) 6949148020SSam Ravnborg #define IRQ_MAC_SCSI IRQ_VIA2_3 7049148020SSam Ravnborg #define IRQ_VIA2_4 (20) 7149148020SSam Ravnborg #define IRQ_VIA2_5 (21) 7249148020SSam Ravnborg #define IRQ_VIA2_6 (22) 7349148020SSam Ravnborg #define IRQ_VIA2_7 (23) 7449148020SSam Ravnborg 7549148020SSam Ravnborg /* Level 3 (PSC, AV Macs only) interrupts */ 7649148020SSam Ravnborg #define IRQ_PSC3_0 (24) 7749148020SSam Ravnborg #define IRQ_MAC_MACE IRQ_PSC3_0 7849148020SSam Ravnborg #define IRQ_PSC3_1 (25) 7949148020SSam Ravnborg #define IRQ_PSC3_2 (26) 8049148020SSam Ravnborg #define IRQ_PSC3_3 (27) 8149148020SSam Ravnborg 8249148020SSam Ravnborg /* Level 4 (PSC, AV Macs only) interrupts */ 8349148020SSam Ravnborg #define IRQ_PSC4_0 (32) 8449148020SSam Ravnborg #define IRQ_PSC4_1 (33) 8580614e5aSFinn Thain #define IRQ_MAC_SCC_A IRQ_PSC4_1 8649148020SSam Ravnborg #define IRQ_PSC4_2 (34) 8780614e5aSFinn Thain #define IRQ_MAC_SCC_B IRQ_PSC4_2 8849148020SSam Ravnborg #define IRQ_PSC4_3 (35) 8949148020SSam Ravnborg #define IRQ_MAC_MACE_DMA IRQ_PSC4_3 9049148020SSam Ravnborg 91*da3fb3c9SFinn Thain /* OSS Level 4 interrupts */ 92*da3fb3c9SFinn Thain #define IRQ_MAC_SCC (33) 93*da3fb3c9SFinn Thain 9449148020SSam Ravnborg /* Level 5 (PSC, AV Macs only) interrupts */ 9549148020SSam Ravnborg #define IRQ_PSC5_0 (40) 9649148020SSam Ravnborg #define IRQ_PSC5_1 (41) 9749148020SSam Ravnborg #define IRQ_PSC5_2 (42) 9849148020SSam Ravnborg #define IRQ_PSC5_3 (43) 9949148020SSam Ravnborg 10049148020SSam Ravnborg /* Level 6 (PSC, AV Macs only) interrupts */ 10149148020SSam Ravnborg #define IRQ_PSC6_0 (48) 10249148020SSam Ravnborg #define IRQ_PSC6_1 (49) 10349148020SSam Ravnborg #define IRQ_PSC6_2 (50) 10449148020SSam Ravnborg #define IRQ_PSC6_3 (51) 10549148020SSam Ravnborg 10649148020SSam Ravnborg /* Nubus interrupts (cascaded to VIA2) */ 10749148020SSam Ravnborg #define IRQ_NUBUS_9 (56) 10849148020SSam Ravnborg #define IRQ_NUBUS_A (57) 10949148020SSam Ravnborg #define IRQ_NUBUS_B (58) 11049148020SSam Ravnborg #define IRQ_NUBUS_C (59) 11149148020SSam Ravnborg #define IRQ_NUBUS_D (60) 11249148020SSam Ravnborg #define IRQ_NUBUS_E (61) 11349148020SSam Ravnborg #define IRQ_NUBUS_F (62) 11449148020SSam Ravnborg 11549148020SSam Ravnborg /* Baboon interrupts (cascaded to nubus slot $C) */ 11649148020SSam Ravnborg #define IRQ_BABOON_0 (64) 11749148020SSam Ravnborg #define IRQ_BABOON_1 (65) 11849148020SSam Ravnborg #define IRQ_BABOON_2 (66) 11949148020SSam Ravnborg #define IRQ_BABOON_3 (67) 12049148020SSam Ravnborg 12149148020SSam Ravnborg #define SLOT2IRQ(x) (x + 47) 12249148020SSam Ravnborg #define IRQ2SLOT(x) (x - 47) 12349148020SSam Ravnborg 12449148020SSam Ravnborg #endif /* asm/macints.h */ 125