1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * 6522 Versatile Interface Adapter (VIA) 4 * 5 * There are two of these on the Mac II. Some IRQ's are vectored 6 * via them as are assorted bits and bobs - eg rtc, adb. The picture 7 * is a bit incomplete as the Mac documentation doesn't cover this well 8 */ 9 10 #ifndef _ASM_MAC_VIA_H_ 11 #define _ASM_MAC_VIA_H_ 12 13 /* 14 * Base addresses for the VIAs. There are two in every machine, 15 * although on some machines the second is an RBV or an OSS. 16 * The OSS is different enough that it's handled separately. 17 * 18 * Do not use these values directly; use the via1 and via2 variables 19 * instead (and don't forget to check rbv_present when using via2!) 20 */ 21 22 #define VIA1_BASE (0x50F00000) 23 #define VIA2_BASE (0x50F02000) 24 #define RBV_BASE (0x50F26000) 25 26 /* 27 * Not all of these are true post MacII I think. 28 * CSA: probably the ones CHRP marks as 'unused' change purposes 29 * when the IWM becomes the SWIM. 30 * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html 31 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf 32 * 33 * also, http://developer.apple.com/technotes/hw/hw_09.html claims the 34 * following changes for IIfx: 35 * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. 36 * Also, "All of the functionality of VIA2 has been moved to other chips". 37 */ 38 39 #define VIA1A_vSccWrReq 0x80 /* SCC write. (input) 40 * [CHRP] SCC WREQ: Reflects the state of the 41 * Wait/Request pins from the SCC. 42 * [Macintosh Family Hardware] 43 * as CHRP on SE/30,II,IIx,IIcx,IIci. 44 * on IIfx, "0 means an active request" 45 */ 46 #define VIA1A_vRev8 0x40 /* Revision 8 board ??? 47 * [CHRP] En WaitReqB: Lets the WaitReq_L 48 * signal from port B of the SCC appear on 49 * the PA7 input pin. Output. 50 * [Macintosh Family] On the SE/30, this 51 * is the bit to flip screen buffers. 52 * 0=alternate, 1=main. 53 * on II,IIx,IIcx,IIci,IIfx this is a bit 54 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx 55 */ 56 #define VIA1A_vHeadSel 0x20 /* Head select for IWM. 57 * [CHRP] unused. 58 * [Macintosh Family] "Floppy disk 59 * state-control line SEL" on all but IIfx 60 */ 61 #define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx 62 * this bit enables the "Overlay" address 63 * map in the address decoders as it is on 64 * reset for mapping the ROM over the reset 65 * vector. 1=use overlay map. 66 * On the IIci,IIfx it is another bit of the 67 * CPU ID: 0=normal IIci, 1=IIci with parity 68 * feature or IIfx. 69 * [CHRP] En WaitReqA: Lets the WaitReq_L 70 * signal from port A of the SCC appear 71 * on the PA7 input pin (CHRP). Output. 72 * [MkLinux] "Drive Select" 73 * (with 0x20 being 'disk head select') 74 */ 75 #define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select: 76 * 1: select the external serial clock to 77 * drive the SCC's /RTxCA pin. 78 * 0: Select the 3.6864MHz clock to drive 79 * the SCC cell. 80 * [Macintosh Family] Correct on all but IIfx 81 */ 82 83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control 84 * on Macs which had the PWM sound hardware. Reserved on newer models. 85 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: 86 * bit 2: 1=IIci, 0=IIfx 87 * bit 1: 1 on both IIci and IIfx. 88 * MkLinux sez bit 0 is 'burnin flag' in this case. 89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as 90 * inputs, these bits will read 0. 91 */ 92 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ 93 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ 94 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ 95 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ 96 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ 97 98 /* Info on VIA1B is from Macintosh Family Hardware & MkLinux. 99 * CHRP offers no info. */ 100 #define VIA1B_vSound 0x80 /* Sound enable (for compatibility with 101 * PWM hardware) 0=enabled. 102 * Also, on IIci w/parity, shows parity error 103 * 0=error, 1=OK. */ 104 #define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled 105 * On SE/30, vertical sync interrupt enable. 106 * 0=enabled. This vSync interrupt shows up 107 * as a slot $E interrupt. */ 108 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ 109 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ 110 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ 111 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ 112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ 113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ 114 115 /* MkLinux defines the following "VIA1 Register B contents where they 116 * differ from standard VIA1". From the naming scheme, we assume they 117 * correspond to a VIA work-alike named 'EVR'. */ 118 #define EVRB_XCVR 0x08 /* XCVR_SESSION* */ 119 #define EVRB_FULL 0x10 /* VIA_FULL */ 120 #define EVRB_SYSES 0x20 /* SYS_SESSION */ 121 #define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */ 122 #define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */ 123 #define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */ 124 #define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */ 125 126 /* 127 * VIA2 A register is the interrupt lines raised off the nubus 128 * slots. 129 * The below info is from 'Macintosh Family Hardware.' 130 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' 131 * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and 132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. 133 * Perhaps OSS uses vRAM1 and vRAM2 for ADB. 134 */ 135 136 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ 137 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ 138 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ 139 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ 140 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ 141 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ 142 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ 143 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ 144 145 /* RAM size bits decoded as follows: 146 * bit1 bit0 size of ICs in bank A 147 * 0 0 256 kbit 148 * 0 1 1 Mbit 149 * 1 0 4 Mbit 150 * 1 1 16 Mbit 151 */ 152 153 /* 154 * Register B has the fun stuff in it 155 */ 156 157 #define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by 158 * timer T1. 159 * on IIci, parity test: 0=test mode. 160 * [MkLinux] RBV_PARODD: 1=odd,0=even. */ 161 #define VIA2B_vSndJck 0x40 /* External sound jack status. 162 * 0=plug is inserted. On SE/30, always 0 */ 163 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ 164 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ 165 #define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush 166 * on II, AMU/PMMU control. 167 * if AMU, 0=24bit to 32bit translation 168 * if PMMU, 1=PMMU is accessing page table. 169 * on SE/30 tied low. 170 * on IIx,IIcx,IIfx, unused. 171 * on IIci/RBV, cache control. 0=flush cache. 172 */ 173 #define VIA2B_vPower 0x04 /* Power off, 0=shut off power. 174 * on SE/30 this signal sent to PDS card. */ 175 #define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked. 176 * on SE/30 sent to PDS card. */ 177 #define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card 178 * on others, 0=disable processor's instruction 179 * and data caches. */ 180 181 /* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html 182 * Another example of a valid function that has no ROM support is the use 183 * of the alternate video page for page-flipping animation. Since there 184 * is no ROM call to flip pages, it is necessary to go play with the 185 * right bit in the VIA chip (6522 Versatile Interface Adapter). 186 * [CSA: don't know which one this is, but it's one of 'em!] 187 */ 188 189 /* 190 * 6522 registers - see databook. 191 * CSA: Assignments for VIA1 confirmed from CHRP spec. 192 */ 193 194 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ 195 /* Note: 15 VIA regs, 8 RBV regs */ 196 197 #define vBufB 0x0000 /* [VIA/RBV] Register B */ 198 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ 199 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ 200 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ 201 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ 202 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ 203 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ 204 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ 205 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ 206 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ 207 #define vSR 0x1400 /* [VIA only] Shift register. */ 208 #define vACR 0x1600 /* [VIA only] Auxiliary control register. */ 209 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ 210 /* CHRP sez never ever to *write* this. 211 * Mac family says never to *change* this. 212 * In fact we need to initialize it once at start. */ 213 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ 214 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ 215 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ 216 217 /* The RBV only decodes the bottom eight address lines; the VIA doesn't 218 * decode the bottom eight -- so vBufB | rBufB will always get you BufB */ 219 /* CSA: in fact, only bits 0,1, and 4 seem to be decoded. 220 * BUT note the values for rIER and rIFR, where the top 8 bits *do* seem 221 * to matter. In fact *all* of the top 8 bits seem to matter; 222 * setting rIER=0x1813 and rIFR=0x1803 doesn't work, either. 223 * Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999] 224 */ 225 226 #define rBufB 0x0000 /* [VIA/RBV] Register B */ 227 #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */ 228 #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */ 229 #define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */ 230 #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */ 231 #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */ 232 #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */ 233 #define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */ 234 #define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */ 235 236 /* 237 * Video monitor parameters, for rMonP: 238 */ 239 #define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */ 240 #define RBV_MONID 0x38 /* monitor type, as below. */ 241 #define RBV_VIDOFF 0x40 /* 1 turns off onboard video */ 242 /* Supported monitor types: */ 243 #define MON_15BW (1<<3) /* 15" BW portrait. */ 244 #define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */ 245 #define MON_15RGB (5<<3) /* 15" RGB portrait. */ 246 #define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */ 247 #define MON_NONE (7<<3) /* No monitor attached. */ 248 249 /* To clarify IER manipulations */ 250 #define IER_SET_BIT(b) (0x80 | (1<<(b)) ) 251 #define IER_CLR_BIT(b) (0x7F & (1<<(b)) ) 252 253 #ifndef __ASSEMBLY__ 254 255 extern volatile __u8 *via1,*via2; 256 extern int rbv_present,via_alt_mapping; 257 258 struct irq_desc; 259 260 extern void via_l2_flush(int writeback); 261 extern void via_register_interrupts(void); 262 extern void via_irq_enable(int); 263 extern void via_irq_disable(int); 264 extern void via_nubus_irq_startup(int irq); 265 extern void via_nubus_irq_shutdown(int irq); 266 extern void via1_irq(struct irq_desc *desc); 267 extern void via1_set_head(int); 268 extern int via2_scsi_drq_pending(void); 269 270 static inline int rbv_set_video_bpp(int bpp) 271 { 272 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; 273 if (!rbv_present || val<0) return -1; 274 via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val; 275 return 0; 276 } 277 278 #endif /* __ASSEMBLY__ */ 279 280 #endif /* _ASM_MAC_VIA_H_ */ 281