1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a12cf0a8SGreg Ungerer /****************************************************************************/ 3a12cf0a8SGreg Ungerer 4a12cf0a8SGreg Ungerer /* 5a12cf0a8SGreg Ungerer * m52xxacr.h -- ColdFire version 2 core cache support 6a12cf0a8SGreg Ungerer * 7a12cf0a8SGreg Ungerer * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> 8a12cf0a8SGreg Ungerer */ 9a12cf0a8SGreg Ungerer 10a12cf0a8SGreg Ungerer /****************************************************************************/ 11a12cf0a8SGreg Ungerer #ifndef m52xxacr_h 12a12cf0a8SGreg Ungerer #define m52xxacr_h 13a12cf0a8SGreg Ungerer /****************************************************************************/ 14a12cf0a8SGreg Ungerer 15a12cf0a8SGreg Ungerer /* 16a12cf0a8SGreg Ungerer * All varients of the ColdFire using version 2 cores have a similar 17a12cf0a8SGreg Ungerer * cache setup. Although not absolutely identical the cache register 18a12cf0a8SGreg Ungerer * definitions are compatible for all of them. Mostly they support a 19a12cf0a8SGreg Ungerer * configurable cache memory that can be instruction only, data only, 20a12cf0a8SGreg Ungerer * or split instruction and data. The exception is the very old version 2 21a12cf0a8SGreg Ungerer * core based parts, like the 5206(e), 5249 and 5272, which are instruction 22a12cf0a8SGreg Ungerer * cache only. Cache size varies from 2k up to 16k. 23a12cf0a8SGreg Ungerer */ 24a12cf0a8SGreg Ungerer 25a12cf0a8SGreg Ungerer /* 26a12cf0a8SGreg Ungerer * Define the Cache Control register flags. 27a12cf0a8SGreg Ungerer */ 28a12cf0a8SGreg Ungerer #define CACR_CENB 0x80000000 /* Enable cache */ 29a12cf0a8SGreg Ungerer #define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ 30a12cf0a8SGreg Ungerer #define CACR_CFRZ 0x08000000 /* Cache freeze mode */ 31a12cf0a8SGreg Ungerer #define CACR_CINV 0x01000000 /* Invalidate cache */ 32a12cf0a8SGreg Ungerer #define CACR_DISI 0x00800000 /* Disable instruction cache */ 33a12cf0a8SGreg Ungerer #define CACR_DISD 0x00400000 /* Disable data cache */ 34a12cf0a8SGreg Ungerer #define CACR_INVI 0x00200000 /* Invalidate instruction cache */ 35a12cf0a8SGreg Ungerer #define CACR_INVD 0x00100000 /* Invalidate data cache */ 36a12cf0a8SGreg Ungerer #define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ 37a12cf0a8SGreg Ungerer #define CACR_DCM 0x00000200 /* Default cache mode */ 38a12cf0a8SGreg Ungerer #define CACR_DBWE 0x00000100 /* Buffered write enable */ 39a12cf0a8SGreg Ungerer #define CACR_DWP 0x00000020 /* Write protection */ 40a12cf0a8SGreg Ungerer #define CACR_EUSP 0x00000010 /* Enable separate user a7 */ 41a12cf0a8SGreg Ungerer 42a12cf0a8SGreg Ungerer /* 43a12cf0a8SGreg Ungerer * Define the Access Control register flags. 44a12cf0a8SGreg Ungerer */ 45a12cf0a8SGreg Ungerer #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ 46a12cf0a8SGreg Ungerer #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ 47a12cf0a8SGreg Ungerer #define ACR_ENABLE 0x00008000 /* Enable this ACR */ 48a12cf0a8SGreg Ungerer #define ACR_USER 0x00000000 /* Allow only user accesses */ 49a12cf0a8SGreg Ungerer #define ACR_SUPER 0x00002000 /* Allow supervisor access only */ 50a12cf0a8SGreg Ungerer #define ACR_ANY 0x00004000 /* Allow any access type */ 51a12cf0a8SGreg Ungerer #define ACR_CENB 0x00000000 /* Caching of region enabled */ 52a12cf0a8SGreg Ungerer #define ACR_CDIS 0x00000040 /* Caching of region disabled */ 53a12cf0a8SGreg Ungerer #define ACR_BWE 0x00000020 /* Write buffer enabled */ 54a12cf0a8SGreg Ungerer #define ACR_WPROTECT 0x00000004 /* Write protect region */ 55a12cf0a8SGreg Ungerer 568ce877a8SGreg Ungerer /* 570ef6c9b8SGreg Ungerer * Set the cache controller settings we will use. On the cores that support 580ef6c9b8SGreg Ungerer * a split cache configuration we allow all the combinations at Kconfig 590ef6c9b8SGreg Ungerer * time. For those cores that only have an instruction cache we just set 600ef6c9b8SGreg Ungerer * that as on. 618ce877a8SGreg Ungerer */ 620ef6c9b8SGreg Ungerer #if defined(CONFIG_CACHE_I) 6307ffee59SGreg Ungerer #define CACHE_TYPE (CACR_DISD + CACR_EUSP) 6407ffee59SGreg Ungerer #define CACHE_INVTYPEI 0 650ef6c9b8SGreg Ungerer #elif defined(CONFIG_CACHE_D) 6607ffee59SGreg Ungerer #define CACHE_TYPE (CACR_DISI + CACR_EUSP) 6707ffee59SGreg Ungerer #define CACHE_INVTYPED 0 6807ffee59SGreg Ungerer #elif defined(CONFIG_CACHE_BOTH) 6907ffee59SGreg Ungerer #define CACHE_TYPE CACR_EUSP 7007ffee59SGreg Ungerer #define CACHE_INVTYPEI CACR_INVI 7107ffee59SGreg Ungerer #define CACHE_INVTYPED CACR_INVD 720ef6c9b8SGreg Ungerer #else 7307ffee59SGreg Ungerer /* This is the instruction cache only devices (no split cache, no eusp) */ 7407ffee59SGreg Ungerer #define CACHE_TYPE 0 7507ffee59SGreg Ungerer #define CACHE_INVTYPEI 0 760ef6c9b8SGreg Ungerer #endif 770ef6c9b8SGreg Ungerer 7807ffee59SGreg Ungerer #define CACHE_INIT (CACR_CINV + CACHE_TYPE) 7907ffee59SGreg Ungerer #define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM) 808ce877a8SGreg Ungerer 818ce877a8SGreg Ungerer #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) 8207ffee59SGreg Ungerer #if defined(CACHE_INVTYPEI) 8307ffee59SGreg Ungerer #define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI) 8407ffee59SGreg Ungerer #endif 8507ffee59SGreg Ungerer #if defined(CACHE_INVTYPED) 8607ffee59SGreg Ungerer #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED) 8707ffee59SGreg Ungerer #endif 888ce877a8SGreg Ungerer 898ce877a8SGreg Ungerer #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ 908ce877a8SGreg Ungerer (0x000f0000) + \ 918ce877a8SGreg Ungerer (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) 928ce877a8SGreg Ungerer #define ACR1_MODE 0 938ce877a8SGreg Ungerer 94a12cf0a8SGreg Ungerer /****************************************************************************/ 95a12cf0a8SGreg Ungerer #endif /* m52xxsim_h */ 96