1 /****************************************************************************/ 2 3 /* 4 * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. 5 * 6 * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 7 */ 8 9 /****************************************************************************/ 10 #ifndef m528xsim_h 11 #define m528xsim_h 12 /****************************************************************************/ 13 14 15 /* 16 * Define the 5280/5282 SIM register set addresses. 17 */ 18 #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 19 #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ 20 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 21 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 22 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 23 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 24 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 25 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 26 #define MCFINTC_IRLR 0x18 /* */ 27 #define MCFINTC_IACKL 0x19 /* */ 28 #define MCFINTC_ICR0 0x40 /* Base ICR register */ 29 30 #define MCFINT_VECBASE 64 /* Vector base number */ 31 #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 32 #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 33 34 /* 35 * SDRAM configuration registers. 36 */ 37 #define MCFSIM_DCR 0x44 /* SDRAM control */ 38 #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 39 #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 40 #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 41 #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 42 43 /* 44 * Derek Cheung - 6 Feb 2005 45 * add I2C and QSPI register definition using Freescale's MCF5282 46 */ 47 /* set Port AS pin for I2C or UART */ 48 #define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056) 49 50 /* Port UA Pin Assignment Register (8 Bit) */ 51 #define MCF5282_GPIO_PUAPAR 0x10005C 52 53 /* Interrupt Mask Register Register Low */ 54 #define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C) 55 /* Interrupt Control Register 7 */ 56 #define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) 57 58 59 60 /********************************************************************* 61 * 62 * Inter-IC (I2C) Module 63 * 64 *********************************************************************/ 65 /* Read/Write access macros for general use */ 66 #define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address 67 #define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider 68 #define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control 69 #define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status 70 #define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O 71 72 /* Bit level definitions and macros */ 73 #define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) 74 75 #define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) 76 77 #define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable 78 #define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable 79 #define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode 80 #define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode 81 #define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable 82 #define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start 83 84 #define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit 85 #define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave 86 #define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy 87 #define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost 88 #define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write 89 #define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt 90 #define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge 91 92 93 94 /********************************************************************* 95 * 96 * Queued Serial Peripheral Interface (QSPI) Module 97 * 98 *********************************************************************/ 99 /* Derek - 21 Feb 2005 */ 100 /* change to the format used in I2C */ 101 /* Read/Write access macros for general use */ 102 #define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340 103 #define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344 104 #define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348 105 #define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C 106 #define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350 107 #define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354 108 #define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354 109 110 /* Bit level definitions and macros */ 111 #define MCF5282_QSPI_QMR_MSTR (0x8000) 112 #define MCF5282_QSPI_QMR_DOHIE (0x4000) 113 #define MCF5282_QSPI_QMR_BITS_16 (0x0000) 114 #define MCF5282_QSPI_QMR_BITS_8 (0x2000) 115 #define MCF5282_QSPI_QMR_BITS_9 (0x2400) 116 #define MCF5282_QSPI_QMR_BITS_10 (0x2800) 117 #define MCF5282_QSPI_QMR_BITS_11 (0x2C00) 118 #define MCF5282_QSPI_QMR_BITS_12 (0x3000) 119 #define MCF5282_QSPI_QMR_BITS_13 (0x3400) 120 #define MCF5282_QSPI_QMR_BITS_14 (0x3800) 121 #define MCF5282_QSPI_QMR_BITS_15 (0x3C00) 122 #define MCF5282_QSPI_QMR_CPOL (0x0200) 123 #define MCF5282_QSPI_QMR_CPHA (0x0100) 124 #define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) 125 126 #define MCF5282_QSPI_QDLYR_SPE (0x80) 127 #define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) 128 #define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) 129 130 #define MCF5282_QSPI_QWR_HALT (0x8000) 131 #define MCF5282_QSPI_QWR_WREN (0x4000) 132 #define MCF5282_QSPI_QWR_WRTO (0x2000) 133 #define MCF5282_QSPI_QWR_CSIV (0x1000) 134 #define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) 135 #define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) 136 #define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) 137 138 #define MCF5282_QSPI_QIR_WCEFB (0x8000) 139 #define MCF5282_QSPI_QIR_ABRTB (0x4000) 140 #define MCF5282_QSPI_QIR_ABRTL (0x1000) 141 #define MCF5282_QSPI_QIR_WCEFE (0x0800) 142 #define MCF5282_QSPI_QIR_ABRTE (0x0400) 143 #define MCF5282_QSPI_QIR_SPIFE (0x0100) 144 #define MCF5282_QSPI_QIR_WCEF (0x0008) 145 #define MCF5282_QSPI_QIR_ABRT (0x0004) 146 #define MCF5282_QSPI_QIR_SPIF (0x0001) 147 148 #define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) 149 150 #define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) 151 #define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) 152 #define MCF5282_QSPI_QCR_CONT (0x8000) 153 #define MCF5282_QSPI_QCR_BITSE (0x4000) 154 #define MCF5282_QSPI_QCR_DT (0x2000) 155 #define MCF5282_QSPI_QCR_DSCK (0x1000) 156 #define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) 157 158 /****************************************************************************/ 159 #endif /* m528xsim_h */ 160