1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 849148020SSam Ravnborg */ 949148020SSam Ravnborg 1049148020SSam Ravnborg /****************************************************************************/ 1149148020SSam Ravnborg #ifndef m528xsim_h 1249148020SSam Ravnborg #define m528xsim_h 1349148020SSam Ravnborg /****************************************************************************/ 1449148020SSam Ravnborg 157fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m528x)" 16733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 17ce3de78aSGreg Ungerer #define MCF_BUSCLK MCF_CLK 1849148020SSam Ravnborg 19a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 20a12cf0a8SGreg Ungerer 2149148020SSam Ravnborg /* 2249148020SSam Ravnborg * Define the 5280/5282 SIM register set addresses. 2349148020SSam Ravnborg */ 24254eef74SGreg Ungerer #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 25254eef74SGreg Ungerer #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ 26254eef74SGreg Ungerer 2749148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2849148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2949148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 3049148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 3149148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 3249148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 3349148020SSam Ravnborg #define MCFINTC_IRLR 0x18 /* */ 3449148020SSam Ravnborg #define MCFINTC_IACKL 0x19 /* */ 3549148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3649148020SSam Ravnborg 3749148020SSam Ravnborg #define MCFINT_VECBASE 64 /* Vector base number */ 3849148020SSam Ravnborg #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 39f8bb5327SGreg Ungerer #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 40f8bb5327SGreg Ungerer #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 412d24b532SSteven King #define MCFINT_I2C0 17 /* Interrupt number for I2C */ 4291d60417SSteven King #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 434f8f9fb8SGreg Ungerer #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ 444f8f9fb8SGreg Ungerer #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ 454f8f9fb8SGreg Ungerer #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ 4649148020SSam Ravnborg #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 4749148020SSam Ravnborg 48f8bb5327SGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 49f8bb5327SGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 50f8bb5327SGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 51f8bb5327SGreg Ungerer 524f8f9fb8SGreg Ungerer #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 534f8f9fb8SGreg Ungerer #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 544f8f9fb8SGreg Ungerer #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 554f8f9fb8SGreg Ungerer 563b2039b2SGreg Ungerer #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 57bdee4e26SSteven King #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 582d24b532SSteven King #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 592d24b532SSteven King 6049148020SSam Ravnborg /* 6149148020SSam Ravnborg * SDRAM configuration registers. 6249148020SSam Ravnborg */ 636a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ 646a92e198SGreg Ungerer #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ 656a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */ 666a92e198SGreg Ungerer #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */ 676a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */ 6849148020SSam Ravnborg 6949148020SSam Ravnborg /* 70babc08b7SGreg Ungerer * DMA unit base addresses. 71babc08b7SGreg Ungerer */ 72babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100) 73babc08b7SGreg Ungerer #define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140) 74babc08b7SGreg Ungerer #define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180) 75babc08b7SGreg Ungerer #define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0) 76babc08b7SGreg Ungerer 77babc08b7SGreg Ungerer /* 7857015421SGreg Ungerer * UART module. 7957015421SGreg Ungerer */ 80f8bb5327SGreg Ungerer #define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200) 81f8bb5327SGreg Ungerer #define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240) 82f8bb5327SGreg Ungerer #define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280) 83a0ba4332SGreg Ungerer 84a0ba4332SGreg Ungerer /* 85a0ba4332SGreg Ungerer * FEC ethernet module. 86a0ba4332SGreg Ungerer */ 874f8f9fb8SGreg Ungerer #define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) 884f8f9fb8SGreg Ungerer #define MCFFEC_SIZE0 0x800 8957015421SGreg Ungerer 9057015421SGreg Ungerer /* 913b2039b2SGreg Ungerer * QSPI module. 923b2039b2SGreg Ungerer */ 93f75b0d07SSteven King #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 943b2039b2SGreg Ungerer #define MCFQSPI_SIZE 0x40 953b2039b2SGreg Ungerer 963b2039b2SGreg Ungerer #define MCFQSPI_CS0 147 973b2039b2SGreg Ungerer #define MCFQSPI_CS1 148 983b2039b2SGreg Ungerer #define MCFQSPI_CS2 149 993b2039b2SGreg Ungerer #define MCFQSPI_CS3 150 1003b2039b2SGreg Ungerer 1013b2039b2SGreg Ungerer /* 1026da6e63cSsfking@fdwdc.com * GPIO registers 1036da6e63cSsfking@fdwdc.com */ 104c222f5f4SGreg Ungerer #define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) 105c222f5f4SGreg Ungerer #define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) 106c222f5f4SGreg Ungerer #define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) 107c222f5f4SGreg Ungerer #define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) 108c222f5f4SGreg Ungerer #define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) 109c222f5f4SGreg Ungerer #define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) 110c222f5f4SGreg Ungerer #define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) 111c222f5f4SGreg Ungerer #define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) 112c222f5f4SGreg Ungerer #define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) 113c222f5f4SGreg Ungerer #define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) 114c222f5f4SGreg Ungerer #define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) 115c222f5f4SGreg Ungerer #define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) 116c222f5f4SGreg Ungerer #define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) 117c222f5f4SGreg Ungerer #define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) 118c222f5f4SGreg Ungerer #define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) 119c222f5f4SGreg Ungerer #define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) 120c222f5f4SGreg Ungerer #define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) 121c222f5f4SGreg Ungerer #define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) 1226da6e63cSsfking@fdwdc.com 123c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) 124c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) 125c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) 126c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) 127c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) 128c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) 129c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) 130c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) 131c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) 132c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) 133c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) 134c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) 135c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) 136c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) 137c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) 138c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) 139c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) 140c222f5f4SGreg Ungerer #define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) 1416da6e63cSsfking@fdwdc.com 142c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) 143c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) 144c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) 145c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) 146c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) 147c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) 148c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) 149c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) 150c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) 151c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) 152c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) 153c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) 154c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) 155c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) 156c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) 157c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) 158c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) 159c222f5f4SGreg Ungerer #define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) 1606da6e63cSsfking@fdwdc.com 161c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) 162c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) 163c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) 164c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) 165c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) 166c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) 167c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) 168c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) 169c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) 170c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) 171c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) 172c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) 173c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) 174c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) 175c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) 176c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) 177c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) 178c222f5f4SGreg Ungerer #define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) 1796da6e63cSsfking@fdwdc.com 1806da6e63cSsfking@fdwdc.com #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) 1816da6e63cSsfking@fdwdc.com #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) 1826da6e63cSsfking@fdwdc.com #define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052) 1836da6e63cSsfking@fdwdc.com #define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054) 1846da6e63cSsfking@fdwdc.com #define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055) 1856da6e63cSsfking@fdwdc.com #define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056) 1866da6e63cSsfking@fdwdc.com #define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058) 1876da6e63cSsfking@fdwdc.com #define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059) 1886da6e63cSsfking@fdwdc.com #define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A) 1896da6e63cSsfking@fdwdc.com #define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B) 1906da6e63cSsfking@fdwdc.com #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) 1916da6e63cSsfking@fdwdc.com 1926da6e63cSsfking@fdwdc.com /* 193f317c71aSGreg Ungerer * PIT timer base addresses. 194f317c71aSGreg Ungerer */ 195f317c71aSGreg Ungerer #define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000) 196f317c71aSGreg Ungerer #define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000) 197f317c71aSGreg Ungerer #define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000) 198f317c71aSGreg Ungerer #define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000) 199f317c71aSGreg Ungerer 200f317c71aSGreg Ungerer /* 2016da6e63cSsfking@fdwdc.com * Edge Port registers 2026da6e63cSsfking@fdwdc.com */ 2036da6e63cSsfking@fdwdc.com #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) 2046da6e63cSsfking@fdwdc.com #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002) 2056da6e63cSsfking@fdwdc.com #define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003) 2066da6e63cSsfking@fdwdc.com #define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004) 2076da6e63cSsfking@fdwdc.com #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005) 2086da6e63cSsfking@fdwdc.com #define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006) 2096da6e63cSsfking@fdwdc.com 2106da6e63cSsfking@fdwdc.com /* 2116da6e63cSsfking@fdwdc.com * Queued ADC registers 2126da6e63cSsfking@fdwdc.com */ 2136da6e63cSsfking@fdwdc.com #define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006) 2146da6e63cSsfking@fdwdc.com #define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007) 2156da6e63cSsfking@fdwdc.com #define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008) 2166da6e63cSsfking@fdwdc.com #define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009) 2176da6e63cSsfking@fdwdc.com 2186da6e63cSsfking@fdwdc.com /* 2196da6e63cSsfking@fdwdc.com * General Purpose Timers registers 2206da6e63cSsfking@fdwdc.com */ 2216da6e63cSsfking@fdwdc.com #define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D) 2226da6e63cSsfking@fdwdc.com #define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E) 2236da6e63cSsfking@fdwdc.com #define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D) 2246da6e63cSsfking@fdwdc.com #define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E) 2256da6e63cSsfking@fdwdc.com /* 2266da6e63cSsfking@fdwdc.com * 2276da6e63cSsfking@fdwdc.com * definitions for generic gpio support 2286da6e63cSsfking@fdwdc.com * 2296da6e63cSsfking@fdwdc.com */ 230c222f5f4SGreg Ungerer #define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ 231c222f5f4SGreg Ungerer #define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ 232c222f5f4SGreg Ungerer #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ 233c222f5f4SGreg Ungerer #define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ 234c222f5f4SGreg Ungerer #define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ 2356da6e63cSsfking@fdwdc.com 2366da6e63cSsfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 2376da6e63cSsfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 2386da6e63cSsfking@fdwdc.com #define MCFGPIO_PIN_MAX 180 2396da6e63cSsfking@fdwdc.com 240dd65b1deSGreg Ungerer /* 241dd65b1deSGreg Ungerer * Reset Control Unit (relative to IPSBAR). 242dd65b1deSGreg Ungerer */ 243645e5333SGreg Ungerer #define MCF_RCR (MCF_IPSBAR + 0x110000) 244645e5333SGreg Ungerer #define MCF_RSR (MCF_IPSBAR + 0x110001) 245dd65b1deSGreg Ungerer 246dd65b1deSGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 247dd65b1deSGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 24849148020SSam Ravnborg 2492d24b532SSteven King /* 2502d24b532SSteven King * I2C module 2512d24b532SSteven King */ 2522d24b532SSteven King #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) 2532d24b532SSteven King #define MCFI2C_SIZE0 0x40 2542d24b532SSteven King 2558a415c4bSGreg Ungerer /****************************************************************************/ 25649148020SSam Ravnborg #endif /* m528xsim_h */ 257