1 /****************************************************************************/ 2 3 /* 4 * m523xsim.h -- ColdFire 523x System Integration Module support. 5 * 6 * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> 7 */ 8 9 /****************************************************************************/ 10 #ifndef m523xsim_h 11 #define m523xsim_h 12 /****************************************************************************/ 13 14 #define CPU_NAME "COLDFIRE(m523x)" 15 #define CPU_INSTR_PER_JIFFY 3 16 #define MCF_BUSCLK (MCF_CLK / 2) 17 18 #include <asm/m52xxacr.h> 19 20 /* 21 * Define the 523x SIM register set addresses. 22 */ 23 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 24 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ 25 26 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 27 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 28 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 29 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 30 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 31 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 32 #define MCFINTC_IRLR 0x18 /* */ 33 #define MCFINTC_IACKL 0x19 /* */ 34 #define MCFINTC_ICR0 0x40 /* Base ICR register */ 35 36 #define MCFINT_VECBASE 64 /* Vector base number */ 37 #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 38 #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 39 #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 40 #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 41 #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ 42 #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ 43 #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ 44 #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 45 46 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 47 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 48 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 49 50 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 51 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 52 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 53 54 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 55 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 56 57 /* 58 * SDRAM configuration registers. 59 */ 60 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 61 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 62 #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 63 #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 64 #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 65 66 /* 67 * Reset Control Unit (relative to IPSBAR). 68 */ 69 #define MCF_RCR (MCF_IPSBAR + 0x110000) 70 #define MCF_RSR (MCF_IPSBAR + 0x110001) 71 72 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 73 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 74 75 /* 76 * UART module. 77 */ 78 #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 79 #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 80 #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 81 82 /* 83 * FEC ethernet module. 84 */ 85 #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 86 #define MCFFEC_SIZE0 0x800 87 88 /* 89 * QSPI module. 90 */ 91 #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 92 #define MCFQSPI_SIZE 0x40 93 94 #define MCFQSPI_CS0 91 95 #define MCFQSPI_CS1 92 96 #define MCFQSPI_CS2 103 97 #define MCFQSPI_CS3 99 98 99 /* 100 * GPIO module. 101 */ 102 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 103 #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 104 #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 105 #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 106 #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 107 #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 108 #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 109 #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 110 #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 111 #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 112 #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 113 #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 114 #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) 115 116 #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 117 #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 118 #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 119 #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 120 #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 121 #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 122 #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 123 #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 124 #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 125 #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 126 #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 127 #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 128 #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) 129 130 #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 131 #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 132 #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 133 #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 134 #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 135 #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 136 #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 137 #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 138 #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 139 #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 140 #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 141 #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 142 #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) 143 144 #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 145 #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 146 #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 147 #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 148 #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 149 #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 150 #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 151 #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 152 #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 153 #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 154 #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 155 #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 156 #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) 157 158 /* 159 * PIT timer base addresses. 160 */ 161 #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 162 #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 163 #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 164 #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 165 166 /* 167 * EPort 168 */ 169 #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 170 #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 171 #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 172 #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 173 #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 174 #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 175 176 /* 177 * Generic GPIO support 178 */ 179 #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 180 #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 181 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 182 #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 183 #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 184 185 #define MCFGPIO_PIN_MAX 107 186 #define MCFGPIO_IRQ_MAX 8 187 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 188 189 /* 190 * Pin Assignment 191 */ 192 #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) 193 #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) 194 #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) 195 #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) 196 #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) 197 #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) 198 #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) 199 #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 200 #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 201 #define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E) 202 203 /* 204 * DMA unit base addresses. 205 */ 206 #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 207 #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 208 #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 209 #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 210 211 /****************************************************************************/ 212 #endif /* m523xsim_h */ 213