1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
249148020SSam Ravnborg /*
349148020SSam Ravnborg * include/asm-m68k/dma.h
449148020SSam Ravnborg *
549148020SSam Ravnborg * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
649148020SSam Ravnborg *
749148020SSam Ravnborg * Hacked to fit Sun3x needs by Thomas Bogendoerfer
849148020SSam Ravnborg */
949148020SSam Ravnborg
1049148020SSam Ravnborg #ifndef __M68K_DVMA_H
1149148020SSam Ravnborg #define __M68K_DVMA_H
1249148020SSam Ravnborg
1349148020SSam Ravnborg
1449148020SSam Ravnborg #define DVMA_PAGE_SHIFT 13
1549148020SSam Ravnborg #define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
1649148020SSam Ravnborg #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
1749148020SSam Ravnborg #define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
1849148020SSam Ravnborg
1949148020SSam Ravnborg extern void dvma_init(void);
2049148020SSam Ravnborg extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
2149148020SSam Ravnborg int len);
2249148020SSam Ravnborg
2349148020SSam Ravnborg #define dvma_malloc(x) dvma_malloc_align(x, 0)
2449148020SSam Ravnborg #define dvma_map(x, y) dvma_map_align(x, y, 0)
2549148020SSam Ravnborg #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
2649148020SSam Ravnborg #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
2749148020SSam Ravnborg extern unsigned long dvma_map_align(unsigned long kaddr, int len,
2849148020SSam Ravnborg int align);
2949148020SSam Ravnborg extern void *dvma_malloc_align(unsigned long len, unsigned long align);
3049148020SSam Ravnborg
3149148020SSam Ravnborg extern void dvma_unmap(void *baddr);
3249148020SSam Ravnborg extern void dvma_free(void *vaddr);
3349148020SSam Ravnborg
3449148020SSam Ravnborg
3549148020SSam Ravnborg #ifdef CONFIG_SUN3
3649148020SSam Ravnborg /* sun3 dvma page support */
3749148020SSam Ravnborg
3849148020SSam Ravnborg /* memory and pmegs potentially reserved for dvma */
3949148020SSam Ravnborg #define DVMA_PMEG_START 10
4049148020SSam Ravnborg #define DVMA_PMEG_END 16
4149148020SSam Ravnborg #define DVMA_START 0xf00000
4249148020SSam Ravnborg #define DVMA_END 0xfe0000
4349148020SSam Ravnborg #define DVMA_SIZE (DVMA_END-DVMA_START)
4449148020SSam Ravnborg #define IOMMU_TOTAL_ENTRIES 128
4549148020SSam Ravnborg #define IOMMU_ENTRIES 120
4649148020SSam Ravnborg
4749148020SSam Ravnborg /* empirical kludge -- dvma regions only seem to work right on 0x10000
4849148020SSam Ravnborg byte boundaries */
4949148020SSam Ravnborg #define DVMA_REGION_SIZE 0x10000
5049148020SSam Ravnborg #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
5149148020SSam Ravnborg ~(DVMA_REGION_SIZE-1))
5249148020SSam Ravnborg
5349148020SSam Ravnborg /* virt <-> phys conversions */
5449148020SSam Ravnborg #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
5549148020SSam Ravnborg #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
5649148020SSam Ravnborg #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
5749148020SSam Ravnborg #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
5849148020SSam Ravnborg #define dvma_vtob(x) dvma_vtop(x)
5949148020SSam Ravnborg #define dvma_btov(x) dvma_ptov(x)
6049148020SSam Ravnborg
61*4ebe8459SGeert Uytterhoeven void sun3_dvma_init(void);
62*4ebe8459SGeert Uytterhoeven
dvma_map_cpu(unsigned long kaddr,unsigned long vaddr,int len)6349148020SSam Ravnborg static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
6449148020SSam Ravnborg int len)
6549148020SSam Ravnborg {
6649148020SSam Ravnborg return 0;
6749148020SSam Ravnborg }
6849148020SSam Ravnborg
dvma_unmap_iommu(unsigned long baddr,int len)69*4ebe8459SGeert Uytterhoeven static inline void dvma_unmap_iommu(unsigned long baddr, int len) { }
70*4ebe8459SGeert Uytterhoeven
7149148020SSam Ravnborg #else /* Sun3x */
7249148020SSam Ravnborg
7349148020SSam Ravnborg /* sun3x dvma page support */
7449148020SSam Ravnborg
7549148020SSam Ravnborg #define DVMA_START 0x0
7649148020SSam Ravnborg #define DVMA_END 0xf00000
7749148020SSam Ravnborg #define DVMA_SIZE (DVMA_END-DVMA_START)
7849148020SSam Ravnborg #define IOMMU_TOTAL_ENTRIES 2048
7949148020SSam Ravnborg /* the prom takes the top meg */
8049148020SSam Ravnborg #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
8149148020SSam Ravnborg
8249148020SSam Ravnborg #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
8349148020SSam Ravnborg #define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
8449148020SSam Ravnborg
sun3_dvma_init(void)85*4ebe8459SGeert Uytterhoeven static inline void sun3_dvma_init(void) { }
8649148020SSam Ravnborg
87*4ebe8459SGeert Uytterhoeven int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
8849148020SSam Ravnborg
89*4ebe8459SGeert Uytterhoeven void dvma_unmap_iommu(unsigned long baddr, int len);
9049148020SSam Ravnborg
9149148020SSam Ravnborg /* everything below this line is specific to dma used for the onboard
9249148020SSam Ravnborg ESP scsi on sun3x */
9349148020SSam Ravnborg
9449148020SSam Ravnborg /* Structure to describe the current status of DMA registers on the Sparc */
9549148020SSam Ravnborg struct sparc_dma_registers {
9649148020SSam Ravnborg __volatile__ unsigned long cond_reg; /* DMA condition register */
9749148020SSam Ravnborg __volatile__ unsigned long st_addr; /* Start address of this transfer */
9849148020SSam Ravnborg __volatile__ unsigned long cnt; /* How many bytes to transfer */
9949148020SSam Ravnborg __volatile__ unsigned long dma_test; /* DMA test register */
10049148020SSam Ravnborg };
10149148020SSam Ravnborg
10249148020SSam Ravnborg /* DVMA chip revisions */
10349148020SSam Ravnborg enum dvma_rev {
10449148020SSam Ravnborg dvmarev0,
10549148020SSam Ravnborg dvmaesc1,
10649148020SSam Ravnborg dvmarev1,
10749148020SSam Ravnborg dvmarev2,
10849148020SSam Ravnborg dvmarev3,
10949148020SSam Ravnborg dvmarevplus,
11049148020SSam Ravnborg dvmahme
11149148020SSam Ravnborg };
11249148020SSam Ravnborg
11349148020SSam Ravnborg #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
11449148020SSam Ravnborg
11549148020SSam Ravnborg /* Linux DMA information structure, filled during probe. */
11649148020SSam Ravnborg struct Linux_SBus_DMA {
11749148020SSam Ravnborg struct Linux_SBus_DMA *next;
11849148020SSam Ravnborg struct linux_sbus_device *SBus_dev;
11949148020SSam Ravnborg struct sparc_dma_registers *regs;
12049148020SSam Ravnborg
12149148020SSam Ravnborg /* Status, misc info */
12249148020SSam Ravnborg int node; /* Prom node for this DMA device */
12349148020SSam Ravnborg int running; /* Are we doing DMA now? */
12449148020SSam Ravnborg int allocated; /* Are we "owned" by anyone yet? */
12549148020SSam Ravnborg
12649148020SSam Ravnborg /* Transfer information. */
12749148020SSam Ravnborg unsigned long addr; /* Start address of current transfer */
12849148020SSam Ravnborg int nbytes; /* Size of current transfer */
12949148020SSam Ravnborg int realbytes; /* For splitting up large transfers, etc. */
13049148020SSam Ravnborg
13149148020SSam Ravnborg /* DMA revision */
13249148020SSam Ravnborg enum dvma_rev revision;
13349148020SSam Ravnborg };
13449148020SSam Ravnborg
13549148020SSam Ravnborg extern struct Linux_SBus_DMA *dma_chain;
13649148020SSam Ravnborg
13749148020SSam Ravnborg /* Broken hardware... */
13849148020SSam Ravnborg #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
13949148020SSam Ravnborg #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
14049148020SSam Ravnborg
14149148020SSam Ravnborg /* Fields in the cond_reg register */
14249148020SSam Ravnborg /* First, the version identification bits */
14349148020SSam Ravnborg #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
14449148020SSam Ravnborg #define DMA_VERS0 0x00000000 /* Sunray DMA version */
14549148020SSam Ravnborg #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
14649148020SSam Ravnborg #define DMA_VERS1 0x80000000 /* DMA rev 1 */
14749148020SSam Ravnborg #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
14849148020SSam Ravnborg #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
14949148020SSam Ravnborg #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
15049148020SSam Ravnborg
15149148020SSam Ravnborg #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
15249148020SSam Ravnborg #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
15349148020SSam Ravnborg #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
15449148020SSam Ravnborg #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
15549148020SSam Ravnborg #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
15649148020SSam Ravnborg #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
15749148020SSam Ravnborg #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
15849148020SSam Ravnborg #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
15949148020SSam Ravnborg #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
16049148020SSam Ravnborg #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
16149148020SSam Ravnborg #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
16249148020SSam Ravnborg #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
16349148020SSam Ravnborg #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
16449148020SSam Ravnborg #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
16549148020SSam Ravnborg #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
16649148020SSam Ravnborg #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
16749148020SSam Ravnborg #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
16849148020SSam Ravnborg #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
16949148020SSam Ravnborg #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
17049148020SSam Ravnborg #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
17149148020SSam Ravnborg #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
17249148020SSam Ravnborg #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
17349148020SSam Ravnborg #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
17449148020SSam Ravnborg #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
17549148020SSam Ravnborg #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
17649148020SSam Ravnborg #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
17749148020SSam Ravnborg #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
17849148020SSam Ravnborg #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
17949148020SSam Ravnborg #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
18049148020SSam Ravnborg #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
18149148020SSam Ravnborg #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
18249148020SSam Ravnborg #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
18349148020SSam Ravnborg #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
18449148020SSam Ravnborg #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
18549148020SSam Ravnborg #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
18649148020SSam Ravnborg #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
18749148020SSam Ravnborg #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
18849148020SSam Ravnborg
18949148020SSam Ravnborg /* Values describing the burst-size property from the PROM */
19049148020SSam Ravnborg #define DMA_BURST1 0x01
19149148020SSam Ravnborg #define DMA_BURST2 0x02
19249148020SSam Ravnborg #define DMA_BURST4 0x04
19349148020SSam Ravnborg #define DMA_BURST8 0x08
19449148020SSam Ravnborg #define DMA_BURST16 0x10
19549148020SSam Ravnborg #define DMA_BURST32 0x20
19649148020SSam Ravnborg #define DMA_BURST64 0x40
19749148020SSam Ravnborg #define DMA_BURSTBITS 0x7f
19849148020SSam Ravnborg
19949148020SSam Ravnborg /* Determine highest possible final transfer address given a base */
20049148020SSam Ravnborg #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
20149148020SSam Ravnborg
20249148020SSam Ravnborg /* Yes, I hack a lot of elisp in my spare time... */
20349148020SSam Ravnborg #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
20449148020SSam Ravnborg #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
20549148020SSam Ravnborg #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
20649148020SSam Ravnborg #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
20749148020SSam Ravnborg #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
20849148020SSam Ravnborg #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
20949148020SSam Ravnborg #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
21049148020SSam Ravnborg #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
21149148020SSam Ravnborg #define DMA_BEGINDMA_W(regs) \
21249148020SSam Ravnborg ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
21349148020SSam Ravnborg #define DMA_BEGINDMA_R(regs) \
21449148020SSam Ravnborg ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
21549148020SSam Ravnborg
21649148020SSam Ravnborg /* For certain DMA chips, we need to disable ints upon irq entry
21749148020SSam Ravnborg * and turn them back on when we are done. So in any ESP interrupt
21849148020SSam Ravnborg * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
21949148020SSam Ravnborg * when leaving the handler. You have been warned...
22049148020SSam Ravnborg */
22149148020SSam Ravnborg #define DMA_IRQ_ENTRY(dma, dregs) do { \
22249148020SSam Ravnborg if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
22349148020SSam Ravnborg } while (0)
22449148020SSam Ravnborg
22549148020SSam Ravnborg #define DMA_IRQ_EXIT(dma, dregs) do { \
22649148020SSam Ravnborg if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
22749148020SSam Ravnborg } while(0)
22849148020SSam Ravnborg
22949148020SSam Ravnborg /* Reset the friggin' thing... */
23049148020SSam Ravnborg #define DMA_RESET(dma) do { \
23149148020SSam Ravnborg struct sparc_dma_registers *regs = dma->regs; \
23249148020SSam Ravnborg /* Let the current FIFO drain itself */ \
23349148020SSam Ravnborg sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
23449148020SSam Ravnborg /* Reset the logic */ \
23549148020SSam Ravnborg regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
23649148020SSam Ravnborg __delay(400); /* let the bits set ;) */ \
23749148020SSam Ravnborg regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
23849148020SSam Ravnborg sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
23949148020SSam Ravnborg /* Enable FAST transfers if available */ \
24049148020SSam Ravnborg if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
24149148020SSam Ravnborg dma->running = 0; \
24249148020SSam Ravnborg } while(0)
24349148020SSam Ravnborg
24449148020SSam Ravnborg
24549148020SSam Ravnborg #endif /* !CONFIG_SUN3 */
24649148020SSam Ravnborg
24749148020SSam Ravnborg #endif /* !(__M68K_DVMA_H) */
248