1 /* 2 * stmark2.c -- Support for Kernelspace AMCORE open board 3 * 4 * (C) Copyright 2026, Angelo Dureghello <angelo@kernel-space.org> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 */ 10 11 #include <linux/ioport.h> 12 #include <linux/platform_device.h> 13 #include <linux/mtd/partitions.h> 14 #include <linux/spi/spi.h> 15 #include <linux/spi/spi-fsl-dspi.h> 16 #include <linux/spi/flash.h> 17 #include <linux/dma-mapping.h> 18 #include <asm/mcfsim.h> 19 20 /* 21 * Partitioning of parallel NOR flash (39VF3201B) 22 */ 23 static struct mtd_partition stmark2_partitions[] = { 24 { 25 .name = "U-Boot (1024K)", 26 .size = 0x100000, 27 .offset = 0x0 28 }, { 29 .name = "Kernel+initramfs (7168K)", 30 .size = 0x700000, 31 .offset = MTDPART_OFS_APPEND 32 }, { 33 .name = "Flash Free Space (8192K)", 34 .size = MTDPART_SIZ_FULL, 35 .offset = MTDPART_OFS_APPEND 36 } 37 }; 38 39 static struct flash_platform_data stmark2_spi_flash_data = { 40 .name = "is25lp128", 41 .parts = stmark2_partitions, 42 .nr_parts = ARRAY_SIZE(stmark2_partitions), 43 .type = "is25lp128", 44 }; 45 46 static struct spi_board_info stmark2_board_info[] __initdata = { 47 { 48 .modalias = "m25p80", 49 .max_speed_hz = 5000000, 50 .bus_num = 0, 51 .chip_select = 1, 52 .platform_data = &stmark2_spi_flash_data, 53 .mode = SPI_MODE_3, 54 } 55 }; 56 57 /* SPI controller data, SPI (0) */ 58 static struct fsl_dspi_platform_data dspi_spi0_info = { 59 .cs_num = 4, 60 .bus_num = 0, 61 .sck_cs_delay = 100, 62 .cs_sck_delay = 100, 63 }; 64 65 static struct resource dspi_spi0_resource[] = { 66 DEFINE_RES_MEM(MCFDSPI_BASE0, 0x100), 67 DEFINE_RES_IRQ(MCF_IRQ_DSPI0), 68 DEFINE_RES_DMA(12), 69 DEFINE_RES_DMA(13), 70 }; 71 72 static u64 stmark2_dspi_mask = DMA_BIT_MASK(32); 73 74 /* SPI controller, id = bus number */ 75 static struct platform_device dspi_spi0_device = { 76 .name = "fsl-dspi", 77 .id = 0, 78 .num_resources = ARRAY_SIZE(dspi_spi0_resource), 79 .resource = dspi_spi0_resource, 80 .dev = { 81 .platform_data = &dspi_spi0_info, 82 .dma_mask = &stmark2_dspi_mask, 83 .coherent_dma_mask = DMA_BIT_MASK(32), 84 }, 85 }; 86 87 static struct resource dac0_resource = DEFINE_RES_MEM(MCFDAC_BASE0, 0x100); 88 89 static struct platform_device dac0_device = { 90 .name = "mcfdac", 91 .id = 0, 92 .num_resources = 1, 93 .resource = &dac0_resource, 94 }; 95 96 static struct resource dac1_resource = DEFINE_RES_MEM(MCFDAC_BASE1, 0x100); 97 98 static struct platform_device dac1_device = { 99 .name = "mcfdac", 100 .id = 1, 101 .num_resources = 1, 102 .resource = &dac1_resource, 103 }; 104 105 static struct platform_device *stmark2_devices[] __initdata = { 106 &dspi_spi0_device, 107 &dac0_device, 108 &dac1_device, 109 }; 110 111 /* 112 * Note: proper pin-mux setup is mandatory for proper SPI functionality. 113 */ 114 static int __init init_stmark2(void) 115 { 116 u16 val; 117 118 /* DSPI0, all pins as DSPI, and using CS1 */ 119 mcf_write8(0x80, MCFGPIO_PAR_DSPIOWL); 120 mcf_write8(0xfc, MCFGPIO_PAR_DSPIOWH); 121 122 /* Board gpio setup */ 123 mcf_write8(0x00, MCFGPIO_PAR_BE); 124 mcf_write8(0x00, MCFGPIO_PAR_FBCTL); 125 mcf_write8(0x00, MCFGPIO_PAR_CS); 126 127 /* CAN pads */ 128 mcf_write8(0x50, MCFGPIO_PAR_CANI2C); 129 130 val = mcf_read16(MCF_CCM_MISCCR2); 131 val &= ~(MCF_CCM_MISCCR2_ADC3_EN | MCF_CCM_MISCCR2_ADC7_EN); 132 val |= MCF_CCM_MISCCR2_DAC0_SEL | MCF_CCM_MISCCR2_DAC1_SEL; 133 mcf_write16(val, MCF_CCM_MISCCR2); 134 135 platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices)); 136 137 spi_register_board_info(stmark2_board_info, 138 ARRAY_SIZE(stmark2_board_info)); 139 140 return 0; 141 } 142 143 device_initcall(init_stmark2); 144