1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2f86b9e03SGreg Ungerer /***************************************************************************/ 3f86b9e03SGreg Ungerer 4f86b9e03SGreg Ungerer /* 5ece9ae65SGreg Ungerer * m54xx.c -- platform support for ColdFire 54xx based boards 6f86b9e03SGreg Ungerer * 7f86b9e03SGreg Ungerer * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be> 8f86b9e03SGreg Ungerer */ 9f86b9e03SGreg Ungerer 10f86b9e03SGreg Ungerer /***************************************************************************/ 11f86b9e03SGreg Ungerer 12f86b9e03SGreg Ungerer #include <linux/kernel.h> 13f86b9e03SGreg Ungerer #include <linux/param.h> 14f86b9e03SGreg Ungerer #include <linux/init.h> 15f86b9e03SGreg Ungerer #include <linux/interrupt.h> 16f86b9e03SGreg Ungerer #include <linux/io.h> 17f86b9e03SGreg Ungerer #include <linux/mm.h> 18f86b9e03SGreg Ungerer #include <linux/clk.h> 19*57c8a661SMike Rapoport #include <linux/memblock.h> 20f86b9e03SGreg Ungerer #include <asm/pgalloc.h> 21f86b9e03SGreg Ungerer #include <asm/machdep.h> 22f86b9e03SGreg Ungerer #include <asm/coldfire.h> 23f86b9e03SGreg Ungerer #include <asm/m54xxsim.h> 24f86b9e03SGreg Ungerer #include <asm/mcfuart.h> 25f86b9e03SGreg Ungerer #include <asm/mcfclk.h> 26f86b9e03SGreg Ungerer #include <asm/m54xxgpt.h> 27f86b9e03SGreg Ungerer #ifdef CONFIG_MMU 28f86b9e03SGreg Ungerer #include <asm/mmu_context.h> 29f86b9e03SGreg Ungerer #endif 30f86b9e03SGreg Ungerer 31f86b9e03SGreg Ungerer /***************************************************************************/ 32f86b9e03SGreg Ungerer 33f86b9e03SGreg Ungerer DEFINE_CLK(pll, "pll.0", MCF_CLK); 34f86b9e03SGreg Ungerer DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 35f86b9e03SGreg Ungerer DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK); 36f86b9e03SGreg Ungerer DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK); 37f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 38f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 39f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 40f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK); 412d24b532SSteven King DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); 42f86b9e03SGreg Ungerer 43f86b9e03SGreg Ungerer struct clk *mcf_clks[] = { 44f86b9e03SGreg Ungerer &clk_pll, 45f86b9e03SGreg Ungerer &clk_sys, 46f86b9e03SGreg Ungerer &clk_mcfslt0, 47f86b9e03SGreg Ungerer &clk_mcfslt1, 48f86b9e03SGreg Ungerer &clk_mcfuart0, 49f86b9e03SGreg Ungerer &clk_mcfuart1, 50f86b9e03SGreg Ungerer &clk_mcfuart2, 51f86b9e03SGreg Ungerer &clk_mcfuart3, 522d24b532SSteven King &clk_mcfi2c0, 53f86b9e03SGreg Ungerer NULL 54f86b9e03SGreg Ungerer }; 55f86b9e03SGreg Ungerer 56f86b9e03SGreg Ungerer /***************************************************************************/ 57f86b9e03SGreg Ungerer 58f86b9e03SGreg Ungerer static void __init m54xx_uarts_init(void) 59f86b9e03SGreg Ungerer { 60f86b9e03SGreg Ungerer /* enable io pins */ 61f86b9e03SGreg Ungerer __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0); 62f86b9e03SGreg Ungerer __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, 63f86b9e03SGreg Ungerer MCFGPIO_PAR_PSC1); 64f86b9e03SGreg Ungerer __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | 65f86b9e03SGreg Ungerer MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2); 66f86b9e03SGreg Ungerer __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3); 67f86b9e03SGreg Ungerer } 68f86b9e03SGreg Ungerer 69f86b9e03SGreg Ungerer /***************************************************************************/ 70f86b9e03SGreg Ungerer 712d24b532SSteven King static void __init m54xx_i2c_init(void) 722d24b532SSteven King { 732d24b532SSteven King #if IS_ENABLED(CONFIG_I2C_IMX) 742d24b532SSteven King u32 r; 752d24b532SSteven King 762d24b532SSteven King /* set the fec/i2c/irq pin assignment register for i2c */ 772d24b532SSteven King r = readl(MCF_PAR_FECI2CIRQ); 782d24b532SSteven King r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL; 792d24b532SSteven King writel(r, MCF_PAR_FECI2CIRQ); 802d24b532SSteven King #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 812d24b532SSteven King } 822d24b532SSteven King 832d24b532SSteven King /***************************************************************************/ 842d24b532SSteven King 85f86b9e03SGreg Ungerer static void mcf54xx_reset(void) 86f86b9e03SGreg Ungerer { 87f86b9e03SGreg Ungerer /* disable interrupts and enable the watchdog */ 88f86b9e03SGreg Ungerer asm("movew #0x2700, %sr\n"); 89f86b9e03SGreg Ungerer __raw_writel(0, MCF_GPT_GMS0); 90f86b9e03SGreg Ungerer __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0); 91f86b9e03SGreg Ungerer __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), 92f86b9e03SGreg Ungerer MCF_GPT_GMS0); 93f86b9e03SGreg Ungerer } 94f86b9e03SGreg Ungerer 95f86b9e03SGreg Ungerer /***************************************************************************/ 96f86b9e03SGreg Ungerer 97f86b9e03SGreg Ungerer void __init config_BSP(char *commandp, int size) 98f86b9e03SGreg Ungerer { 99f86b9e03SGreg Ungerer mach_reset = mcf54xx_reset; 100f86b9e03SGreg Ungerer mach_sched_init = hw_timer_init; 101f86b9e03SGreg Ungerer m54xx_uarts_init(); 1022d24b532SSteven King m54xx_i2c_init(); 103f86b9e03SGreg Ungerer } 104f86b9e03SGreg Ungerer 105f86b9e03SGreg Ungerer /***************************************************************************/ 106