1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2f86b9e03SGreg Ungerer /***************************************************************************/
3f86b9e03SGreg Ungerer
4f86b9e03SGreg Ungerer /*
5ece9ae65SGreg Ungerer * m528x.c -- platform support for ColdFire 528x based boards
6f86b9e03SGreg Ungerer *
7f86b9e03SGreg Ungerer * Sub-architcture dependent initialization code for the Freescale
8f86b9e03SGreg Ungerer * 5280, 5281 and 5282 CPUs.
9f86b9e03SGreg Ungerer *
10f86b9e03SGreg Ungerer * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
11f86b9e03SGreg Ungerer * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12f86b9e03SGreg Ungerer */
13f86b9e03SGreg Ungerer
14f86b9e03SGreg Ungerer /***************************************************************************/
15f86b9e03SGreg Ungerer
16*63aadb77SArnd Bergmann #include <linux/clkdev.h>
17f86b9e03SGreg Ungerer #include <linux/kernel.h>
18f86b9e03SGreg Ungerer #include <linux/param.h>
19f86b9e03SGreg Ungerer #include <linux/init.h>
20f86b9e03SGreg Ungerer #include <linux/platform_device.h>
21f86b9e03SGreg Ungerer #include <linux/io.h>
22f86b9e03SGreg Ungerer #include <asm/machdep.h>
23f86b9e03SGreg Ungerer #include <asm/coldfire.h>
24f86b9e03SGreg Ungerer #include <asm/mcfsim.h>
25f86b9e03SGreg Ungerer #include <asm/mcfuart.h>
26f86b9e03SGreg Ungerer #include <asm/mcfclk.h>
27f86b9e03SGreg Ungerer
28f86b9e03SGreg Ungerer /***************************************************************************/
29f86b9e03SGreg Ungerer
30f86b9e03SGreg Ungerer DEFINE_CLK(pll, "pll.0", MCF_CLK);
31f86b9e03SGreg Ungerer DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
32f86b9e03SGreg Ungerer
33*63aadb77SArnd Bergmann static struct clk_lookup m528x_clk_lookup[] = {
34*63aadb77SArnd Bergmann CLKDEV_INIT(NULL, "pll.0", &clk_pll),
35*63aadb77SArnd Bergmann CLKDEV_INIT(NULL, "sys.0", &clk_sys),
36*63aadb77SArnd Bergmann CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
37*63aadb77SArnd Bergmann CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
38*63aadb77SArnd Bergmann CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
39*63aadb77SArnd Bergmann CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
40*63aadb77SArnd Bergmann CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
41*63aadb77SArnd Bergmann CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
42*63aadb77SArnd Bergmann CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
43*63aadb77SArnd Bergmann CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
44*63aadb77SArnd Bergmann CLKDEV_INIT("fec.0", NULL, &clk_sys),
45*63aadb77SArnd Bergmann CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
46f86b9e03SGreg Ungerer };
47f86b9e03SGreg Ungerer
48f86b9e03SGreg Ungerer /***************************************************************************/
49f86b9e03SGreg Ungerer
m528x_qspi_init(void)50f86b9e03SGreg Ungerer static void __init m528x_qspi_init(void)
51f86b9e03SGreg Ungerer {
52f86b9e03SGreg Ungerer #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
53f86b9e03SGreg Ungerer /* setup Port QS for QSPI with gpio CS control */
54f86b9e03SGreg Ungerer __raw_writeb(0x07, MCFGPIO_PQSPAR);
55f86b9e03SGreg Ungerer #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
56f86b9e03SGreg Ungerer }
57f86b9e03SGreg Ungerer
58f86b9e03SGreg Ungerer /***************************************************************************/
59f86b9e03SGreg Ungerer
m528x_i2c_init(void)602d24b532SSteven King static void __init m528x_i2c_init(void)
612d24b532SSteven King {
622d24b532SSteven King #if IS_ENABLED(CONFIG_I2C_IMX)
632d24b532SSteven King u16 paspar;
642d24b532SSteven King
652d24b532SSteven King /* setup Port AS Pin Assignment Register for I2C */
662d24b532SSteven King /* set PASPA0 to SCL and PASPA1 to SDA */
672d24b532SSteven King paspar = readw(MCFGPIO_PASPAR);
682d24b532SSteven King paspar |= 0xF;
692d24b532SSteven King writew(paspar, MCFGPIO_PASPAR);
702d24b532SSteven King #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
712d24b532SSteven King }
722d24b532SSteven King
732d24b532SSteven King /***************************************************************************/
742d24b532SSteven King
m528x_uarts_init(void)75f86b9e03SGreg Ungerer static void __init m528x_uarts_init(void)
76f86b9e03SGreg Ungerer {
77f86b9e03SGreg Ungerer u8 port;
78f86b9e03SGreg Ungerer
79f86b9e03SGreg Ungerer /* make sure PUAPAR is set for UART0 and UART1 */
80f86b9e03SGreg Ungerer port = readb(MCFGPIO_PUAPAR);
81f86b9e03SGreg Ungerer port |= 0x03 | (0x03 << 2);
82f86b9e03SGreg Ungerer writeb(port, MCFGPIO_PUAPAR);
83f86b9e03SGreg Ungerer }
84f86b9e03SGreg Ungerer
85f86b9e03SGreg Ungerer /***************************************************************************/
86f86b9e03SGreg Ungerer
m528x_fec_init(void)87f86b9e03SGreg Ungerer static void __init m528x_fec_init(void)
88f86b9e03SGreg Ungerer {
89f86b9e03SGreg Ungerer u16 v16;
90f86b9e03SGreg Ungerer
91f86b9e03SGreg Ungerer /* Set multi-function pins to ethernet mode for fec0 */
92f86b9e03SGreg Ungerer v16 = readw(MCFGPIO_PASPAR);
93f86b9e03SGreg Ungerer writew(v16 | 0xf00, MCFGPIO_PASPAR);
94f86b9e03SGreg Ungerer writeb(0xc0, MCFGPIO_PEHLPAR);
95f86b9e03SGreg Ungerer }
96f86b9e03SGreg Ungerer
97f86b9e03SGreg Ungerer /***************************************************************************/
98f86b9e03SGreg Ungerer
99f86b9e03SGreg Ungerer #ifdef CONFIG_WILDFIRE
wildfire_halt(void)100f86b9e03SGreg Ungerer void wildfire_halt(void)
101f86b9e03SGreg Ungerer {
102f86b9e03SGreg Ungerer writeb(0, 0x30000007);
103f86b9e03SGreg Ungerer writeb(0x2, 0x30000007);
104f86b9e03SGreg Ungerer }
105f86b9e03SGreg Ungerer #endif
106f86b9e03SGreg Ungerer
107f86b9e03SGreg Ungerer #ifdef CONFIG_WILDFIREMOD
wildfiremod_halt(void)108f86b9e03SGreg Ungerer void wildfiremod_halt(void)
109f86b9e03SGreg Ungerer {
110f86b9e03SGreg Ungerer printk(KERN_INFO "WildFireMod hibernating...\n");
111f86b9e03SGreg Ungerer
112f86b9e03SGreg Ungerer /* Set portE.5 to Digital IO */
11341b39ea1SGreg Ungerer writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
114f86b9e03SGreg Ungerer
115f86b9e03SGreg Ungerer /* Make portE.5 an output */
11641b39ea1SGreg Ungerer writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
117f86b9e03SGreg Ungerer
118f86b9e03SGreg Ungerer /* Now toggle portE.5 from low to high */
11941b39ea1SGreg Ungerer writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
12041b39ea1SGreg Ungerer writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
121f86b9e03SGreg Ungerer
122f86b9e03SGreg Ungerer printk(KERN_EMERG "Failed to hibernate. Halting!\n");
123f86b9e03SGreg Ungerer }
124f86b9e03SGreg Ungerer #endif
125f86b9e03SGreg Ungerer
config_BSP(char * commandp,int size)126f86b9e03SGreg Ungerer void __init config_BSP(char *commandp, int size)
127f86b9e03SGreg Ungerer {
128f86b9e03SGreg Ungerer #ifdef CONFIG_WILDFIRE
129f86b9e03SGreg Ungerer mach_halt = wildfire_halt;
130f86b9e03SGreg Ungerer #endif
131f86b9e03SGreg Ungerer #ifdef CONFIG_WILDFIREMOD
132f86b9e03SGreg Ungerer mach_halt = wildfiremod_halt;
133f86b9e03SGreg Ungerer #endif
134f86b9e03SGreg Ungerer mach_sched_init = hw_timer_init;
135f86b9e03SGreg Ungerer m528x_uarts_init();
136f86b9e03SGreg Ungerer m528x_fec_init();
137f86b9e03SGreg Ungerer m528x_qspi_init();
1382d24b532SSteven King m528x_i2c_init();
139*63aadb77SArnd Bergmann
140*63aadb77SArnd Bergmann clkdev_add_table(m528x_clk_lookup, ARRAY_SIZE(m528x_clk_lookup));
141f86b9e03SGreg Ungerer }
142f86b9e03SGreg Ungerer
143f86b9e03SGreg Ungerer /***************************************************************************/
144