1*f86b9e03SGreg Ungerer /***************************************************************************/ 2*f86b9e03SGreg Ungerer 3*f86b9e03SGreg Ungerer /* 4*f86b9e03SGreg Ungerer * linux/arch/m68knommu/platform/527x/config.c 5*f86b9e03SGreg Ungerer * 6*f86b9e03SGreg Ungerer * Sub-architcture dependent initialization code for the Freescale 7*f86b9e03SGreg Ungerer * 5270/5271 CPUs. 8*f86b9e03SGreg Ungerer * 9*f86b9e03SGreg Ungerer * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) 10*f86b9e03SGreg Ungerer * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) 11*f86b9e03SGreg Ungerer */ 12*f86b9e03SGreg Ungerer 13*f86b9e03SGreg Ungerer /***************************************************************************/ 14*f86b9e03SGreg Ungerer 15*f86b9e03SGreg Ungerer #include <linux/kernel.h> 16*f86b9e03SGreg Ungerer #include <linux/param.h> 17*f86b9e03SGreg Ungerer #include <linux/init.h> 18*f86b9e03SGreg Ungerer #include <linux/io.h> 19*f86b9e03SGreg Ungerer #include <asm/machdep.h> 20*f86b9e03SGreg Ungerer #include <asm/coldfire.h> 21*f86b9e03SGreg Ungerer #include <asm/mcfsim.h> 22*f86b9e03SGreg Ungerer #include <asm/mcfuart.h> 23*f86b9e03SGreg Ungerer #include <asm/mcfclk.h> 24*f86b9e03SGreg Ungerer 25*f86b9e03SGreg Ungerer /***************************************************************************/ 26*f86b9e03SGreg Ungerer 27*f86b9e03SGreg Ungerer DEFINE_CLK(pll, "pll.0", MCF_CLK); 28*f86b9e03SGreg Ungerer DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 29*f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); 30*f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); 31*f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); 32*f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); 33*f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 34*f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 35*f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 36*f86b9e03SGreg Ungerer DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 37*f86b9e03SGreg Ungerer DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); 38*f86b9e03SGreg Ungerer DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK); 39*f86b9e03SGreg Ungerer 40*f86b9e03SGreg Ungerer struct clk *mcf_clks[] = { 41*f86b9e03SGreg Ungerer &clk_pll, 42*f86b9e03SGreg Ungerer &clk_sys, 43*f86b9e03SGreg Ungerer &clk_mcfpit0, 44*f86b9e03SGreg Ungerer &clk_mcfpit1, 45*f86b9e03SGreg Ungerer &clk_mcfpit2, 46*f86b9e03SGreg Ungerer &clk_mcfpit3, 47*f86b9e03SGreg Ungerer &clk_mcfuart0, 48*f86b9e03SGreg Ungerer &clk_mcfuart1, 49*f86b9e03SGreg Ungerer &clk_mcfuart2, 50*f86b9e03SGreg Ungerer &clk_mcfqspi0, 51*f86b9e03SGreg Ungerer &clk_fec0, 52*f86b9e03SGreg Ungerer &clk_fec1, 53*f86b9e03SGreg Ungerer NULL 54*f86b9e03SGreg Ungerer }; 55*f86b9e03SGreg Ungerer 56*f86b9e03SGreg Ungerer /***************************************************************************/ 57*f86b9e03SGreg Ungerer 58*f86b9e03SGreg Ungerer static void __init m527x_qspi_init(void) 59*f86b9e03SGreg Ungerer { 60*f86b9e03SGreg Ungerer #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 61*f86b9e03SGreg Ungerer #if defined(CONFIG_M5271) 62*f86b9e03SGreg Ungerer u16 par; 63*f86b9e03SGreg Ungerer 64*f86b9e03SGreg Ungerer /* setup QSPS pins for QSPI with gpio CS control */ 65*f86b9e03SGreg Ungerer writeb(0x1f, MCFGPIO_PAR_QSPI); 66*f86b9e03SGreg Ungerer /* and CS2 & CS3 as gpio */ 67*f86b9e03SGreg Ungerer par = readw(MCFGPIO_PAR_TIMER); 68*f86b9e03SGreg Ungerer par &= 0x3f3f; 69*f86b9e03SGreg Ungerer writew(par, MCFGPIO_PAR_TIMER); 70*f86b9e03SGreg Ungerer #elif defined(CONFIG_M5275) 71*f86b9e03SGreg Ungerer /* setup QSPS pins for QSPI with gpio CS control */ 72*f86b9e03SGreg Ungerer writew(0x003e, MCFGPIO_PAR_QSPI); 73*f86b9e03SGreg Ungerer #endif 74*f86b9e03SGreg Ungerer #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 75*f86b9e03SGreg Ungerer } 76*f86b9e03SGreg Ungerer 77*f86b9e03SGreg Ungerer /***************************************************************************/ 78*f86b9e03SGreg Ungerer 79*f86b9e03SGreg Ungerer static void __init m527x_uarts_init(void) 80*f86b9e03SGreg Ungerer { 81*f86b9e03SGreg Ungerer u16 sepmask; 82*f86b9e03SGreg Ungerer 83*f86b9e03SGreg Ungerer /* 84*f86b9e03SGreg Ungerer * External Pin Mask Setting & Enable External Pin for Interface 85*f86b9e03SGreg Ungerer */ 86*f86b9e03SGreg Ungerer sepmask = readw(MCFGPIO_PAR_UART); 87*f86b9e03SGreg Ungerer sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; 88*f86b9e03SGreg Ungerer writew(sepmask, MCFGPIO_PAR_UART); 89*f86b9e03SGreg Ungerer } 90*f86b9e03SGreg Ungerer 91*f86b9e03SGreg Ungerer /***************************************************************************/ 92*f86b9e03SGreg Ungerer 93*f86b9e03SGreg Ungerer static void __init m527x_fec_init(void) 94*f86b9e03SGreg Ungerer { 95*f86b9e03SGreg Ungerer u16 par; 96*f86b9e03SGreg Ungerer u8 v; 97*f86b9e03SGreg Ungerer 98*f86b9e03SGreg Ungerer /* Set multi-function pins to ethernet mode for fec0 */ 99*f86b9e03SGreg Ungerer #if defined(CONFIG_M5271) 100*f86b9e03SGreg Ungerer v = readb(MCFGPIO_PAR_FECI2C); 101*f86b9e03SGreg Ungerer writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); 102*f86b9e03SGreg Ungerer #else 103*f86b9e03SGreg Ungerer par = readw(MCFGPIO_PAR_FECI2C); 104*f86b9e03SGreg Ungerer writew(par | 0xf00, MCFGPIO_PAR_FECI2C); 105*f86b9e03SGreg Ungerer v = readb(MCFGPIO_PAR_FEC0HL); 106*f86b9e03SGreg Ungerer writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); 107*f86b9e03SGreg Ungerer 108*f86b9e03SGreg Ungerer /* Set multi-function pins to ethernet mode for fec1 */ 109*f86b9e03SGreg Ungerer par = readw(MCFGPIO_PAR_FECI2C); 110*f86b9e03SGreg Ungerer writew(par | 0xa0, MCFGPIO_PAR_FECI2C); 111*f86b9e03SGreg Ungerer v = readb(MCFGPIO_PAR_FEC1HL); 112*f86b9e03SGreg Ungerer writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); 113*f86b9e03SGreg Ungerer #endif 114*f86b9e03SGreg Ungerer } 115*f86b9e03SGreg Ungerer 116*f86b9e03SGreg Ungerer /***************************************************************************/ 117*f86b9e03SGreg Ungerer 118*f86b9e03SGreg Ungerer void __init config_BSP(char *commandp, int size) 119*f86b9e03SGreg Ungerer { 120*f86b9e03SGreg Ungerer mach_sched_init = hw_timer_init; 121*f86b9e03SGreg Ungerer m527x_uarts_init(); 122*f86b9e03SGreg Ungerer m527x_fec_init(); 123*f86b9e03SGreg Ungerer m527x_qspi_init(); 124*f86b9e03SGreg Ungerer } 125*f86b9e03SGreg Ungerer 126*f86b9e03SGreg Ungerer /***************************************************************************/ 127