1 // SPDX-License-Identifier: GPL-2.0 2 /***************************************************************************/ 3 4 /* 5 * m5272.c -- platform support for ColdFire 5272 based boards 6 * 7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) 8 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com) 9 */ 10 11 /***************************************************************************/ 12 13 #include <linux/clkdev.h> 14 #include <linux/kernel.h> 15 #include <linux/param.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/phy.h> 19 #include <asm/machdep.h> 20 #include <asm/coldfire.h> 21 #include <asm/mcfsim.h> 22 #include <asm/mcfuart.h> 23 #include <asm/mcfclk.h> 24 25 /***************************************************************************/ 26 27 /* 28 * Some platforms need software versions of the GPIO data registers. 29 */ 30 unsigned short ppdata; 31 unsigned char ledbank = 0xff; 32 33 /***************************************************************************/ 34 35 DEFINE_CLK(pll, "pll.0", MCF_CLK); 36 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 37 38 static struct clk_lookup m5272_clk_lookup[] = { 39 CLKDEV_INIT(NULL, "pll.0", &clk_pll), 40 CLKDEV_INIT(NULL, "sys.0", &clk_sys), 41 CLKDEV_INIT("mcftmr.0", NULL, &clk_sys), 42 CLKDEV_INIT("mcftmr.1", NULL, &clk_sys), 43 CLKDEV_INIT("mcftmr.2", NULL, &clk_sys), 44 CLKDEV_INIT("mcftmr.3", NULL, &clk_sys), 45 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), 46 CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), 47 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), 48 CLKDEV_INIT("fec.0", NULL, &clk_sys), 49 }; 50 51 /***************************************************************************/ 52 53 static void __init m5272_uarts_init(void) 54 { 55 u32 v; 56 57 /* Enable the output lines for the serial ports */ 58 v = readl(MCFSIM_PBCNT); 59 v = (v & ~0x000000ff) | 0x00000055; 60 writel(v, MCFSIM_PBCNT); 61 62 v = readl(MCFSIM_PDCNT); 63 v = (v & ~0x000003fc) | 0x000002a8; 64 writel(v, MCFSIM_PDCNT); 65 } 66 67 /***************************************************************************/ 68 69 static void m5272_cpu_reset(void) 70 { 71 local_irq_disable(); 72 /* Set watchdog to reset, and enabled */ 73 __raw_writew(0, MCFSIM_WIRR); 74 __raw_writew(1, MCFSIM_WRRR); 75 __raw_writew(0, MCFSIM_WCR); 76 for (;;) 77 /* wait for watchdog to timeout */; 78 } 79 80 /***************************************************************************/ 81 82 void __init config_BSP(char *commandp, int size) 83 { 84 #if defined (CONFIG_MOD5272) 85 /* Set base of device vectors to be 64 */ 86 writeb(0x40, MCFSIM_PIVR); 87 #endif 88 89 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) 90 /* Copy command line from FLASH to local buffer... */ 91 memcpy(commandp, (char *) 0xf0004000, size); 92 commandp[size-1] = 0; 93 #elif defined(CONFIG_CANCam) 94 /* Copy command line from FLASH to local buffer... */ 95 memcpy(commandp, (char *) 0xf0010000, size); 96 commandp[size-1] = 0; 97 #endif 98 99 mach_reset = m5272_cpu_reset; 100 mach_sched_init = hw_timer_init; 101 } 102 103 /***************************************************************************/ 104 105 static int __init init_BSP(void) 106 { 107 m5272_uarts_init(); 108 clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup)); 109 return 0; 110 } 111 112 arch_initcall(init_BSP); 113 114 /***************************************************************************/ 115