1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2f86b9e03SGreg Ungerer /***************************************************************************/ 3f86b9e03SGreg Ungerer 4f86b9e03SGreg Ungerer /* 5ece9ae65SGreg Ungerer * m523x.c -- platform support for ColdFire 523x based boards 6f86b9e03SGreg Ungerer * 7f86b9e03SGreg Ungerer * Sub-architcture dependent initialization code for the Freescale 8f86b9e03SGreg Ungerer * 523x CPUs. 9f86b9e03SGreg Ungerer * 10f86b9e03SGreg Ungerer * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com) 11f86b9e03SGreg Ungerer * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) 12f86b9e03SGreg Ungerer */ 13f86b9e03SGreg Ungerer 14f86b9e03SGreg Ungerer /***************************************************************************/ 15f86b9e03SGreg Ungerer 16f86b9e03SGreg Ungerer #include <linux/kernel.h> 17f86b9e03SGreg Ungerer #include <linux/param.h> 18f86b9e03SGreg Ungerer #include <linux/init.h> 19f86b9e03SGreg Ungerer #include <linux/io.h> 20f86b9e03SGreg Ungerer #include <asm/machdep.h> 21f86b9e03SGreg Ungerer #include <asm/coldfire.h> 22f86b9e03SGreg Ungerer #include <asm/mcfsim.h> 23f86b9e03SGreg Ungerer #include <asm/mcfclk.h> 24f86b9e03SGreg Ungerer 25f86b9e03SGreg Ungerer /***************************************************************************/ 26f86b9e03SGreg Ungerer 27f86b9e03SGreg Ungerer DEFINE_CLK(pll, "pll.0", MCF_CLK); 28f86b9e03SGreg Ungerer DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 29f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK); 30f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK); 31f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK); 32f86b9e03SGreg Ungerer DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK); 33f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 34f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 35f86b9e03SGreg Ungerer DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 36f86b9e03SGreg Ungerer DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 37f86b9e03SGreg Ungerer DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); 382d24b532SSteven King DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); 39f86b9e03SGreg Ungerer 40f86b9e03SGreg Ungerer struct clk *mcf_clks[] = { 41f86b9e03SGreg Ungerer &clk_pll, 42f86b9e03SGreg Ungerer &clk_sys, 43f86b9e03SGreg Ungerer &clk_mcfpit0, 44f86b9e03SGreg Ungerer &clk_mcfpit1, 45f86b9e03SGreg Ungerer &clk_mcfpit2, 46f86b9e03SGreg Ungerer &clk_mcfpit3, 47f86b9e03SGreg Ungerer &clk_mcfuart0, 48f86b9e03SGreg Ungerer &clk_mcfuart1, 49f86b9e03SGreg Ungerer &clk_mcfuart2, 50f86b9e03SGreg Ungerer &clk_mcfqspi0, 51f86b9e03SGreg Ungerer &clk_fec0, 522d24b532SSteven King &clk_mcfi2c0, 53f86b9e03SGreg Ungerer NULL 54f86b9e03SGreg Ungerer }; 55f86b9e03SGreg Ungerer 56f86b9e03SGreg Ungerer /***************************************************************************/ 57f86b9e03SGreg Ungerer 58f86b9e03SGreg Ungerer static void __init m523x_qspi_init(void) 59f86b9e03SGreg Ungerer { 60f86b9e03SGreg Ungerer #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 61f86b9e03SGreg Ungerer u16 par; 62f86b9e03SGreg Ungerer 63f86b9e03SGreg Ungerer /* setup QSPS pins for QSPI with gpio CS control */ 64f86b9e03SGreg Ungerer writeb(0x1f, MCFGPIO_PAR_QSPI); 65f86b9e03SGreg Ungerer /* and CS2 & CS3 as gpio */ 66f86b9e03SGreg Ungerer par = readw(MCFGPIO_PAR_TIMER); 67f86b9e03SGreg Ungerer par &= 0x3f3f; 68f86b9e03SGreg Ungerer writew(par, MCFGPIO_PAR_TIMER); 69f86b9e03SGreg Ungerer #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 70f86b9e03SGreg Ungerer } 71f86b9e03SGreg Ungerer 72f86b9e03SGreg Ungerer /***************************************************************************/ 73f86b9e03SGreg Ungerer 742d24b532SSteven King static void __init m523x_i2c_init(void) 752d24b532SSteven King { 762d24b532SSteven King #if IS_ENABLED(CONFIG_I2C_IMX) 772d24b532SSteven King u8 par; 782d24b532SSteven King 792d24b532SSteven King /* setup Port AS Pin Assignment Register for I2C */ 802d24b532SSteven King /* set PASPA0 to SCL and PASPA1 to SDA */ 812d24b532SSteven King par = readb(MCFGPIO_PAR_FECI2C); 822d24b532SSteven King par |= 0x0f; 832d24b532SSteven King writeb(par, MCFGPIO_PAR_FECI2C); 842d24b532SSteven King #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 852d24b532SSteven King } 862d24b532SSteven King 872d24b532SSteven King /***************************************************************************/ 882d24b532SSteven King 89f86b9e03SGreg Ungerer static void __init m523x_fec_init(void) 90f86b9e03SGreg Ungerer { 91f86b9e03SGreg Ungerer /* Set multi-function pins to ethernet use */ 92f86b9e03SGreg Ungerer writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C); 93f86b9e03SGreg Ungerer } 94f86b9e03SGreg Ungerer 95f86b9e03SGreg Ungerer /***************************************************************************/ 96f86b9e03SGreg Ungerer 97f86b9e03SGreg Ungerer void __init config_BSP(char *commandp, int size) 98f86b9e03SGreg Ungerer { 99f86b9e03SGreg Ungerer mach_sched_init = hw_timer_init; 100f86b9e03SGreg Ungerer m523x_fec_init(); 101f86b9e03SGreg Ungerer m523x_qspi_init(); 1022d24b532SSteven King m523x_i2c_init(); 103f86b9e03SGreg Ungerer } 104f86b9e03SGreg Ungerer 105f86b9e03SGreg Ungerer /***************************************************************************/ 106