1*f86b9e03SGreg Ungerer /*
2*f86b9e03SGreg Ungerer * intc2.c -- support for the 2nd INTC controller of the 525x
3*f86b9e03SGreg Ungerer *
4*f86b9e03SGreg Ungerer * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5*f86b9e03SGreg Ungerer * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
6*f86b9e03SGreg Ungerer *
7*f86b9e03SGreg Ungerer * This file is subject to the terms and conditions of the GNU General Public
8*f86b9e03SGreg Ungerer * License. See the file COPYING in the main directory of this archive
9*f86b9e03SGreg Ungerer * for more details.
10*f86b9e03SGreg Ungerer */
11*f86b9e03SGreg Ungerer
12*f86b9e03SGreg Ungerer #include <linux/types.h>
13*f86b9e03SGreg Ungerer #include <linux/init.h>
14*f86b9e03SGreg Ungerer #include <linux/kernel.h>
15*f86b9e03SGreg Ungerer #include <linux/interrupt.h>
16*f86b9e03SGreg Ungerer #include <linux/irq.h>
17*f86b9e03SGreg Ungerer #include <linux/io.h>
18*f86b9e03SGreg Ungerer #include <asm/coldfire.h>
19*f86b9e03SGreg Ungerer #include <asm/mcfsim.h>
20*f86b9e03SGreg Ungerer
intc2_irq_gpio_mask(struct irq_data * d)21*f86b9e03SGreg Ungerer static void intc2_irq_gpio_mask(struct irq_data *d)
22*f86b9e03SGreg Ungerer {
23*f86b9e03SGreg Ungerer u32 imr = readl(MCFSIM2_GPIOINTENABLE);
24*f86b9e03SGreg Ungerer u32 type = irqd_get_trigger_type(d);
25*f86b9e03SGreg Ungerer int irq = d->irq - MCF_IRQ_GPIO0;
26*f86b9e03SGreg Ungerer
27*f86b9e03SGreg Ungerer if (type & IRQ_TYPE_EDGE_RISING)
28*f86b9e03SGreg Ungerer imr &= ~(0x001 << irq);
29*f86b9e03SGreg Ungerer if (type & IRQ_TYPE_EDGE_FALLING)
30*f86b9e03SGreg Ungerer imr &= ~(0x100 << irq);
31*f86b9e03SGreg Ungerer writel(imr, MCFSIM2_GPIOINTENABLE);
32*f86b9e03SGreg Ungerer }
33*f86b9e03SGreg Ungerer
intc2_irq_gpio_unmask(struct irq_data * d)34*f86b9e03SGreg Ungerer static void intc2_irq_gpio_unmask(struct irq_data *d)
35*f86b9e03SGreg Ungerer {
36*f86b9e03SGreg Ungerer u32 imr = readl(MCFSIM2_GPIOINTENABLE);
37*f86b9e03SGreg Ungerer u32 type = irqd_get_trigger_type(d);
38*f86b9e03SGreg Ungerer int irq = d->irq - MCF_IRQ_GPIO0;
39*f86b9e03SGreg Ungerer
40*f86b9e03SGreg Ungerer if (type & IRQ_TYPE_EDGE_RISING)
41*f86b9e03SGreg Ungerer imr |= (0x001 << irq);
42*f86b9e03SGreg Ungerer if (type & IRQ_TYPE_EDGE_FALLING)
43*f86b9e03SGreg Ungerer imr |= (0x100 << irq);
44*f86b9e03SGreg Ungerer writel(imr, MCFSIM2_GPIOINTENABLE);
45*f86b9e03SGreg Ungerer }
46*f86b9e03SGreg Ungerer
intc2_irq_gpio_ack(struct irq_data * d)47*f86b9e03SGreg Ungerer static void intc2_irq_gpio_ack(struct irq_data *d)
48*f86b9e03SGreg Ungerer {
49*f86b9e03SGreg Ungerer u32 imr = 0;
50*f86b9e03SGreg Ungerer u32 type = irqd_get_trigger_type(d);
51*f86b9e03SGreg Ungerer int irq = d->irq - MCF_IRQ_GPIO0;
52*f86b9e03SGreg Ungerer
53*f86b9e03SGreg Ungerer if (type & IRQ_TYPE_EDGE_RISING)
54*f86b9e03SGreg Ungerer imr |= (0x001 << irq);
55*f86b9e03SGreg Ungerer if (type & IRQ_TYPE_EDGE_FALLING)
56*f86b9e03SGreg Ungerer imr |= (0x100 << irq);
57*f86b9e03SGreg Ungerer writel(imr, MCFSIM2_GPIOINTCLEAR);
58*f86b9e03SGreg Ungerer }
59*f86b9e03SGreg Ungerer
intc2_irq_gpio_set_type(struct irq_data * d,unsigned int f)60*f86b9e03SGreg Ungerer static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
61*f86b9e03SGreg Ungerer {
62*f86b9e03SGreg Ungerer if (f & ~IRQ_TYPE_EDGE_BOTH)
63*f86b9e03SGreg Ungerer return -EINVAL;
64*f86b9e03SGreg Ungerer return 0;
65*f86b9e03SGreg Ungerer }
66*f86b9e03SGreg Ungerer
67*f86b9e03SGreg Ungerer static struct irq_chip intc2_irq_gpio_chip = {
68*f86b9e03SGreg Ungerer .name = "CF-INTC2",
69*f86b9e03SGreg Ungerer .irq_mask = intc2_irq_gpio_mask,
70*f86b9e03SGreg Ungerer .irq_unmask = intc2_irq_gpio_unmask,
71*f86b9e03SGreg Ungerer .irq_ack = intc2_irq_gpio_ack,
72*f86b9e03SGreg Ungerer .irq_set_type = intc2_irq_gpio_set_type,
73*f86b9e03SGreg Ungerer };
74*f86b9e03SGreg Ungerer
mcf_intc2_init(void)75*f86b9e03SGreg Ungerer static int __init mcf_intc2_init(void)
76*f86b9e03SGreg Ungerer {
77*f86b9e03SGreg Ungerer int irq;
78*f86b9e03SGreg Ungerer
79*f86b9e03SGreg Ungerer /* set the interrupt base for the second interrupt controller */
80*f86b9e03SGreg Ungerer writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
81*f86b9e03SGreg Ungerer
82*f86b9e03SGreg Ungerer /* GPIO interrupt sources */
83*f86b9e03SGreg Ungerer for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
84*f86b9e03SGreg Ungerer irq_set_chip(irq, &intc2_irq_gpio_chip);
85*f86b9e03SGreg Ungerer irq_set_handler(irq, handle_edge_irq);
86*f86b9e03SGreg Ungerer }
87*f86b9e03SGreg Ungerer
88*f86b9e03SGreg Ungerer return 0;
89*f86b9e03SGreg Ungerer }
90*f86b9e03SGreg Ungerer
91*f86b9e03SGreg Ungerer arch_initcall(mcf_intc2_init);
92