1f86b9e03SGreg Ungerer /* 2f86b9e03SGreg Ungerer * dma_timer.c -- Freescale ColdFire DMA Timer. 3f86b9e03SGreg Ungerer * 4f86b9e03SGreg Ungerer * Copyright (C) 2007, Benedikt Spranger <b.spranger@linutronix.de> 5f86b9e03SGreg Ungerer * Copyright (C) 2008. Sebastian Siewior, Linutronix 6f86b9e03SGreg Ungerer * 7f86b9e03SGreg Ungerer */ 8f86b9e03SGreg Ungerer 9f86b9e03SGreg Ungerer #include <linux/clocksource.h> 10f86b9e03SGreg Ungerer #include <linux/io.h> 11f86b9e03SGreg Ungerer 12f86b9e03SGreg Ungerer #include <asm/machdep.h> 13f86b9e03SGreg Ungerer #include <asm/coldfire.h> 14f86b9e03SGreg Ungerer #include <asm/mcfpit.h> 15f86b9e03SGreg Ungerer #include <asm/mcfsim.h> 16f86b9e03SGreg Ungerer 17f86b9e03SGreg Ungerer #define DMA_TIMER_0 (0x00) 18f86b9e03SGreg Ungerer #define DMA_TIMER_1 (0x40) 19f86b9e03SGreg Ungerer #define DMA_TIMER_2 (0x80) 20f86b9e03SGreg Ungerer #define DMA_TIMER_3 (0xc0) 21f86b9e03SGreg Ungerer 22f86b9e03SGreg Ungerer #define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400) 23f86b9e03SGreg Ungerer #define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402) 24f86b9e03SGreg Ungerer #define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403) 25f86b9e03SGreg Ungerer #define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404) 26f86b9e03SGreg Ungerer #define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408) 27f86b9e03SGreg Ungerer #define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c) 28f86b9e03SGreg Ungerer 29f86b9e03SGreg Ungerer #define DMA_FREQ ((MCF_CLK / 2) / 16) 30f86b9e03SGreg Ungerer 31f86b9e03SGreg Ungerer /* DTMR */ 32f86b9e03SGreg Ungerer #define DMA_DTMR_RESTART (1 << 3) 33f86b9e03SGreg Ungerer #define DMA_DTMR_CLK_DIV_1 (1 << 1) 34f86b9e03SGreg Ungerer #define DMA_DTMR_CLK_DIV_16 (2 << 1) 35f86b9e03SGreg Ungerer #define DMA_DTMR_ENABLE (1 << 0) 36f86b9e03SGreg Ungerer 37*a5a1d1c2SThomas Gleixner static u64 cf_dt_get_cycles(struct clocksource *cs) 38f86b9e03SGreg Ungerer { 39f86b9e03SGreg Ungerer return __raw_readl(DTCN0); 40f86b9e03SGreg Ungerer } 41f86b9e03SGreg Ungerer 42f86b9e03SGreg Ungerer static struct clocksource clocksource_cf_dt = { 43f86b9e03SGreg Ungerer .name = "coldfire_dma_timer", 44f86b9e03SGreg Ungerer .rating = 200, 45f86b9e03SGreg Ungerer .read = cf_dt_get_cycles, 46f86b9e03SGreg Ungerer .mask = CLOCKSOURCE_MASK(32), 47f86b9e03SGreg Ungerer .flags = CLOCK_SOURCE_IS_CONTINUOUS, 48f86b9e03SGreg Ungerer }; 49f86b9e03SGreg Ungerer 50f86b9e03SGreg Ungerer static int __init init_cf_dt_clocksource(void) 51f86b9e03SGreg Ungerer { 52f86b9e03SGreg Ungerer /* 53f86b9e03SGreg Ungerer * We setup DMA timer 0 in free run mode. This incrementing counter is 54f86b9e03SGreg Ungerer * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we 55f86b9e03SGreg Ungerer * get a ~213 ns resolution and the 32bit register will overflow almost 56f86b9e03SGreg Ungerer * every 15 minutes. 57f86b9e03SGreg Ungerer */ 58f86b9e03SGreg Ungerer __raw_writeb(0x00, DTXMR0); 59f86b9e03SGreg Ungerer __raw_writeb(0x00, DTER0); 60f86b9e03SGreg Ungerer __raw_writel(0x00000000, DTRR0); 61f86b9e03SGreg Ungerer __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0); 62f86b9e03SGreg Ungerer return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ); 63f86b9e03SGreg Ungerer } 64f86b9e03SGreg Ungerer 65f86b9e03SGreg Ungerer arch_initcall(init_cf_dt_clocksource); 66f86b9e03SGreg Ungerer 67f86b9e03SGreg Ungerer #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ 68f86b9e03SGreg Ungerer #define CYC2NS_SCALE ((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000)) 69f86b9e03SGreg Ungerer 70f86b9e03SGreg Ungerer static unsigned long long cycles2ns(unsigned long cycl) 71f86b9e03SGreg Ungerer { 72f86b9e03SGreg Ungerer return (unsigned long long) ((unsigned long long)cycl * 73f86b9e03SGreg Ungerer CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR; 74f86b9e03SGreg Ungerer } 75f86b9e03SGreg Ungerer 76f86b9e03SGreg Ungerer unsigned long long sched_clock(void) 77f86b9e03SGreg Ungerer { 78f86b9e03SGreg Ungerer unsigned long cycl = __raw_readl(DTCN0); 79f86b9e03SGreg Ungerer 80f86b9e03SGreg Ungerer return cycles2ns(cycl); 81f86b9e03SGreg Ungerer } 82