xref: /linux/arch/m68k/coldfire/dma_timer.c (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2f86b9e03SGreg Ungerer /*
3f86b9e03SGreg Ungerer  * dma_timer.c -- Freescale ColdFire DMA Timer.
4f86b9e03SGreg Ungerer  *
5f86b9e03SGreg Ungerer  * Copyright (C) 2007, Benedikt Spranger <b.spranger@linutronix.de>
6f86b9e03SGreg Ungerer  * Copyright (C) 2008. Sebastian Siewior, Linutronix
7f86b9e03SGreg Ungerer  *
8f86b9e03SGreg Ungerer  */
9f86b9e03SGreg Ungerer 
10f86b9e03SGreg Ungerer #include <linux/clocksource.h>
11f86b9e03SGreg Ungerer #include <linux/io.h>
12f86b9e03SGreg Ungerer 
13f86b9e03SGreg Ungerer #include <asm/machdep.h>
14f86b9e03SGreg Ungerer #include <asm/coldfire.h>
15f86b9e03SGreg Ungerer #include <asm/mcfpit.h>
16f86b9e03SGreg Ungerer #include <asm/mcfsim.h>
17f86b9e03SGreg Ungerer 
18f86b9e03SGreg Ungerer #define DMA_TIMER_0	(0x00)
19f86b9e03SGreg Ungerer #define DMA_TIMER_1	(0x40)
20f86b9e03SGreg Ungerer #define DMA_TIMER_2	(0x80)
21f86b9e03SGreg Ungerer #define DMA_TIMER_3	(0xc0)
22f86b9e03SGreg Ungerer 
23f86b9e03SGreg Ungerer #define DTMR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x400)
24f86b9e03SGreg Ungerer #define DTXMR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x402)
25f86b9e03SGreg Ungerer #define DTER0	(MCF_IPSBAR + DMA_TIMER_0 + 0x403)
26f86b9e03SGreg Ungerer #define DTRR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x404)
27f86b9e03SGreg Ungerer #define DTCR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x408)
28f86b9e03SGreg Ungerer #define DTCN0	(MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
29f86b9e03SGreg Ungerer 
30f86b9e03SGreg Ungerer #define DMA_FREQ    ((MCF_CLK / 2) / 16)
31f86b9e03SGreg Ungerer 
32f86b9e03SGreg Ungerer /* DTMR */
33f86b9e03SGreg Ungerer #define DMA_DTMR_RESTART	(1 << 3)
34f86b9e03SGreg Ungerer #define DMA_DTMR_CLK_DIV_1	(1 << 1)
35f86b9e03SGreg Ungerer #define DMA_DTMR_CLK_DIV_16	(2 << 1)
36f86b9e03SGreg Ungerer #define DMA_DTMR_ENABLE		(1 << 0)
37f86b9e03SGreg Ungerer 
cf_dt_get_cycles(struct clocksource * cs)38a5a1d1c2SThomas Gleixner static u64 cf_dt_get_cycles(struct clocksource *cs)
39f86b9e03SGreg Ungerer {
40f86b9e03SGreg Ungerer 	return __raw_readl(DTCN0);
41f86b9e03SGreg Ungerer }
42f86b9e03SGreg Ungerer 
43f86b9e03SGreg Ungerer static struct clocksource clocksource_cf_dt = {
44f86b9e03SGreg Ungerer 	.name		= "coldfire_dma_timer",
45f86b9e03SGreg Ungerer 	.rating		= 200,
46f86b9e03SGreg Ungerer 	.read		= cf_dt_get_cycles,
47f86b9e03SGreg Ungerer 	.mask		= CLOCKSOURCE_MASK(32),
48f86b9e03SGreg Ungerer 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
49f86b9e03SGreg Ungerer };
50f86b9e03SGreg Ungerer 
init_cf_dt_clocksource(void)51f86b9e03SGreg Ungerer static int __init init_cf_dt_clocksource(void)
52f86b9e03SGreg Ungerer {
53f86b9e03SGreg Ungerer 	/*
54f86b9e03SGreg Ungerer 	 * We setup DMA timer 0 in free run mode. This incrementing counter is
55f86b9e03SGreg Ungerer 	 * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we
56f86b9e03SGreg Ungerer 	 * get a ~213 ns resolution and the 32bit register will overflow almost
57f86b9e03SGreg Ungerer 	 * every 15 minutes.
58f86b9e03SGreg Ungerer 	 */
59f86b9e03SGreg Ungerer 	__raw_writeb(0x00, DTXMR0);
60f86b9e03SGreg Ungerer 	__raw_writeb(0x00, DTER0);
61f86b9e03SGreg Ungerer 	__raw_writel(0x00000000, DTRR0);
62f86b9e03SGreg Ungerer 	__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
63f86b9e03SGreg Ungerer 	return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
64f86b9e03SGreg Ungerer }
65f86b9e03SGreg Ungerer 
66f86b9e03SGreg Ungerer arch_initcall(init_cf_dt_clocksource);
67f86b9e03SGreg Ungerer 
68f86b9e03SGreg Ungerer #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
69f86b9e03SGreg Ungerer #define CYC2NS_SCALE	((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000))
70f86b9e03SGreg Ungerer 
cycles2ns(unsigned long cycl)71f86b9e03SGreg Ungerer static unsigned long long cycles2ns(unsigned long cycl)
72f86b9e03SGreg Ungerer {
73f86b9e03SGreg Ungerer 	return (unsigned long long) ((unsigned long long)cycl *
74f86b9e03SGreg Ungerer 			CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR;
75f86b9e03SGreg Ungerer }
76f86b9e03SGreg Ungerer 
sched_clock(void)77f86b9e03SGreg Ungerer unsigned long long sched_clock(void)
78f86b9e03SGreg Ungerer {
79f86b9e03SGreg Ungerer 	unsigned long cycl = __raw_readl(DTCN0);
80f86b9e03SGreg Ungerer 
81f86b9e03SGreg Ungerer 	return cycles2ns(cycl);
82f86b9e03SGreg Ungerer }
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