1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1993 Hamish Macdonald 4 * Copyright (C) 1999 D. Jeff Dionne 5 * Copyright (C) 2001 Georges Menie, Ken Desmet 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/init.h> 12 #include <asm/machdep.h> 13 #include <asm/MC68VZ328.h> 14 #include "m68328.h" 15 #include "screen.h" 16 17 /***************************************************************************/ 18 /* Init Dragon Engine II hardware */ 19 /***************************************************************************/ 20 21 static void dragen2_reset(void) 22 { 23 local_irq_disable(); 24 25 #ifdef CONFIG_INIT_LCD 26 PBDATA |= 0x20; /* disable CCFL light */ 27 PKDATA |= 0x4; /* disable LCD controller */ 28 LCKCON = 0; 29 #endif 30 31 __asm__ __volatile__( 32 "reset\n\t" 33 "moveal #0x04000000, %a0\n\t" 34 "moveal 0(%a0), %sp\n\t" 35 "moveal 4(%a0), %a0\n\t" 36 "jmp (%a0)" 37 ); 38 } 39 40 void __init init_dragen2(char *command, int size) 41 { 42 mach_reset = dragen2_reset; 43 44 #ifdef CONFIG_DIRECT_IO_ACCESS 45 SCR = 0x10; /* allow user access to internal registers */ 46 #endif 47 48 /* CSGB Init */ 49 CSGBB = 0x4000; 50 CSB = 0x1a1; 51 52 /* CS8900 init */ 53 /* PK3: hardware sleep function pin, active low */ 54 PKSEL |= PK(3); /* select pin as I/O */ 55 PKDIR |= PK(3); /* select pin as output */ 56 PKDATA |= PK(3); /* set pin high */ 57 58 /* PF5: hardware reset function pin, active high */ 59 PFSEL |= PF(5); /* select pin as I/O */ 60 PFDIR |= PF(5); /* select pin as output */ 61 PFDATA &= ~PF(5); /* set pin low */ 62 63 /* cs8900 hardware reset */ 64 PFDATA |= PF(5); 65 { int i; for (i = 0; i < 32000; ++i); } 66 PFDATA &= ~PF(5); 67 68 /* INT1 enable (cs8900 IRQ) */ 69 PDPOL &= ~PD(1); /* active high signal */ 70 PDIQEG &= ~PD(1); 71 PDIRQEN |= PD(1); /* IRQ enabled */ 72 73 #ifdef CONFIG_INIT_LCD 74 /* initialize LCD controller */ 75 LSSA = (long) screen_bits; 76 LVPW = 0x14; 77 LXMAX = 0x140; 78 LYMAX = 0xef; 79 LRRA = 0; 80 LPXCD = 3; 81 LPICF = 0x08; 82 LPOLCF = 0; 83 LCKCON = 0x80; 84 PCPDEN = 0xff; 85 PCSEL = 0; 86 87 /* Enable LCD controller */ 88 PKDIR |= 0x4; 89 PKSEL |= 0x4; 90 PKDATA &= ~0x4; 91 92 /* Enable CCFL backlighting circuit */ 93 PBDIR |= 0x20; 94 PBSEL |= 0x20; 95 PBDATA &= ~0x20; 96 97 /* contrast control register */ 98 PFDIR |= 0x1; 99 PFSEL &= ~0x1; 100 PWMR = 0x037F; 101 #endif 102 } 103