1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/bug.h> 9 #include <linux/compiler.h> 10 #include <linux/context_tracking.h> 11 #include <linux/entry-common.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/kexec.h> 15 #include <linux/module.h> 16 #include <linux/export.h> 17 #include <linux/extable.h> 18 #include <linux/mm.h> 19 #include <linux/sched/mm.h> 20 #include <linux/sched/debug.h> 21 #include <linux/smp.h> 22 #include <linux/spinlock.h> 23 #include <linux/kallsyms.h> 24 #include <linux/memblock.h> 25 #include <linux/interrupt.h> 26 #include <linux/ptrace.h> 27 #include <linux/kgdb.h> 28 #include <linux/kdebug.h> 29 #include <linux/notifier.h> 30 #include <linux/irq.h> 31 #include <linux/perf_event.h> 32 33 #include <asm/addrspace.h> 34 #include <asm/bootinfo.h> 35 #include <asm/branch.h> 36 #include <asm/break.h> 37 #include <asm/cpu.h> 38 #include <asm/exception.h> 39 #include <asm/fpu.h> 40 #include <asm/lbt.h> 41 #include <asm/inst.h> 42 #include <asm/kgdb.h> 43 #include <asm/loongarch.h> 44 #include <asm/mmu_context.h> 45 #include <asm/pgtable.h> 46 #include <asm/ptrace.h> 47 #include <asm/sections.h> 48 #include <asm/siginfo.h> 49 #include <asm/stacktrace.h> 50 #include <asm/tlb.h> 51 #include <asm/types.h> 52 #include <asm/unwind.h> 53 #include <asm/uprobes.h> 54 55 #include "access-helper.h" 56 57 void *exception_table[EXCCODE_INT_START] = { 58 [0 ... EXCCODE_INT_START - 1] = handle_reserved, 59 60 [EXCCODE_TLBI] = handle_tlb_load, 61 [EXCCODE_TLBL] = handle_tlb_load, 62 [EXCCODE_TLBS] = handle_tlb_store, 63 [EXCCODE_TLBM] = handle_tlb_modify, 64 [EXCCODE_TLBNR] = handle_tlb_protect, 65 [EXCCODE_TLBNX] = handle_tlb_protect, 66 [EXCCODE_TLBPE] = handle_tlb_protect, 67 [EXCCODE_ADE] = handle_ade, 68 [EXCCODE_ALE] = handle_ale, 69 [EXCCODE_BCE] = handle_bce, 70 [EXCCODE_SYS] = handle_sys, 71 [EXCCODE_BP] = handle_bp, 72 [EXCCODE_INE] = handle_ri, 73 [EXCCODE_IPE] = handle_ri, 74 [EXCCODE_FPDIS] = handle_fpu, 75 [EXCCODE_LSXDIS] = handle_lsx, 76 [EXCCODE_LASXDIS] = handle_lasx, 77 [EXCCODE_FPE] = handle_fpe, 78 [EXCCODE_WATCH] = handle_watch, 79 [EXCCODE_BTDIS] = handle_lbt, 80 }; 81 EXPORT_SYMBOL_GPL(exception_table); 82 83 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs, 84 const char *loglvl, bool user) 85 { 86 unsigned long addr; 87 struct unwind_state state; 88 struct pt_regs *pregs = (struct pt_regs *)regs; 89 90 if (!task) 91 task = current; 92 93 printk("%sCall Trace:", loglvl); 94 for (unwind_start(&state, task, pregs); 95 !unwind_done(&state); unwind_next_frame(&state)) { 96 addr = unwind_get_return_address(&state); 97 print_ip_sym(loglvl, addr); 98 } 99 printk("%s\n", loglvl); 100 } 101 102 static void show_stacktrace(struct task_struct *task, 103 const struct pt_regs *regs, const char *loglvl, bool user) 104 { 105 int i; 106 const int field = 2 * sizeof(unsigned long); 107 unsigned long stackdata; 108 unsigned long *sp = (unsigned long *)regs->regs[3]; 109 110 printk("%sStack :", loglvl); 111 i = 0; 112 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 113 if (i && ((i % (64 / field)) == 0)) { 114 pr_cont("\n"); 115 printk("%s ", loglvl); 116 } 117 if (i > 39) { 118 pr_cont(" ..."); 119 break; 120 } 121 122 if (__get_addr(&stackdata, sp++, user)) { 123 pr_cont(" (Bad stack address)"); 124 break; 125 } 126 127 pr_cont(" %0*lx", field, stackdata); 128 i++; 129 } 130 pr_cont("\n"); 131 show_backtrace(task, regs, loglvl, user); 132 } 133 134 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl) 135 { 136 struct pt_regs regs; 137 138 regs.csr_crmd = 0; 139 if (sp) { 140 regs.csr_era = 0; 141 regs.regs[1] = 0; 142 regs.regs[3] = (unsigned long)sp; 143 } else { 144 if (!task || task == current) 145 prepare_frametrace(®s); 146 else { 147 regs.csr_era = task->thread.reg01; 148 regs.regs[1] = 0; 149 regs.regs[3] = task->thread.reg03; 150 regs.regs[22] = task->thread.reg22; 151 } 152 } 153 154 show_stacktrace(task, ®s, loglvl, false); 155 } 156 157 static void show_code(unsigned int *pc, bool user) 158 { 159 long i; 160 unsigned int insn; 161 162 printk("Code:"); 163 164 for(i = -3 ; i < 6 ; i++) { 165 if (__get_inst(&insn, pc + i, user)) { 166 pr_cont(" (Bad address in era)\n"); 167 break; 168 } 169 pr_cont("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 170 } 171 pr_cont("\n"); 172 } 173 174 static void print_bool_fragment(const char *key, unsigned long val, bool first) 175 { 176 /* e.g. "+PG", "-DA" */ 177 pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key); 178 } 179 180 static void print_plv_fragment(const char *key, int val) 181 { 182 /* e.g. "PLV0", "PPLV3" */ 183 pr_cont("%s%d", key, val); 184 } 185 186 static void print_memory_type_fragment(const char *key, unsigned long val) 187 { 188 const char *humanized_type; 189 190 switch (val) { 191 case 0: 192 humanized_type = "SUC"; 193 break; 194 case 1: 195 humanized_type = "CC"; 196 break; 197 case 2: 198 humanized_type = "WUC"; 199 break; 200 default: 201 pr_cont(" %s=Reserved(%lu)", key, val); 202 return; 203 } 204 205 /* e.g. " DATM=WUC" */ 206 pr_cont(" %s=%s", key, humanized_type); 207 } 208 209 static void print_intr_fragment(const char *key, unsigned long val) 210 { 211 /* e.g. "LIE=0-1,3,5-7" */ 212 pr_cont("%s=%*pbl", key, EXCCODE_INT_NUM, &val); 213 } 214 215 static void print_crmd(unsigned long x) 216 { 217 printk(" CRMD: %08lx (", x); 218 print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x)); 219 print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false); 220 print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false); 221 print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false); 222 print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x)); 223 print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x)); 224 print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), false); 225 pr_cont(")\n"); 226 } 227 228 static void print_prmd(unsigned long x) 229 { 230 printk(" PRMD: %08lx (", x); 231 print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x)); 232 print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false); 233 print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), false); 234 pr_cont(")\n"); 235 } 236 237 static void print_euen(unsigned long x) 238 { 239 printk(" EUEN: %08lx (", x); 240 print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), true); 241 print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false); 242 print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false); 243 print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), false); 244 pr_cont(")\n"); 245 } 246 247 static void print_ecfg(unsigned long x) 248 { 249 printk(" ECFG: %08lx (", x); 250 print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x)); 251 pr_cont(" VS=%d)\n", (int) FIELD_GET(CSR_ECFG_VS, x)); 252 } 253 254 static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode) 255 { 256 /* 257 * LoongArch users and developers are probably more familiar with 258 * those names found in the ISA manual, so we are going to print out 259 * the latter. This will require some mapping. 260 */ 261 switch (ecode) { 262 case EXCCODE_RSV: return "INT"; 263 case EXCCODE_TLBL: return "PIL"; 264 case EXCCODE_TLBS: return "PIS"; 265 case EXCCODE_TLBI: return "PIF"; 266 case EXCCODE_TLBM: return "PME"; 267 case EXCCODE_TLBNR: return "PNR"; 268 case EXCCODE_TLBNX: return "PNX"; 269 case EXCCODE_TLBPE: return "PPI"; 270 case EXCCODE_ADE: 271 switch (esubcode) { 272 case EXSUBCODE_ADEF: return "ADEF"; 273 case EXSUBCODE_ADEM: return "ADEM"; 274 } 275 break; 276 case EXCCODE_ALE: return "ALE"; 277 case EXCCODE_BCE: return "BCE"; 278 case EXCCODE_SYS: return "SYS"; 279 case EXCCODE_BP: return "BRK"; 280 case EXCCODE_INE: return "INE"; 281 case EXCCODE_IPE: return "IPE"; 282 case EXCCODE_FPDIS: return "FPD"; 283 case EXCCODE_LSXDIS: return "SXD"; 284 case EXCCODE_LASXDIS: return "ASXD"; 285 case EXCCODE_FPE: 286 switch (esubcode) { 287 case EXCSUBCODE_FPE: return "FPE"; 288 case EXCSUBCODE_VFPE: return "VFPE"; 289 } 290 break; 291 case EXCCODE_WATCH: 292 switch (esubcode) { 293 case EXCSUBCODE_WPEF: return "WPEF"; 294 case EXCSUBCODE_WPEM: return "WPEM"; 295 } 296 break; 297 case EXCCODE_BTDIS: return "BTD"; 298 case EXCCODE_BTE: return "BTE"; 299 case EXCCODE_GSPR: return "GSPR"; 300 case EXCCODE_HVC: return "HVC"; 301 case EXCCODE_GCM: 302 switch (esubcode) { 303 case EXCSUBCODE_GCSC: return "GCSC"; 304 case EXCSUBCODE_GCHC: return "GCHC"; 305 } 306 break; 307 /* 308 * The manual did not mention the EXCCODE_SE case, but print out it 309 * nevertheless. 310 */ 311 case EXCCODE_SE: return "SE"; 312 } 313 314 return "???"; 315 } 316 317 static void print_estat(unsigned long x) 318 { 319 unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x); 320 unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x); 321 322 printk("ESTAT: %08lx [%s] (", x, humanize_exc_name(ecode, esubcode)); 323 print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x)); 324 pr_cont(" ECode=%d EsubCode=%d)\n", (int) ecode, (int) esubcode); 325 } 326 327 static void __show_regs(const struct pt_regs *regs) 328 { 329 const int field = 2 * sizeof(unsigned long); 330 unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat); 331 332 show_regs_print_info(KERN_DEFAULT); 333 334 /* Print saved GPRs except $zero (substituting with PC/ERA) */ 335 #define GPR_FIELD(x) field, regs->regs[x] 336 printk("pc %0*lx ra %0*lx tp %0*lx sp %0*lx\n", 337 field, regs->csr_era, GPR_FIELD(1), GPR_FIELD(2), GPR_FIELD(3)); 338 printk("a0 %0*lx a1 %0*lx a2 %0*lx a3 %0*lx\n", 339 GPR_FIELD(4), GPR_FIELD(5), GPR_FIELD(6), GPR_FIELD(7)); 340 printk("a4 %0*lx a5 %0*lx a6 %0*lx a7 %0*lx\n", 341 GPR_FIELD(8), GPR_FIELD(9), GPR_FIELD(10), GPR_FIELD(11)); 342 printk("t0 %0*lx t1 %0*lx t2 %0*lx t3 %0*lx\n", 343 GPR_FIELD(12), GPR_FIELD(13), GPR_FIELD(14), GPR_FIELD(15)); 344 printk("t4 %0*lx t5 %0*lx t6 %0*lx t7 %0*lx\n", 345 GPR_FIELD(16), GPR_FIELD(17), GPR_FIELD(18), GPR_FIELD(19)); 346 printk("t8 %0*lx u0 %0*lx s9 %0*lx s0 %0*lx\n", 347 GPR_FIELD(20), GPR_FIELD(21), GPR_FIELD(22), GPR_FIELD(23)); 348 printk("s1 %0*lx s2 %0*lx s3 %0*lx s4 %0*lx\n", 349 GPR_FIELD(24), GPR_FIELD(25), GPR_FIELD(26), GPR_FIELD(27)); 350 printk("s5 %0*lx s6 %0*lx s7 %0*lx s8 %0*lx\n", 351 GPR_FIELD(28), GPR_FIELD(29), GPR_FIELD(30), GPR_FIELD(31)); 352 353 /* The slot for $zero is reused as the syscall restart flag */ 354 if (regs->regs[0]) 355 printk("syscall restart flag: %0*lx\n", GPR_FIELD(0)); 356 357 if (user_mode(regs)) { 358 printk(" ra: %0*lx\n", GPR_FIELD(1)); 359 printk(" ERA: %0*lx\n", field, regs->csr_era); 360 } else { 361 printk(" ra: %0*lx %pS\n", GPR_FIELD(1), (void *) regs->regs[1]); 362 printk(" ERA: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era); 363 } 364 #undef GPR_FIELD 365 366 /* Print saved important CSRs */ 367 print_crmd(regs->csr_crmd); 368 print_prmd(regs->csr_prmd); 369 print_euen(regs->csr_euen); 370 print_ecfg(regs->csr_ecfg); 371 print_estat(regs->csr_estat); 372 373 if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE) 374 printk(" BADV: %0*lx\n", field, regs->csr_badvaddr); 375 376 printk(" PRID: %08x (%s, %s)\n", read_cpucfg(LOONGARCH_CPUCFG0), 377 cpu_family_string(), cpu_full_name_string()); 378 } 379 380 void show_regs(struct pt_regs *regs) 381 { 382 __show_regs((struct pt_regs *)regs); 383 dump_stack(); 384 } 385 386 void show_registers(struct pt_regs *regs) 387 { 388 __show_regs(regs); 389 print_modules(); 390 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 391 current->comm, current->pid, current_thread_info(), current); 392 393 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs)); 394 show_code((void *)regs->csr_era, user_mode(regs)); 395 printk("\n"); 396 } 397 398 static DEFINE_RAW_SPINLOCK(die_lock); 399 400 void die(const char *str, struct pt_regs *regs) 401 { 402 int ret; 403 static int die_counter; 404 405 oops_enter(); 406 407 ret = notify_die(DIE_OOPS, str, regs, 0, 408 current->thread.trap_nr, SIGSEGV); 409 410 console_verbose(); 411 raw_spin_lock_irq(&die_lock); 412 bust_spinlocks(1); 413 414 printk("%s[#%d]:\n", str, ++die_counter); 415 show_registers(regs); 416 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 417 raw_spin_unlock_irq(&die_lock); 418 419 oops_exit(); 420 421 if (ret == NOTIFY_STOP) 422 return; 423 424 if (regs && kexec_should_crash(current)) 425 crash_kexec(regs); 426 427 if (in_interrupt()) 428 panic("Fatal exception in interrupt"); 429 430 if (panic_on_oops) 431 panic("Fatal exception"); 432 433 make_task_dead(SIGSEGV); 434 } 435 436 static inline void setup_vint_size(unsigned int size) 437 { 438 unsigned int vs; 439 440 vs = ilog2(size/4); 441 442 if (vs == 0 || vs > 7) 443 panic("vint_size %d Not support yet", vs); 444 445 csr_xchg32(vs<<CSR_ECFG_VS_SHIFT, CSR_ECFG_VS, LOONGARCH_CSR_ECFG); 446 } 447 448 /* 449 * Send SIGFPE according to FCSR Cause bits, which must have already 450 * been masked against Enable bits. This is impotant as Inexact can 451 * happen together with Overflow or Underflow, and `ptrace' can set 452 * any bits. 453 */ 454 static void force_fcsr_sig(unsigned long fcsr, 455 void __user *fault_addr, struct task_struct *tsk) 456 { 457 int si_code = FPE_FLTUNK; 458 459 if (fcsr & FPU_CSR_INV_X) 460 si_code = FPE_FLTINV; 461 else if (fcsr & FPU_CSR_DIV_X) 462 si_code = FPE_FLTDIV; 463 else if (fcsr & FPU_CSR_OVF_X) 464 si_code = FPE_FLTOVF; 465 else if (fcsr & FPU_CSR_UDF_X) 466 si_code = FPE_FLTUND; 467 else if (fcsr & FPU_CSR_INE_X) 468 si_code = FPE_FLTRES; 469 470 force_sig_fault(SIGFPE, si_code, fault_addr); 471 } 472 473 static int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcsr) 474 { 475 int si_code; 476 477 switch (sig) { 478 case 0: 479 return 0; 480 481 case SIGFPE: 482 force_fcsr_sig(fcsr, fault_addr, current); 483 return 1; 484 485 case SIGBUS: 486 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr); 487 return 1; 488 489 case SIGSEGV: 490 mmap_read_lock(current->mm); 491 if (vma_lookup(current->mm, (unsigned long)fault_addr)) 492 si_code = SEGV_ACCERR; 493 else 494 si_code = SEGV_MAPERR; 495 mmap_read_unlock(current->mm); 496 force_sig_fault(SIGSEGV, si_code, fault_addr); 497 return 1; 498 499 default: 500 force_sig(sig); 501 return 1; 502 } 503 } 504 505 /* 506 * Delayed fp exceptions when doing a lazy ctx switch 507 */ 508 asmlinkage void noinstr do_fpe(struct pt_regs *regs, unsigned long fcsr) 509 { 510 int sig; 511 void __user *fault_addr; 512 irqentry_state_t state = irqentry_enter(regs); 513 514 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 515 SIGFPE) == NOTIFY_STOP) 516 goto out; 517 518 /* Clear FCSR.Cause before enabling interrupts */ 519 write_fcsr(LOONGARCH_FCSR0, fcsr & ~mask_fcsr_x(fcsr)); 520 local_irq_enable(); 521 522 die_if_kernel("FP exception in kernel code", regs); 523 524 sig = SIGFPE; 525 fault_addr = (void __user *) regs->csr_era; 526 527 /* Send a signal if required. */ 528 process_fpemu_return(sig, fault_addr, fcsr); 529 530 out: 531 local_irq_disable(); 532 irqentry_exit(regs, state); 533 } 534 535 asmlinkage void noinstr do_ade(struct pt_regs *regs) 536 { 537 irqentry_state_t state = irqentry_enter(regs); 538 539 die_if_kernel("Kernel ade access", regs); 540 force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)regs->csr_badvaddr); 541 542 irqentry_exit(regs, state); 543 } 544 545 /* sysctl hooks */ 546 int unaligned_enabled __read_mostly = 1; /* Enabled by default */ 547 int no_unaligned_warning __read_mostly = 1; /* Only 1 warning by default */ 548 549 asmlinkage void noinstr do_ale(struct pt_regs *regs) 550 { 551 irqentry_state_t state = irqentry_enter(regs); 552 553 #ifndef CONFIG_ARCH_STRICT_ALIGN 554 die_if_kernel("Kernel ale access", regs); 555 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 556 #else 557 bool pie = regs_irqs_disabled(regs); 558 unsigned int *pc; 559 560 if (!pie) 561 local_irq_enable(); 562 563 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->csr_badvaddr); 564 565 /* 566 * Did we catch a fault trying to load an instruction? 567 */ 568 if (regs->csr_badvaddr == regs->csr_era) 569 goto sigbus; 570 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE)) 571 goto sigbus; 572 if (!unaligned_enabled) 573 goto sigbus; 574 if (!no_unaligned_warning) 575 show_registers(regs); 576 577 pc = (unsigned int *)exception_era(regs); 578 579 emulate_load_store_insn(regs, (void __user *)regs->csr_badvaddr, pc); 580 581 goto out; 582 583 sigbus: 584 die_if_kernel("Kernel ale access", regs); 585 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)regs->csr_badvaddr); 586 out: 587 if (!pie) 588 local_irq_disable(); 589 #endif 590 irqentry_exit(regs, state); 591 } 592 593 #ifdef CONFIG_GENERIC_BUG 594 int is_valid_bugaddr(unsigned long addr) 595 { 596 return 1; 597 } 598 #endif /* CONFIG_GENERIC_BUG */ 599 600 static void bug_handler(struct pt_regs *regs) 601 { 602 if (user_mode(regs)) { 603 force_sig(SIGTRAP); 604 return; 605 } 606 607 switch (report_bug(regs->csr_era, regs)) { 608 case BUG_TRAP_TYPE_BUG: 609 die("Oops - BUG", regs); 610 break; 611 612 case BUG_TRAP_TYPE_WARN: 613 /* Skip the BUG instruction and continue */ 614 regs->csr_era += LOONGARCH_INSN_SIZE; 615 break; 616 617 default: 618 if (!fixup_exception(regs)) 619 die("Oops - BUG", regs); 620 } 621 } 622 623 asmlinkage void noinstr do_bce(struct pt_regs *regs) 624 { 625 bool user = user_mode(regs); 626 bool pie = regs_irqs_disabled(regs); 627 unsigned long era = exception_era(regs); 628 u64 badv = 0, lower = 0, upper = ULONG_MAX; 629 union loongarch_instruction insn; 630 irqentry_state_t state = irqentry_enter(regs); 631 632 if (!pie) 633 local_irq_enable(); 634 635 current->thread.trap_nr = read_csr_excode(); 636 637 die_if_kernel("Bounds check error in kernel code", regs); 638 639 /* 640 * Pull out the address that failed bounds checking, and the lower / 641 * upper bound, by minimally looking at the faulting instruction word 642 * and reading from the correct register. 643 */ 644 if (__get_inst(&insn.word, (u32 *)era, user)) 645 goto bad_era; 646 647 switch (insn.reg3_format.opcode) { 648 case asrtle_op: 649 if (insn.reg3_format.rd != 0) 650 break; /* not asrtle */ 651 badv = regs->regs[insn.reg3_format.rj]; 652 upper = regs->regs[insn.reg3_format.rk]; 653 break; 654 655 case asrtgt_op: 656 if (insn.reg3_format.rd != 0) 657 break; /* not asrtgt */ 658 badv = regs->regs[insn.reg3_format.rj]; 659 lower = regs->regs[insn.reg3_format.rk]; 660 break; 661 662 case ldleb_op: 663 case ldleh_op: 664 case ldlew_op: 665 case ldled_op: 666 case stleb_op: 667 case stleh_op: 668 case stlew_op: 669 case stled_op: 670 case fldles_op: 671 case fldled_op: 672 case fstles_op: 673 case fstled_op: 674 badv = regs->regs[insn.reg3_format.rj]; 675 upper = regs->regs[insn.reg3_format.rk]; 676 break; 677 678 case ldgtb_op: 679 case ldgth_op: 680 case ldgtw_op: 681 case ldgtd_op: 682 case stgtb_op: 683 case stgth_op: 684 case stgtw_op: 685 case stgtd_op: 686 case fldgts_op: 687 case fldgtd_op: 688 case fstgts_op: 689 case fstgtd_op: 690 badv = regs->regs[insn.reg3_format.rj]; 691 lower = regs->regs[insn.reg3_format.rk]; 692 break; 693 } 694 695 force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper); 696 697 out: 698 if (!pie) 699 local_irq_disable(); 700 701 irqentry_exit(regs, state); 702 return; 703 704 bad_era: 705 /* 706 * Cannot pull out the instruction word, hence cannot provide more 707 * info than a regular SIGSEGV in this case. 708 */ 709 force_sig(SIGSEGV); 710 goto out; 711 } 712 713 asmlinkage void noinstr do_bp(struct pt_regs *regs) 714 { 715 bool user = user_mode(regs); 716 bool pie = regs_irqs_disabled(regs); 717 unsigned int opcode, bcode; 718 unsigned long era = exception_era(regs); 719 irqentry_state_t state = irqentry_enter(regs); 720 721 if (!pie) 722 local_irq_enable(); 723 724 if (__get_inst(&opcode, (u32 *)era, user)) 725 goto out_sigsegv; 726 727 bcode = (opcode & 0x7fff); 728 729 /* 730 * notify the kprobe handlers, if instruction is likely to 731 * pertain to them. 732 */ 733 switch (bcode) { 734 case BRK_KDB: 735 if (kgdb_breakpoint_handler(regs)) 736 goto out; 737 else 738 break; 739 case BRK_KPROBE_BP: 740 if (kprobe_breakpoint_handler(regs)) 741 goto out; 742 else 743 break; 744 case BRK_KPROBE_SSTEPBP: 745 if (kprobe_singlestep_handler(regs)) 746 goto out; 747 else 748 break; 749 case BRK_UPROBE_BP: 750 if (uprobe_breakpoint_handler(regs)) 751 goto out; 752 else 753 break; 754 case BRK_UPROBE_XOLBP: 755 if (uprobe_singlestep_handler(regs)) 756 goto out; 757 else 758 break; 759 default: 760 current->thread.trap_nr = read_csr_excode(); 761 if (notify_die(DIE_TRAP, "Break", regs, bcode, 762 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 763 goto out; 764 else 765 break; 766 } 767 768 switch (bcode) { 769 case BRK_BUG: 770 bug_handler(regs); 771 break; 772 case BRK_DIVZERO: 773 die_if_kernel("Break instruction in kernel code", regs); 774 force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->csr_era); 775 break; 776 case BRK_OVERFLOW: 777 die_if_kernel("Break instruction in kernel code", regs); 778 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->csr_era); 779 break; 780 default: 781 die_if_kernel("Break instruction in kernel code", regs); 782 force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->csr_era); 783 break; 784 } 785 786 out: 787 if (!pie) 788 local_irq_disable(); 789 790 irqentry_exit(regs, state); 791 return; 792 793 out_sigsegv: 794 force_sig(SIGSEGV); 795 goto out; 796 } 797 798 asmlinkage void noinstr do_watch(struct pt_regs *regs) 799 { 800 irqentry_state_t state = irqentry_enter(regs); 801 802 #ifndef CONFIG_HAVE_HW_BREAKPOINT 803 pr_warn("Hardware watch point handler not implemented!\n"); 804 #else 805 if (kgdb_breakpoint_handler(regs)) 806 goto out; 807 808 if (test_tsk_thread_flag(current, TIF_SINGLESTEP)) { 809 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1); 810 unsigned long pc = instruction_pointer(regs); 811 union loongarch_instruction *ip = (union loongarch_instruction *)pc; 812 813 if (llbit) { 814 /* 815 * When the ll-sc combo is encountered, it is regarded as an single 816 * instruction. So don't clear llbit and reset CSR.FWPS.Skip until 817 * the llsc execution is completed. 818 */ 819 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 820 csr_write32(CSR_LLBCTL_KLO, LOONGARCH_CSR_LLBCTL); 821 goto out; 822 } 823 824 if (pc == current->thread.single_step) { 825 /* 826 * Certain insns are occasionally not skipped when CSR.FWPS.Skip is 827 * set, such as fld.d/fst.d. So singlestep needs to compare whether 828 * the csr_era is equal to the value of singlestep which last time set. 829 */ 830 if (!is_self_loop_ins(ip, regs)) { 831 /* 832 * Check if the given instruction the target pc is equal to the 833 * current pc, If yes, then we should not set the CSR.FWPS.SKIP 834 * bit to break the original instruction stream. 835 */ 836 csr_write32(CSR_FWPC_SKIP, LOONGARCH_CSR_FWPS); 837 goto out; 838 } 839 } 840 } else { 841 breakpoint_handler(regs); 842 watchpoint_handler(regs); 843 } 844 845 force_sig(SIGTRAP); 846 out: 847 #endif 848 irqentry_exit(regs, state); 849 } 850 851 asmlinkage void noinstr do_ri(struct pt_regs *regs) 852 { 853 int status = SIGILL; 854 unsigned int __maybe_unused opcode; 855 unsigned int __user *era = (unsigned int __user *)exception_era(regs); 856 irqentry_state_t state = irqentry_enter(regs); 857 858 local_irq_enable(); 859 current->thread.trap_nr = read_csr_excode(); 860 861 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 862 SIGILL) == NOTIFY_STOP) 863 goto out; 864 865 die_if_kernel("Reserved instruction in kernel code", regs); 866 867 if (unlikely(get_user(opcode, era) < 0)) { 868 status = SIGSEGV; 869 current->thread.error_code = 1; 870 } 871 872 force_sig(status); 873 874 out: 875 local_irq_disable(); 876 irqentry_exit(regs, state); 877 } 878 879 static void init_restore_fp(void) 880 { 881 if (!used_math()) { 882 /* First time FP context user. */ 883 init_fpu(); 884 } else { 885 /* This task has formerly used the FP context */ 886 if (!is_fpu_owner()) 887 own_fpu_inatomic(1); 888 } 889 890 BUG_ON(!is_fp_enabled()); 891 } 892 893 static void init_restore_lsx(void) 894 { 895 enable_lsx(); 896 897 if (!thread_lsx_context_live()) { 898 /* First time LSX context user */ 899 init_restore_fp(); 900 init_lsx_upper(); 901 set_thread_flag(TIF_LSX_CTX_LIVE); 902 } else { 903 if (!is_simd_owner()) { 904 if (is_fpu_owner()) { 905 restore_lsx_upper(current); 906 } else { 907 __own_fpu(); 908 restore_lsx(current); 909 } 910 } 911 } 912 913 set_thread_flag(TIF_USEDSIMD); 914 915 BUG_ON(!is_fp_enabled()); 916 BUG_ON(!is_lsx_enabled()); 917 } 918 919 static void init_restore_lasx(void) 920 { 921 enable_lasx(); 922 923 if (!thread_lasx_context_live()) { 924 /* First time LASX context user */ 925 init_restore_lsx(); 926 init_lasx_upper(); 927 set_thread_flag(TIF_LASX_CTX_LIVE); 928 } else { 929 if (is_fpu_owner() || is_simd_owner()) { 930 init_restore_lsx(); 931 restore_lasx_upper(current); 932 } else { 933 __own_fpu(); 934 enable_lsx(); 935 restore_lasx(current); 936 } 937 } 938 939 set_thread_flag(TIF_USEDSIMD); 940 941 BUG_ON(!is_fp_enabled()); 942 BUG_ON(!is_lsx_enabled()); 943 BUG_ON(!is_lasx_enabled()); 944 } 945 946 asmlinkage void noinstr do_fpu(struct pt_regs *regs) 947 { 948 irqentry_state_t state = irqentry_enter(regs); 949 950 local_irq_enable(); 951 die_if_kernel("do_fpu invoked from kernel context!", regs); 952 BUG_ON(is_lsx_enabled()); 953 BUG_ON(is_lasx_enabled()); 954 955 preempt_disable(); 956 init_restore_fp(); 957 preempt_enable(); 958 959 local_irq_disable(); 960 irqentry_exit(regs, state); 961 } 962 963 asmlinkage void noinstr do_lsx(struct pt_regs *regs) 964 { 965 irqentry_state_t state = irqentry_enter(regs); 966 967 local_irq_enable(); 968 if (!cpu_has_lsx) { 969 force_sig(SIGILL); 970 goto out; 971 } 972 973 die_if_kernel("do_lsx invoked from kernel context!", regs); 974 BUG_ON(is_lasx_enabled()); 975 976 preempt_disable(); 977 init_restore_lsx(); 978 preempt_enable(); 979 980 out: 981 local_irq_disable(); 982 irqentry_exit(regs, state); 983 } 984 985 asmlinkage void noinstr do_lasx(struct pt_regs *regs) 986 { 987 irqentry_state_t state = irqentry_enter(regs); 988 989 local_irq_enable(); 990 if (!cpu_has_lasx) { 991 force_sig(SIGILL); 992 goto out; 993 } 994 995 die_if_kernel("do_lasx invoked from kernel context!", regs); 996 997 preempt_disable(); 998 init_restore_lasx(); 999 preempt_enable(); 1000 1001 out: 1002 local_irq_disable(); 1003 irqentry_exit(regs, state); 1004 } 1005 1006 static void init_restore_lbt(void) 1007 { 1008 if (!thread_lbt_context_live()) { 1009 /* First time LBT context user */ 1010 init_lbt(); 1011 set_thread_flag(TIF_LBT_CTX_LIVE); 1012 } else { 1013 if (!is_lbt_owner()) 1014 own_lbt_inatomic(1); 1015 } 1016 1017 BUG_ON(!is_lbt_enabled()); 1018 } 1019 1020 asmlinkage void noinstr do_lbt(struct pt_regs *regs) 1021 { 1022 bool pie = regs_irqs_disabled(regs); 1023 irqentry_state_t state = irqentry_enter(regs); 1024 1025 /* 1026 * BTD (Binary Translation Disable exception) can be triggered 1027 * during FP save/restore if TM (Top Mode) is on, which may 1028 * cause irq_enable during 'switch_to'. To avoid this situation 1029 * (including the user using 'MOVGR2GCSR' to turn on TM, which 1030 * will not trigger the BTE), we need to check PRMD first. 1031 */ 1032 if (!pie) 1033 local_irq_enable(); 1034 1035 if (!cpu_has_lbt) { 1036 force_sig(SIGILL); 1037 goto out; 1038 } 1039 BUG_ON(is_lbt_enabled()); 1040 1041 preempt_disable(); 1042 init_restore_lbt(); 1043 preempt_enable(); 1044 1045 out: 1046 if (!pie) 1047 local_irq_disable(); 1048 1049 irqentry_exit(regs, state); 1050 } 1051 1052 asmlinkage void noinstr do_reserved(struct pt_regs *regs) 1053 { 1054 irqentry_state_t state = irqentry_enter(regs); 1055 1056 local_irq_enable(); 1057 /* 1058 * Game over - no way to handle this if it ever occurs. Most probably 1059 * caused by a fatal error after another hardware/software error. 1060 */ 1061 pr_err("Caught reserved exception %u on pid:%d [%s] - should not happen\n", 1062 read_csr_excode(), current->pid, current->comm); 1063 die_if_kernel("do_reserved exception", regs); 1064 force_sig(SIGUNUSED); 1065 1066 local_irq_disable(); 1067 1068 irqentry_exit(regs, state); 1069 } 1070 1071 asmlinkage void cache_parity_error(void) 1072 { 1073 /* For the moment, report the problem and hang. */ 1074 pr_err("Cache error exception:\n"); 1075 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); 1076 pr_err("csr_merrera == %016lx\n", csr_read64(LOONGARCH_CSR_MERRERA)); 1077 panic("Can't handle the cache error!"); 1078 } 1079 1080 asmlinkage void noinstr handle_loongarch_irq(struct pt_regs *regs) 1081 { 1082 struct pt_regs *old_regs; 1083 1084 irq_enter_rcu(); 1085 old_regs = set_irq_regs(regs); 1086 handle_arch_irq(regs); 1087 set_irq_regs(old_regs); 1088 irq_exit_rcu(); 1089 } 1090 1091 asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) 1092 { 1093 register int cpu; 1094 register unsigned long stack; 1095 irqentry_state_t state = irqentry_enter(regs); 1096 1097 cpu = smp_processor_id(); 1098 1099 if (on_irq_stack(cpu, sp)) 1100 handle_loongarch_irq(regs); 1101 else { 1102 stack = per_cpu(irq_stack, cpu) + IRQ_STACK_START; 1103 1104 /* Save task's sp on IRQ stack for unwinding */ 1105 *(unsigned long *)stack = sp; 1106 1107 __asm__ __volatile__( 1108 "move $s0, $sp \n" /* Preserve sp */ 1109 "move $sp, %[stk] \n" /* Switch stack */ 1110 "move $a0, %[regs] \n" 1111 "bl handle_loongarch_irq \n" 1112 "move $sp, $s0 \n" /* Restore sp */ 1113 : /* No outputs */ 1114 : [stk] "r" (stack), [regs] "r" (regs) 1115 : "$a0", "$a1", "$a2", "$a3", "$a4", "$a5", "$a6", "$a7", "$s0", 1116 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", "$t8", 1117 "memory"); 1118 } 1119 1120 irqentry_exit(regs, state); 1121 } 1122 1123 unsigned long eentry; 1124 unsigned long tlbrentry; 1125 1126 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K); 1127 1128 static void configure_exception_vector(void) 1129 { 1130 eentry = (unsigned long)exception_handlers; 1131 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; 1132 1133 csr_write64(eentry, LOONGARCH_CSR_EENTRY); 1134 csr_write64(eentry, LOONGARCH_CSR_MERRENTRY); 1135 csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY); 1136 } 1137 1138 void per_cpu_trap_init(int cpu) 1139 { 1140 unsigned int i; 1141 1142 setup_vint_size(VECSIZE); 1143 1144 configure_exception_vector(); 1145 1146 if (!cpu_data[cpu].asid_cache) 1147 cpu_data[cpu].asid_cache = asid_first_version(cpu); 1148 1149 mmgrab(&init_mm); 1150 current->active_mm = &init_mm; 1151 BUG_ON(current->mm); 1152 enter_lazy_tlb(&init_mm, current); 1153 1154 /* Initialise exception handlers */ 1155 if (cpu == 0) 1156 for (i = 0; i < 64; i++) 1157 set_handler(i * VECSIZE, handle_reserved, VECSIZE); 1158 1159 tlb_init(cpu); 1160 cpu_cache_init(); 1161 } 1162 1163 /* Install CPU exception handler */ 1164 void set_handler(unsigned long offset, void *addr, unsigned long size) 1165 { 1166 memcpy((void *)(eentry + offset), addr, size); 1167 local_flush_icache_range(eentry + offset, eentry + offset + size); 1168 } 1169 1170 static const char panic_null_cerr[] = 1171 "Trying to set NULL cache error exception handler\n"; 1172 1173 /* 1174 * Install uncached CPU exception handler. 1175 * This is suitable only for the cache error exception which is the only 1176 * exception handler that is being run uncached. 1177 */ 1178 void set_merr_handler(unsigned long offset, void *addr, unsigned long size) 1179 { 1180 unsigned long uncached_eentry = TO_UNCACHE(__pa(eentry)); 1181 1182 if (!addr) 1183 panic(panic_null_cerr); 1184 1185 memcpy((void *)(uncached_eentry + offset), addr, size); 1186 } 1187 1188 void __init trap_init(void) 1189 { 1190 long i; 1191 1192 /* Set interrupt vector handler */ 1193 for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++) 1194 set_handler(i * VECSIZE, handle_vint, VECSIZE); 1195 1196 /* Set exception vector handler */ 1197 for (i = EXCCODE_ADE; i <= EXCCODE_BTDIS; i++) 1198 set_handler(i * VECSIZE, exception_table[i], VECSIZE); 1199 1200 cache_error_setup(); 1201 1202 local_flush_icache_range(eentry, eentry + 0x400); 1203 } 1204