1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Common time service routines for LoongArch machines. 4 * 5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 6 */ 7 #include <linux/clockchips.h> 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/sched_clock.h> 14 #include <linux/spinlock.h> 15 16 #include <asm/cpu-features.h> 17 #include <asm/loongarch.h> 18 #include <asm/time.h> 19 20 u64 cpu_clock_freq; 21 EXPORT_SYMBOL(cpu_clock_freq); 22 u64 const_clock_freq; 23 EXPORT_SYMBOL(const_clock_freq); 24 25 static DEFINE_RAW_SPINLOCK(state_lock); 26 static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device); 27 28 static void constant_event_handler(struct clock_event_device *dev) 29 { 30 } 31 32 static irqreturn_t constant_timer_interrupt(int irq, void *data) 33 { 34 int cpu = smp_processor_id(); 35 struct clock_event_device *cd; 36 37 /* Clear Timer Interrupt */ 38 write_csr_tintclear(CSR_TINTCLR_TI); 39 cd = &per_cpu(constant_clockevent_device, cpu); 40 cd->event_handler(cd); 41 42 return IRQ_HANDLED; 43 } 44 45 static int constant_set_state_oneshot(struct clock_event_device *evt) 46 { 47 unsigned long timer_config; 48 49 raw_spin_lock(&state_lock); 50 51 timer_config = csr_read64(LOONGARCH_CSR_TCFG); 52 timer_config |= CSR_TCFG_EN; 53 timer_config &= ~CSR_TCFG_PERIOD; 54 csr_write64(timer_config, LOONGARCH_CSR_TCFG); 55 56 raw_spin_unlock(&state_lock); 57 58 return 0; 59 } 60 61 static int constant_set_state_periodic(struct clock_event_device *evt) 62 { 63 unsigned long period; 64 unsigned long timer_config; 65 66 raw_spin_lock(&state_lock); 67 68 period = const_clock_freq / HZ; 69 timer_config = period & CSR_TCFG_VAL; 70 timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN); 71 csr_write64(timer_config, LOONGARCH_CSR_TCFG); 72 73 raw_spin_unlock(&state_lock); 74 75 return 0; 76 } 77 78 static int constant_set_state_shutdown(struct clock_event_device *evt) 79 { 80 unsigned long timer_config; 81 82 raw_spin_lock(&state_lock); 83 84 timer_config = csr_read64(LOONGARCH_CSR_TCFG); 85 timer_config &= ~CSR_TCFG_EN; 86 csr_write64(timer_config, LOONGARCH_CSR_TCFG); 87 88 raw_spin_unlock(&state_lock); 89 90 return 0; 91 } 92 93 static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt) 94 { 95 unsigned long timer_config; 96 97 delta &= CSR_TCFG_VAL; 98 timer_config = delta | CSR_TCFG_EN; 99 csr_write64(timer_config, LOONGARCH_CSR_TCFG); 100 101 return 0; 102 } 103 104 static unsigned long __init get_loops_per_jiffy(void) 105 { 106 unsigned long lpj = (unsigned long)const_clock_freq; 107 108 do_div(lpj, HZ); 109 110 return lpj; 111 } 112 113 static long init_offset __nosavedata; 114 115 void save_counter(void) 116 { 117 init_offset = drdtime(); 118 } 119 120 void sync_counter(void) 121 { 122 /* Ensure counter begin at 0 */ 123 csr_write64(init_offset, LOONGARCH_CSR_CNTC); 124 } 125 126 int constant_clockevent_init(void) 127 { 128 unsigned int cpu = smp_processor_id(); 129 unsigned long min_delta = 0x600; 130 unsigned long max_delta = (1UL << 48) - 1; 131 struct clock_event_device *cd; 132 static int irq = 0, timer_irq_installed = 0; 133 134 if (!timer_irq_installed) { 135 irq = get_percpu_irq(INT_TI); 136 if (irq < 0) 137 pr_err("Failed to map irq %d (timer)\n", irq); 138 } 139 140 cd = &per_cpu(constant_clockevent_device, cpu); 141 142 cd->name = "Constant"; 143 cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_PERCPU; 144 145 cd->irq = irq; 146 cd->rating = 320; 147 cd->cpumask = cpumask_of(cpu); 148 cd->set_state_oneshot = constant_set_state_oneshot; 149 cd->set_state_oneshot_stopped = constant_set_state_shutdown; 150 cd->set_state_periodic = constant_set_state_periodic; 151 cd->set_state_shutdown = constant_set_state_shutdown; 152 cd->set_next_event = constant_timer_next_event; 153 cd->event_handler = constant_event_handler; 154 155 clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta); 156 157 if (timer_irq_installed) 158 return 0; 159 160 timer_irq_installed = 1; 161 162 sync_counter(); 163 164 if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU | IRQF_TIMER, "timer", NULL)) 165 pr_err("Failed to request irq %d (timer)\n", irq); 166 167 lpj_fine = get_loops_per_jiffy(); 168 pr_info("Constant clock event device register\n"); 169 170 return 0; 171 } 172 173 static u64 read_const_counter(struct clocksource *clk) 174 { 175 return drdtime(); 176 } 177 178 static noinstr u64 sched_clock_read(void) 179 { 180 return drdtime(); 181 } 182 183 static struct clocksource clocksource_const = { 184 .name = "Constant", 185 .rating = 400, 186 .read = read_const_counter, 187 .mask = CLOCKSOURCE_MASK(64), 188 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 189 .vdso_clock_mode = VDSO_CLOCKMODE_CPU, 190 }; 191 192 int __init constant_clocksource_init(void) 193 { 194 int res; 195 unsigned long freq = const_clock_freq; 196 197 res = clocksource_register_hz(&clocksource_const, freq); 198 199 sched_clock_register(sched_clock_read, 64, freq); 200 201 pr_info("Constant clock source device register\n"); 202 203 return res; 204 } 205 206 void __init time_init(void) 207 { 208 if (!cpu_has_cpucfg) 209 const_clock_freq = cpu_clock_freq; 210 else 211 const_clock_freq = calc_const_freq(); 212 213 init_offset = -(drdtime() - csr_read64(LOONGARCH_CSR_CNTC)); 214 215 constant_clockevent_init(); 216 constant_clocksource_init(); 217 } 218