1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5#include <linux/init.h> 6#include <linux/threads.h> 7 8#include <asm/addrspace.h> 9#include <asm/asm.h> 10#include <asm/asmmacro.h> 11#include <asm/bug.h> 12#include <asm/regdef.h> 13#include <asm/loongarch.h> 14#include <asm/stackframe.h> 15 16#ifdef CONFIG_EFI_STUB 17 18#include "efi-header.S" 19 20 __HEAD 21 22_head: 23 .word IMAGE_DOS_SIGNATURE /* "MZ", MS-DOS header */ 24 .org 0x8 25 .dword _kernel_entry /* Kernel entry point (physical address) */ 26 .dword _kernel_asize /* Kernel image effective size */ 27 .quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */ 28 .org 0x38 /* 0x20 ~ 0x37 reserved */ 29 .long LINUX_PE_MAGIC 30 .long pe_header - _head /* Offset to the PE header */ 31 32pe_header: 33 __EFI_PE_HEADER 34 35SYM_DATA(kernel_asize, .long _kernel_asize); 36SYM_DATA(kernel_fsize, .long _kernel_fsize); 37 38#endif 39 40 __REF 41 42 .align 12 43 44SYM_CODE_START(kernel_entry) # kernel entry point 45 46 SETUP_TWINS 47 SETUP_MODES t0 48 JUMP_VIRT_ADDR t0, t1 49 SETUP_DMWINS t0 50 51 la.pcrel t0, __bss_start # clear .bss 52 LONG_S zero, t0, 0 53 la.pcrel t1, __bss_stop - LONGSIZE 541: 55 PTR_ADDI t0, t0, LONGSIZE 56 LONG_S zero, t0, 0 57 bne t0, t1, 1b 58 59 la.pcrel t0, fw_arg0 60 PTR_S a0, t0, 0 # firmware arguments 61 la.pcrel t0, fw_arg1 62 PTR_S a1, t0, 0 63 la.pcrel t0, fw_arg2 64 PTR_S a2, t0, 0 65 66#ifdef CONFIG_PAGE_SIZE_4KB 67 LONG_LI t0, 0 68 LONG_LI t1, CSR_STFILL 69 csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1 70#endif 71 /* KSave3 used for percpu base, initialized as 0 */ 72 csrwr zero, PERCPU_BASE_KS 73 /* GPR21 used for percpu base (runtime), initialized as 0 */ 74 move u0, zero 75 76 la.pcrel tp, init_thread_union 77 /* Set the SP after an empty pt_regs. */ 78 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 79 PTR_ADD sp, sp, tp 80 set_saved_sp sp, t0, t1 81 82#ifdef CONFIG_RELOCATABLE 83 84 bl relocate_kernel 85 86#ifdef CONFIG_RANDOMIZE_BASE 87 /* Repoint the sp into the new kernel */ 88 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 89 PTR_ADD sp, sp, tp 90 set_saved_sp sp, t0, t1 91 92 /* Jump to the new kernel: new_pc = current_pc + random_offset */ 93 pcaddi t0, 0 94 PTR_ADD t0, t0, a0 95 jirl zero, t0, 0xc 96#endif /* CONFIG_RANDOMIZE_BASE */ 97 98#endif /* CONFIG_RELOCATABLE */ 99 100#ifdef CONFIG_KASAN 101 bl kasan_early_init 102#endif 103 104 bl start_kernel 105 ASM_BUG() 106 107SYM_CODE_END(kernel_entry) 108 109#ifdef CONFIG_SMP 110 111/* 112 * SMP slave cpus entry point. Board specific code for bootstrap calls this 113 * function after setting up the stack and tp registers. 114 */ 115SYM_CODE_START(smpboot_entry) 116 117 SETUP_TWINS 118 SETUP_MODES t0 119 JUMP_VIRT_ADDR t0, t1 120 SETUP_DMWINS t0 121 122#ifdef CONFIG_PAGE_SIZE_4KB 123 LONG_LI t0, 0 124 LONG_LI t1, CSR_STFILL 125 csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1 126#endif 127 /* Enable PG */ 128 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 129 csrwr t0, LOONGARCH_CSR_CRMD 130 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 131 csrwr t0, LOONGARCH_CSR_PRMD 132 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 133 csrwr t0, LOONGARCH_CSR_EUEN 134 135 la.pcrel t0, cpuboot_data 136 ld.d sp, t0, CPU_BOOT_STACK 137 ld.d tp, t0, CPU_BOOT_TINFO 138 139 bl start_secondary 140 ASM_BUG() 141 142SYM_CODE_END(smpboot_entry) 143 144#endif /* CONFIG_SMP */ 145 146SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) 147