1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5#include <linux/init.h> 6#include <linux/threads.h> 7 8#include <asm/addrspace.h> 9#include <asm/asm.h> 10#include <asm/asmmacro.h> 11#include <asm/bug.h> 12#include <asm/regdef.h> 13#include <asm/loongarch.h> 14#include <asm/stackframe.h> 15 16#ifdef CONFIG_EFI_STUB 17 18#include "efi-header.S" 19 20 __HEAD 21 22_head: 23 .word MZ_MAGIC /* "MZ", MS-DOS header */ 24 .org 0x8 25 .dword _kernel_entry /* Kernel entry point (physical address) */ 26 .dword _kernel_asize /* Kernel image effective size */ 27 .quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */ 28 .org 0x38 /* 0x20 ~ 0x37 reserved */ 29 .long LINUX_PE_MAGIC 30 .long pe_header - _head /* Offset to the PE header */ 31 32pe_header: 33 __EFI_PE_HEADER 34 35SYM_DATA(kernel_asize, .long _kernel_asize); 36SYM_DATA(kernel_fsize, .long _kernel_fsize); 37 38#endif 39 40 __REF 41 42 .align 12 43 44SYM_CODE_START(kernel_entry) # kernel entry point 45 46 /* Config direct window and set PG */ 47 li.d t0, CSR_DMW0_INIT # UC, PLV0, 0x8000 xxxx xxxx xxxx 48 csrwr t0, LOONGARCH_CSR_DMWIN0 49 li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx 50 csrwr t0, LOONGARCH_CSR_DMWIN1 51 52 JUMP_VIRT_ADDR t0, t1 53 54 /* Enable PG */ 55 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 56 csrwr t0, LOONGARCH_CSR_CRMD 57 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 58 csrwr t0, LOONGARCH_CSR_PRMD 59 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 60 csrwr t0, LOONGARCH_CSR_EUEN 61 62 la.pcrel t0, __bss_start # clear .bss 63 st.d zero, t0, 0 64 la.pcrel t1, __bss_stop - LONGSIZE 651: 66 addi.d t0, t0, LONGSIZE 67 st.d zero, t0, 0 68 bne t0, t1, 1b 69 70 la.pcrel t0, fw_arg0 71 st.d a0, t0, 0 # firmware arguments 72 la.pcrel t0, fw_arg1 73 st.d a1, t0, 0 74 la.pcrel t0, fw_arg2 75 st.d a2, t0, 0 76 77#ifdef CONFIG_PAGE_SIZE_4KB 78 li.d t0, 0 79 li.d t1, CSR_STFILL 80 csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1 81#endif 82 /* KSave3 used for percpu base, initialized as 0 */ 83 csrwr zero, PERCPU_BASE_KS 84 /* GPR21 used for percpu base (runtime), initialized as 0 */ 85 move u0, zero 86 87 la.pcrel tp, init_thread_union 88 /* Set the SP after an empty pt_regs. */ 89 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 90 PTR_ADD sp, sp, tp 91 set_saved_sp sp, t0, t1 92 93#ifdef CONFIG_RELOCATABLE 94 95 bl relocate_kernel 96 97#ifdef CONFIG_RANDOMIZE_BASE 98 /* Repoint the sp into the new kernel */ 99 PTR_LI sp, (_THREAD_SIZE - PT_SIZE) 100 PTR_ADD sp, sp, tp 101 set_saved_sp sp, t0, t1 102 103 /* Jump to the new kernel: new_pc = current_pc + random_offset */ 104 pcaddi t0, 0 105 add.d t0, t0, a0 106 jirl zero, t0, 0xc 107#endif /* CONFIG_RANDOMIZE_BASE */ 108 109#endif /* CONFIG_RELOCATABLE */ 110 111#ifdef CONFIG_KASAN 112 bl kasan_early_init 113#endif 114 115 bl start_kernel 116 ASM_BUG() 117 118SYM_CODE_END(kernel_entry) 119 120#ifdef CONFIG_SMP 121 122/* 123 * SMP slave cpus entry point. Board specific code for bootstrap calls this 124 * function after setting up the stack and tp registers. 125 */ 126SYM_CODE_START(smpboot_entry) 127 li.d t0, CSR_DMW0_INIT # UC, PLV0 128 csrwr t0, LOONGARCH_CSR_DMWIN0 129 li.d t0, CSR_DMW1_INIT # CA, PLV0 130 csrwr t0, LOONGARCH_CSR_DMWIN1 131 132 JUMP_VIRT_ADDR t0, t1 133 134#ifdef CONFIG_PAGE_SIZE_4KB 135 li.d t0, 0 136 li.d t1, CSR_STFILL 137 csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1 138#endif 139 /* Enable PG */ 140 li.w t0, 0xb0 # PLV=0, IE=0, PG=1 141 csrwr t0, LOONGARCH_CSR_CRMD 142 li.w t0, 0x04 # PLV=0, PIE=1, PWE=0 143 csrwr t0, LOONGARCH_CSR_PRMD 144 li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0 145 csrwr t0, LOONGARCH_CSR_EUEN 146 147 la.pcrel t0, cpuboot_data 148 ld.d sp, t0, CPU_BOOT_STACK 149 ld.d tp, t0, CPU_BOOT_TINFO 150 151 bl start_secondary 152 ASM_BUG() 153 154SYM_CODE_END(smpboot_entry) 155 156#endif /* CONFIG_SMP */ 157 158SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE) 159