1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Processor capabilities determination functions. 4 * 5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 6 */ 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <linux/ptrace.h> 10 #include <linux/smp.h> 11 #include <linux/stddef.h> 12 #include <linux/export.h> 13 #include <linux/printk.h> 14 #include <linux/uaccess.h> 15 16 #include <asm/cpu-features.h> 17 #include <asm/elf.h> 18 #include <asm/fpu.h> 19 #include <asm/loongarch.h> 20 #include <asm/pgtable-bits.h> 21 #include <asm/setup.h> 22 23 /* Hardware capabilities */ 24 unsigned int elf_hwcap __read_mostly; 25 EXPORT_SYMBOL_GPL(elf_hwcap); 26 27 /* 28 * Determine the FCSR mask for FPU hardware. 29 */ 30 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c) 31 { 32 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 33 34 fcsr = c->fpu_csr0; 35 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 36 37 sr = read_csr_euen(); 38 enable_fpu(); 39 40 fcsr0 = fcsr & mask; 41 write_fcsr(LOONGARCH_FCSR0, fcsr0); 42 fcsr0 = read_fcsr(LOONGARCH_FCSR0); 43 44 fcsr1 = fcsr | ~mask; 45 write_fcsr(LOONGARCH_FCSR0, fcsr1); 46 fcsr1 = read_fcsr(LOONGARCH_FCSR0); 47 48 write_fcsr(LOONGARCH_FCSR0, fcsr); 49 50 write_csr_euen(sr); 51 52 c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask; 53 } 54 55 static inline void set_elf_platform(int cpu, const char *plat) 56 { 57 if (cpu == 0) 58 __elf_platform = plat; 59 } 60 61 /* MAP BASE */ 62 unsigned long vm_map_base; 63 EXPORT_SYMBOL(vm_map_base); 64 65 static void cpu_probe_addrbits(struct cpuinfo_loongarch *c) 66 { 67 #ifdef __NEED_ADDRBITS_PROBE 68 c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4; 69 c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12; 70 vm_map_base = 0UL - (1UL << c->vabits); 71 #endif 72 } 73 74 static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa) 75 { 76 switch (isa) { 77 case LOONGARCH_CPU_ISA_LA64: 78 c->isa_level |= LOONGARCH_CPU_ISA_LA64; 79 fallthrough; 80 case LOONGARCH_CPU_ISA_LA32S: 81 c->isa_level |= LOONGARCH_CPU_ISA_LA32S; 82 fallthrough; 83 case LOONGARCH_CPU_ISA_LA32R: 84 c->isa_level |= LOONGARCH_CPU_ISA_LA32R; 85 break; 86 } 87 } 88 89 static void cpu_probe_common(struct cpuinfo_loongarch *c) 90 { 91 unsigned int config; 92 unsigned long asid_mask; 93 94 c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | 95 LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; 96 97 elf_hwcap = HWCAP_LOONGARCH_CPUCFG; 98 99 config = read_cpucfg(LOONGARCH_CPUCFG1); 100 if (config & CPUCFG1_UAL) { 101 c->options |= LOONGARCH_CPU_UAL; 102 elf_hwcap |= HWCAP_LOONGARCH_UAL; 103 } 104 if (config & CPUCFG1_CRC32) { 105 c->options |= LOONGARCH_CPU_CRC32; 106 elf_hwcap |= HWCAP_LOONGARCH_CRC32; 107 } 108 109 config = read_cpucfg(LOONGARCH_CPUCFG2); 110 if (config & CPUCFG2_LAM) { 111 c->options |= LOONGARCH_CPU_LAM; 112 elf_hwcap |= HWCAP_LOONGARCH_LAM; 113 } 114 if (config & CPUCFG2_FP) { 115 c->options |= LOONGARCH_CPU_FPU; 116 elf_hwcap |= HWCAP_LOONGARCH_FPU; 117 } 118 #ifdef CONFIG_CPU_HAS_LSX 119 if (config & CPUCFG2_LSX) { 120 c->options |= LOONGARCH_CPU_LSX; 121 elf_hwcap |= HWCAP_LOONGARCH_LSX; 122 } 123 #endif 124 #ifdef CONFIG_CPU_HAS_LASX 125 if (config & CPUCFG2_LASX) { 126 c->options |= LOONGARCH_CPU_LASX; 127 elf_hwcap |= HWCAP_LOONGARCH_LASX; 128 } 129 #endif 130 if (config & CPUCFG2_COMPLEX) { 131 c->options |= LOONGARCH_CPU_COMPLEX; 132 elf_hwcap |= HWCAP_LOONGARCH_COMPLEX; 133 } 134 if (config & CPUCFG2_CRYPTO) { 135 c->options |= LOONGARCH_CPU_CRYPTO; 136 elf_hwcap |= HWCAP_LOONGARCH_CRYPTO; 137 } 138 if (config & CPUCFG2_PTW) { 139 c->options |= LOONGARCH_CPU_PTW; 140 elf_hwcap |= HWCAP_LOONGARCH_PTW; 141 } 142 if (config & CPUCFG2_LVZP) { 143 c->options |= LOONGARCH_CPU_LVZ; 144 elf_hwcap |= HWCAP_LOONGARCH_LVZ; 145 } 146 #ifdef CONFIG_CPU_HAS_LBT 147 if (config & CPUCFG2_X86BT) { 148 c->options |= LOONGARCH_CPU_LBT_X86; 149 elf_hwcap |= HWCAP_LOONGARCH_LBT_X86; 150 } 151 if (config & CPUCFG2_ARMBT) { 152 c->options |= LOONGARCH_CPU_LBT_ARM; 153 elf_hwcap |= HWCAP_LOONGARCH_LBT_ARM; 154 } 155 if (config & CPUCFG2_MIPSBT) { 156 c->options |= LOONGARCH_CPU_LBT_MIPS; 157 elf_hwcap |= HWCAP_LOONGARCH_LBT_MIPS; 158 } 159 #endif 160 161 config = read_cpucfg(LOONGARCH_CPUCFG6); 162 if (config & CPUCFG6_PMP) 163 c->options |= LOONGARCH_CPU_PMP; 164 165 config = iocsr_read32(LOONGARCH_IOCSR_FEATURES); 166 if (config & IOCSRF_CSRIPI) 167 c->options |= LOONGARCH_CPU_CSRIPI; 168 if (config & IOCSRF_EXTIOI) 169 c->options |= LOONGARCH_CPU_EXTIOI; 170 if (config & IOCSRF_FREQSCALE) 171 c->options |= LOONGARCH_CPU_SCALEFREQ; 172 if (config & IOCSRF_FLATMODE) 173 c->options |= LOONGARCH_CPU_FLATMODE; 174 if (config & IOCSRF_EIODECODE) 175 c->options |= LOONGARCH_CPU_EIODECODE; 176 if (config & IOCSRF_AVEC) 177 c->options |= LOONGARCH_CPU_AVECINT; 178 if (config & IOCSRF_VM) 179 c->options |= LOONGARCH_CPU_HYPERVISOR; 180 181 config = csr_read32(LOONGARCH_CSR_ASID); 182 config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT; 183 asid_mask = GENMASK(config - 1, 0); 184 set_cpu_asid_mask(c, asid_mask); 185 186 config = read_csr_prcfg1(); 187 c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0); 188 c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK); 189 190 config = read_csr_prcfg3(); 191 switch (config & CSR_CONF3_TLBTYPE) { 192 case 0: 193 c->tlbsizemtlb = 0; 194 c->tlbsizestlbsets = 0; 195 c->tlbsizestlbways = 0; 196 c->tlbsize = 0; 197 break; 198 case 1: 199 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1; 200 c->tlbsizestlbsets = 0; 201 c->tlbsizestlbways = 0; 202 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; 203 break; 204 case 2: 205 c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1; 206 c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT); 207 c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1; 208 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; 209 break; 210 default: 211 pr_warn("Warning: unknown TLB type\n"); 212 } 213 } 214 215 #define MAX_NAME_LEN 32 216 #define VENDOR_OFFSET 0 217 #define CPUNAME_OFFSET 9 218 219 static char cpu_full_name[MAX_NAME_LEN] = " - "; 220 221 static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu) 222 { 223 uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]); 224 uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]); 225 226 if (!__cpu_full_name[cpu]) 227 __cpu_full_name[cpu] = cpu_full_name; 228 229 *vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR); 230 *cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME); 231 232 switch (c->processor_id & PRID_SERIES_MASK) { 233 case PRID_SERIES_LA132: 234 c->cputype = CPU_LOONGSON32; 235 set_isa(c, LOONGARCH_CPU_ISA_LA32S); 236 __cpu_family[cpu] = "Loongson-32bit"; 237 pr_info("32-bit Loongson Processor probed (LA132 Core)\n"); 238 break; 239 case PRID_SERIES_LA264: 240 c->cputype = CPU_LOONGSON64; 241 set_isa(c, LOONGARCH_CPU_ISA_LA64); 242 __cpu_family[cpu] = "Loongson-64bit"; 243 pr_info("64-bit Loongson Processor probed (LA264 Core)\n"); 244 break; 245 case PRID_SERIES_LA364: 246 c->cputype = CPU_LOONGSON64; 247 set_isa(c, LOONGARCH_CPU_ISA_LA64); 248 __cpu_family[cpu] = "Loongson-64bit"; 249 pr_info("64-bit Loongson Processor probed (LA364 Core)\n"); 250 break; 251 case PRID_SERIES_LA464: 252 c->cputype = CPU_LOONGSON64; 253 set_isa(c, LOONGARCH_CPU_ISA_LA64); 254 __cpu_family[cpu] = "Loongson-64bit"; 255 pr_info("64-bit Loongson Processor probed (LA464 Core)\n"); 256 break; 257 case PRID_SERIES_LA664: 258 c->cputype = CPU_LOONGSON64; 259 set_isa(c, LOONGARCH_CPU_ISA_LA64); 260 __cpu_family[cpu] = "Loongson-64bit"; 261 pr_info("64-bit Loongson Processor probed (LA664 Core)\n"); 262 break; 263 default: /* Default to 64 bit */ 264 c->cputype = CPU_LOONGSON64; 265 set_isa(c, LOONGARCH_CPU_ISA_LA64); 266 __cpu_family[cpu] = "Loongson-64bit"; 267 pr_info("64-bit Loongson Processor probed (Unknown Core)\n"); 268 } 269 } 270 271 #ifdef CONFIG_64BIT 272 /* For use by uaccess.h */ 273 u64 __ua_limit; 274 EXPORT_SYMBOL(__ua_limit); 275 #endif 276 277 const char *__cpu_family[NR_CPUS]; 278 const char *__cpu_full_name[NR_CPUS]; 279 const char *__elf_platform; 280 281 static void cpu_report(void) 282 { 283 struct cpuinfo_loongarch *c = ¤t_cpu_data; 284 285 pr_info("CPU%d revision is: %08x (%s)\n", 286 smp_processor_id(), c->processor_id, cpu_family_string()); 287 if (c->options & LOONGARCH_CPU_FPU) 288 pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers); 289 } 290 291 void cpu_probe(void) 292 { 293 unsigned int cpu = smp_processor_id(); 294 struct cpuinfo_loongarch *c = ¤t_cpu_data; 295 296 /* 297 * Set a default ELF platform, cpu probe may later 298 * overwrite it with a more precise value 299 */ 300 set_elf_platform(cpu, "loongarch"); 301 302 c->cputype = CPU_UNKNOWN; 303 c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0); 304 c->fpu_vers = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3; 305 306 c->fpu_csr0 = FPU_CSR_RN; 307 c->fpu_mask = FPU_CSR_RSVD; 308 309 cpu_probe_common(c); 310 311 per_cpu_trap_init(cpu); 312 313 switch (c->processor_id & PRID_COMP_MASK) { 314 case PRID_COMP_LOONGSON: 315 cpu_probe_loongson(c, cpu); 316 break; 317 } 318 319 BUG_ON(!__cpu_family[cpu]); 320 BUG_ON(c->cputype == CPU_UNKNOWN); 321 322 cpu_probe_addrbits(c); 323 324 #ifdef CONFIG_64BIT 325 if (cpu == 0) 326 __ua_limit = ~((1ull << cpu_vabits) - 1); 327 #endif 328 329 cpu_report(); 330 } 331