xref: /linux/arch/loongarch/include/asm/thread_info.h (revision bb3c90fe347a5321e7d176ed5b21367aa28be9ee)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * thread_info.h: LoongArch low-level thread information
4  *
5  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef _ASM_THREAD_INFO_H
9 #define _ASM_THREAD_INFO_H
10 
11 #ifdef __KERNEL__
12 
13 #ifndef __ASSEMBLER__
14 
15 #include <asm/processor.h>
16 
17 /*
18  * low level task data that entry.S needs immediate access to
19  * - this struct should fit entirely inside of one cache line
20  * - this struct shares the supervisor stack pages
21  * - if the contents of this structure are changed, the assembly constants
22  *   must also be changed
23  */
24 struct thread_info {
25 	unsigned long		flags;		/* low level flags */
26 	unsigned long		tp_value;	/* thread pointer */
27 	__u32			cpu;		/* current CPU */
28 	int			preempt_count;	/* 0 => preemptible, <0 => BUG */
29 	struct pt_regs		*regs;
30 	unsigned long		syscall;	/* syscall number */
31 	unsigned long		syscall_work;	/* SYSCALL_WORK_ flags */
32 };
33 
34 /*
35  * macros/functions for gaining access to the thread information structure
36  */
37 #define INIT_THREAD_INFO(tsk)			\
38 {						\
39 	.flags		= _TIF_FIXADE,		\
40 	.cpu		= 0,			\
41 	.preempt_count	= INIT_PREEMPT_COUNT,	\
42 }
43 
44 register unsigned long current_stack_pointer __asm__("$sp");
45 
46 #endif /* !__ASSEMBLER__ */
47 
48 /* thread information allocation */
49 #define THREAD_SIZE		SZ_16K
50 #define THREAD_MASK		(THREAD_SIZE - 1UL)
51 #define THREAD_SIZE_ORDER	ilog2(THREAD_SIZE / PAGE_SIZE)
52 /*
53  * thread information flags
54  * - these are process state flags that various assembly files may need to
55  *   access
56  * - pending work-to-be-done flags are in LSW
57  * - other flags in MSW
58  *
59  * Tell the generic TIF infrastructure which special bits loongarch supports
60  */
61 #define HAVE_TIF_NEED_RESCHED_LAZY
62 #define HAVE_TIF_RESTORE_SIGMASK
63 
64 #include <asm-generic/thread_info_tif.h>
65 
66 /* Architecture specific bits */
67 #define TIF_NOHZ		16	/* in adaptive nohz mode */
68 #define TIF_USEDFPU		17	/* FPU was used by this task this quantum (SMP) */
69 #define TIF_USEDSIMD		18	/* SIMD has been used this quantum */
70 #define TIF_FIXADE		19	/* Fix address errors in software */
71 #define TIF_LOGADE		20	/* Log address errors to syslog */
72 #define TIF_32BIT_REGS		21	/* 32-bit general purpose registers */
73 #define TIF_32BIT_ADDR		22	/* 32-bit address space */
74 #define TIF_LOAD_WATCH		23	/* If set, load watch registers */
75 #define TIF_SINGLESTEP		24	/* Single Step */
76 #define TIF_LSX_CTX_LIVE	25	/* LSX context must be preserved */
77 #define TIF_LASX_CTX_LIVE	26	/* LASX context must be preserved */
78 #define TIF_USEDLBT		27	/* LBT was used by this task this quantum (SMP) */
79 #define TIF_LBT_CTX_LIVE	28	/* LBT context must be preserved */
80 
81 #define _TIF_NOHZ		BIT(TIF_NOHZ)
82 #define _TIF_USEDFPU		BIT(TIF_USEDFPU)
83 #define _TIF_USEDSIMD		BIT(TIF_USEDSIMD)
84 #define _TIF_FIXADE		BIT(TIF_FIXADE)
85 #define _TIF_LOGADE		BIT(TIF_LOGADE)
86 #define _TIF_32BIT_REGS		BIT(TIF_32BIT_REGS)
87 #define _TIF_32BIT_ADDR		BIT(TIF_32BIT_ADDR)
88 #define _TIF_LOAD_WATCH		BIT(TIF_LOAD_WATCH)
89 #define _TIF_SINGLESTEP		BIT(TIF_SINGLESTEP)
90 #define _TIF_LSX_CTX_LIVE	BIT(TIF_LSX_CTX_LIVE)
91 #define _TIF_LASX_CTX_LIVE	BIT(TIF_LASX_CTX_LIVE)
92 #define _TIF_USEDLBT		BIT(TIF_USEDLBT)
93 #define _TIF_LBT_CTX_LIVE	BIT(TIF_LBT_CTX_LIVE)
94 
95 #endif /* __KERNEL__ */
96 #endif /* _ASM_THREAD_INFO_H */
97