1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Author: Huacai Chen <chenhuacai@loongson.cn> 4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef __ASM_LOONGSON_H 8 #define __ASM_LOONGSON_H 9 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/irq.h> 13 #include <linux/pci.h> 14 #include <asm/addrspace.h> 15 #include <asm/bootinfo.h> 16 17 extern const struct plat_smp_ops loongson3_smp_ops; 18 19 #define LOONGSON_REG(x) \ 20 (*(volatile u32 *)((char *)TO_UNCACHE(LOONGSON_REG_BASE) + (x))) 21 22 #define LOONGSON_LIO_BASE 0x18000000 23 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */ 24 #define LOONGSON_LIO_TOP (LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1) 25 26 #define LOONGSON_BOOT_BASE 0x1c000000 27 #define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */ 28 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) 29 30 #define LOONGSON_REG_BASE 0x1fe00000 31 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */ 32 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) 33 34 /* GPIO Regs - r/w */ 35 36 #define LOONGSON_GPIODATA LOONGSON_REG(0x11c) 37 #define LOONGSON_GPIOIE LOONGSON_REG(0x120) 38 #define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c) 39 40 #define MAX_PACKAGES 16 41 42 /* Chip Config register of each physical cpu package */ 43 extern u64 loongson_chipcfg[MAX_PACKAGES]; 44 #define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) 45 46 /* Chip Temperature register of each physical cpu package */ 47 extern u64 loongson_chiptemp[MAX_PACKAGES]; 48 #define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id])) 49 50 /* Freq Control register of each physical cpu package */ 51 extern u64 loongson_freqctrl[MAX_PACKAGES]; 52 #define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) 53 54 #define xconf_readl(addr) readl(addr) 55 #define xconf_readq(addr) readq(addr) 56 57 static inline void xconf_writel(u32 val, volatile void __iomem *addr) 58 { 59 asm volatile ( 60 " st.w %[v], %[hw], 0 \n" 61 " ld.b $r0, %[hw], 0 \n" 62 : 63 : [hw] "r" (addr), [v] "r" (val) 64 ); 65 } 66 67 static inline void xconf_writeq(u64 val64, volatile void __iomem *addr) 68 { 69 asm volatile ( 70 " st.d %[v], %[hw], 0 \n" 71 " ld.b $r0, %[hw], 0 \n" 72 : 73 : [hw] "r" (addr), [v] "r" (val64) 74 ); 75 } 76 77 /* ============== LS7A registers =============== */ 78 #define LS7A_PCH_REG_BASE 0x10000000UL 79 /* LPC regs */ 80 #define LS7A_LPC_REG_BASE (LS7A_PCH_REG_BASE + 0x00002000) 81 /* CHIPCFG regs */ 82 #define LS7A_CHIPCFG_REG_BASE (LS7A_PCH_REG_BASE + 0x00010000) 83 /* MISC reg base */ 84 #define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000) 85 /* ACPI regs */ 86 #define LS7A_ACPI_REG_BASE (LS7A_MISC_REG_BASE + 0x00050000) 87 /* RTC regs */ 88 #define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100) 89 90 #define LS7A_DMA_CFG (volatile void *)TO_UNCACHE(LS7A_CHIPCFG_REG_BASE + 0x041c) 91 #define LS7A_DMA_NODE_SHF 8 92 #define LS7A_DMA_NODE_MASK 0x1F00 93 94 #define LS7A_INT_MASK_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x020) 95 #define LS7A_INT_EDGE_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x060) 96 #define LS7A_INT_CLEAR_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x080) 97 #define LS7A_INT_HTMSI_EN_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x040) 98 #define LS7A_INT_ROUTE_ENTRY_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x100) 99 #define LS7A_INT_HTMSI_VEC_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200) 100 #define LS7A_INT_STATUS_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3a0) 101 #define LS7A_INT_POL_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3e0) 102 #define LS7A_LPC_INT_CTL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2000) 103 #define LS7A_LPC_INT_ENA (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2004) 104 #define LS7A_LPC_INT_STS (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2008) 105 #define LS7A_LPC_INT_CLR (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200c) 106 #define LS7A_LPC_INT_POL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2010) 107 108 #define LS7A_PMCON_SOC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x000) 109 #define LS7A_PMCON_RESUME_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x004) 110 #define LS7A_PMCON_RTC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x008) 111 #define LS7A_PM1_EVT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x00c) 112 #define LS7A_PM1_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x010) 113 #define LS7A_PM1_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x014) 114 #define LS7A_PM1_TMR_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x018) 115 #define LS7A_P_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x01c) 116 #define LS7A_GPE0_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x028) 117 #define LS7A_GPE0_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x02c) 118 #define LS7A_RST_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x030) 119 #define LS7A_WD_SET_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x034) 120 #define LS7A_WD_TIMER_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x038) 121 #define LS7A_THSENS_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x04c) 122 #define LS7A_GEN_RTC_1_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x050) 123 #define LS7A_GEN_RTC_2_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x054) 124 #define LS7A_DPM_CFG_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x400) 125 #define LS7A_DPM_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x404) 126 #define LS7A_DPM_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x408) 127 128 typedef enum { 129 ACPI_PCI_HOTPLUG_STATUS = 1 << 1, 130 ACPI_CPU_HOTPLUG_STATUS = 1 << 2, 131 ACPI_MEM_HOTPLUG_STATUS = 1 << 3, 132 ACPI_POWERBUTTON_STATUS = 1 << 8, 133 ACPI_RTC_WAKE_STATUS = 1 << 10, 134 ACPI_PCI_WAKE_STATUS = 1 << 14, 135 ACPI_ANY_WAKE_STATUS = 1 << 15, 136 } AcpiEventStatusBits; 137 138 #define HT1LO_OFFSET 0xe0000000000UL 139 140 /* PCI Configuration Space Base */ 141 #define MCFG_EXT_PCICFG_BASE 0xefe00000000UL 142 143 /* REG ACCESS*/ 144 #define ls7a_readb(addr) (*(volatile unsigned char *)TO_UNCACHE(addr)) 145 #define ls7a_readw(addr) (*(volatile unsigned short *)TO_UNCACHE(addr)) 146 #define ls7a_readl(addr) (*(volatile unsigned int *)TO_UNCACHE(addr)) 147 #define ls7a_readq(addr) (*(volatile unsigned long *)TO_UNCACHE(addr)) 148 #define ls7a_writeb(val, addr) *(volatile unsigned char *)TO_UNCACHE(addr) = (val) 149 #define ls7a_writew(val, addr) *(volatile unsigned short *)TO_UNCACHE(addr) = (val) 150 #define ls7a_writel(val, addr) *(volatile unsigned int *)TO_UNCACHE(addr) = (val) 151 #define ls7a_writeq(val, addr) *(volatile unsigned long *)TO_UNCACHE(addr) = (val) 152 153 #endif /* __ASM_LOONGSON_H */ 154