1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited 4 */ 5 6 #ifndef __ASM_LOONGARCH_KVM_VCPU_H__ 7 #define __ASM_LOONGARCH_KVM_VCPU_H__ 8 9 #include <linux/kvm_host.h> 10 #include <asm/loongarch.h> 11 12 /* Controlled by 0x5 guest estat */ 13 #define CPU_SIP0 BIT(INT_SWI0) 14 #define CPU_SIP1 BIT(INT_SWI1) 15 #define CPU_HWI0 BIT(INT_HWI0) 16 #define CPU_HWI1 BIT(INT_HWI1) 17 #define CPU_HWI2 BIT(INT_HWI2) 18 #define CPU_HWI3 BIT(INT_HWI3) 19 #define CPU_HWI4 BIT(INT_HWI4) 20 #define CPU_HWI5 BIT(INT_HWI5) 21 #define CPU_HWI6 BIT(INT_HWI6) 22 #define CPU_HWI7 BIT(INT_HWI7) 23 #define CPU_PMU BIT(INT_PCOV) 24 #define CPU_TIMER BIT(INT_TI) 25 #define CPU_IPI BIT(INT_IPI) 26 #define CPU_AVEC BIT(INT_AVEC) 27 #define KVM_ESTAT_INTI_MASK (CPU_SIP0 | CPU_SIP1 | CPU_PMU | CPU_TIMER \ 28 | CPU_IPI | CPU_AVEC) 29 #define KVM_ESTAT_EXTI_MASK (CPU_HWI0 | CPU_HWI1 | CPU_HWI2 | CPU_HWI3 \ 30 | CPU_HWI4 | CPU_HWI5 | CPU_HWI6 | CPU_HWI7) 31 32 /* Controlled by 0x52 guest exception VIP aligned to estat bit 5~12 */ 33 #define VIP_DELTA (INT_HWI0 - CSR_GINTC_VIP_SHIFT) 34 #define CPU_IP0 BIT(INT_HWI0 - VIP_DELTA) 35 #define CPU_IP1 BIT(INT_HWI1 - VIP_DELTA) 36 #define CPU_IP2 BIT(INT_HWI2 - VIP_DELTA) 37 #define CPU_IP3 BIT(INT_HWI3 - VIP_DELTA) 38 #define CPU_IP4 BIT(INT_HWI4 - VIP_DELTA) 39 #define CPU_IP5 BIT(INT_HWI5 - VIP_DELTA) 40 #define CPU_IP6 BIT(INT_HWI6 - VIP_DELTA) 41 #define CPU_IP7 BIT(INT_HWI7 - VIP_DELTA) 42 #define KVM_GINTC_IRQ_MASK (CPU_IP0 | CPU_IP1 | CPU_IP2 | CPU_IP3 \ 43 | CPU_IP4 | CPU_IP5 | CPU_IP6 | CPU_IP7) 44 45 #define MNSEC_PER_SEC (NSEC_PER_SEC >> 20) 46 47 /* KVM_IRQ_LINE irq field index values */ 48 #define KVM_LOONGSON_IRQ_TYPE_SHIFT 24 49 #define KVM_LOONGSON_IRQ_TYPE_MASK 0xff 50 #define KVM_LOONGSON_IRQ_VCPU_SHIFT 16 51 #define KVM_LOONGSON_IRQ_VCPU_MASK 0xff 52 #define KVM_LOONGSON_IRQ_NUM_SHIFT 0 53 #define KVM_LOONGSON_IRQ_NUM_MASK 0xffff 54 55 typedef union loongarch_instruction larch_inst; 56 typedef int (*exit_handle_fn)(struct kvm_vcpu *, int); 57 58 int kvm_emu_mmio_read(struct kvm_vcpu *vcpu, larch_inst inst); 59 int kvm_emu_mmio_write(struct kvm_vcpu *vcpu, larch_inst inst); 60 int kvm_complete_mmio_read(struct kvm_vcpu *vcpu, struct kvm_run *run); 61 int kvm_complete_iocsr_read(struct kvm_vcpu *vcpu, struct kvm_run *run); 62 int kvm_complete_user_service(struct kvm_vcpu *vcpu, struct kvm_run *run); 63 int kvm_emu_idle(struct kvm_vcpu *vcpu); 64 int kvm_pending_timer(struct kvm_vcpu *vcpu); 65 int kvm_handle_fault(struct kvm_vcpu *vcpu, int fault); 66 void kvm_deliver_intr(struct kvm_vcpu *vcpu); 67 void kvm_deliver_exception(struct kvm_vcpu *vcpu); 68 69 void kvm_own_fpu(struct kvm_vcpu *vcpu); 70 void kvm_lose_fpu(struct kvm_vcpu *vcpu); 71 void kvm_save_fpu(struct loongarch_fpu *fpu); 72 void kvm_restore_fpu(struct loongarch_fpu *fpu); 73 void kvm_restore_fcsr(struct loongarch_fpu *fpu); 74 75 #ifdef CONFIG_CPU_HAS_LSX 76 int kvm_own_lsx(struct kvm_vcpu *vcpu); 77 void kvm_save_lsx(struct loongarch_fpu *fpu); 78 void kvm_restore_lsx(struct loongarch_fpu *fpu); 79 #else 80 static inline int kvm_own_lsx(struct kvm_vcpu *vcpu) { return -EINVAL; } 81 static inline void kvm_save_lsx(struct loongarch_fpu *fpu) { } 82 static inline void kvm_restore_lsx(struct loongarch_fpu *fpu) { } 83 #endif 84 85 #ifdef CONFIG_CPU_HAS_LASX 86 int kvm_own_lasx(struct kvm_vcpu *vcpu); 87 void kvm_save_lasx(struct loongarch_fpu *fpu); 88 void kvm_restore_lasx(struct loongarch_fpu *fpu); 89 #else 90 static inline int kvm_own_lasx(struct kvm_vcpu *vcpu) { return -EINVAL; } 91 static inline void kvm_save_lasx(struct loongarch_fpu *fpu) { } 92 static inline void kvm_restore_lasx(struct loongarch_fpu *fpu) { } 93 #endif 94 95 #ifdef CONFIG_CPU_HAS_LBT 96 int kvm_own_lbt(struct kvm_vcpu *vcpu); 97 #else 98 static inline int kvm_own_lbt(struct kvm_vcpu *vcpu) { return -EINVAL; } 99 #endif 100 101 void kvm_init_timer(struct kvm_vcpu *vcpu, unsigned long hz); 102 void kvm_save_timer(struct kvm_vcpu *vcpu); 103 void kvm_restore_timer(struct kvm_vcpu *vcpu); 104 105 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq); 106 struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm, int cpuid); 107 108 /* 109 * Loongarch KVM guest interrupt handling 110 */ 111 static inline void kvm_queue_irq(struct kvm_vcpu *vcpu, unsigned int irq) 112 { 113 set_bit(irq, &vcpu->arch.irq_pending); 114 clear_bit(irq, &vcpu->arch.irq_clear); 115 } 116 117 static inline void kvm_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int irq) 118 { 119 clear_bit(irq, &vcpu->arch.irq_pending); 120 set_bit(irq, &vcpu->arch.irq_clear); 121 } 122 123 static inline int kvm_queue_exception(struct kvm_vcpu *vcpu, 124 unsigned int code, unsigned int subcode) 125 { 126 /* only one exception can be injected */ 127 if (!vcpu->arch.exception_pending) { 128 set_bit(code, &vcpu->arch.exception_pending); 129 vcpu->arch.esubcode = subcode; 130 return 0; 131 } else 132 return -1; 133 } 134 135 static inline unsigned long kvm_read_reg(struct kvm_vcpu *vcpu, int num) 136 { 137 return vcpu->arch.gprs[num]; 138 } 139 140 static inline void kvm_write_reg(struct kvm_vcpu *vcpu, int num, unsigned long val) 141 { 142 vcpu->arch.gprs[num] = val; 143 } 144 145 static inline bool kvm_pvtime_supported(void) 146 { 147 return !!sched_info_on(); 148 } 149 150 static inline bool kvm_guest_has_pv_feature(struct kvm_vcpu *vcpu, unsigned int feature) 151 { 152 return vcpu->kvm->arch.pv_features & BIT(feature); 153 } 154 155 #endif /* __ASM_LOONGARCH_KVM_VCPU_H__ */ 156