1e785dfacSXianglai Li /* SPDX-License-Identifier: GPL-2.0 */ 2e785dfacSXianglai Li /* 3e785dfacSXianglai Li * Copyright (C) 2024 Loongson Technology Corporation Limited 4e785dfacSXianglai Li */ 5e785dfacSXianglai Li 6e785dfacSXianglai Li #ifndef __ASM_KVM_PCH_PIC_H 7e785dfacSXianglai Li #define __ASM_KVM_PCH_PIC_H 8e785dfacSXianglai Li 9e785dfacSXianglai Li #include <kvm/iodev.h> 10e785dfacSXianglai Li 11*f5f31efaSXianglai Li #define PCH_PIC_SIZE 0x3e8 12*f5f31efaSXianglai Li 13*f5f31efaSXianglai Li #define PCH_PIC_INT_ID_START 0x0 14*f5f31efaSXianglai Li #define PCH_PIC_INT_ID_END 0x7 15*f5f31efaSXianglai Li #define PCH_PIC_MASK_START 0x20 16*f5f31efaSXianglai Li #define PCH_PIC_MASK_END 0x27 17*f5f31efaSXianglai Li #define PCH_PIC_HTMSI_EN_START 0x40 18*f5f31efaSXianglai Li #define PCH_PIC_HTMSI_EN_END 0x47 19*f5f31efaSXianglai Li #define PCH_PIC_EDGE_START 0x60 20*f5f31efaSXianglai Li #define PCH_PIC_EDGE_END 0x67 21*f5f31efaSXianglai Li #define PCH_PIC_CLEAR_START 0x80 22*f5f31efaSXianglai Li #define PCH_PIC_CLEAR_END 0x87 23*f5f31efaSXianglai Li #define PCH_PIC_AUTO_CTRL0_START 0xc0 24*f5f31efaSXianglai Li #define PCH_PIC_AUTO_CTRL0_END 0xc7 25*f5f31efaSXianglai Li #define PCH_PIC_AUTO_CTRL1_START 0xe0 26*f5f31efaSXianglai Li #define PCH_PIC_AUTO_CTRL1_END 0xe7 27*f5f31efaSXianglai Li #define PCH_PIC_ROUTE_ENTRY_START 0x100 28*f5f31efaSXianglai Li #define PCH_PIC_ROUTE_ENTRY_END 0x13f 29*f5f31efaSXianglai Li #define PCH_PIC_HTMSI_VEC_START 0x200 30*f5f31efaSXianglai Li #define PCH_PIC_HTMSI_VEC_END 0x23f 31*f5f31efaSXianglai Li #define PCH_PIC_INT_IRR_START 0x380 32*f5f31efaSXianglai Li #define PCH_PIC_INT_IRR_END 0x38f 33*f5f31efaSXianglai Li #define PCH_PIC_INT_ISR_START 0x3a0 34*f5f31efaSXianglai Li #define PCH_PIC_INT_ISR_END 0x3af 35*f5f31efaSXianglai Li #define PCH_PIC_POLARITY_START 0x3e0 36*f5f31efaSXianglai Li #define PCH_PIC_POLARITY_END 0x3e7 37*f5f31efaSXianglai Li #define PCH_PIC_INT_ID_VAL 0x7000000UL 38*f5f31efaSXianglai Li #define PCH_PIC_INT_ID_VER 0x1UL 39*f5f31efaSXianglai Li 40e785dfacSXianglai Li struct loongarch_pch_pic { 41e785dfacSXianglai Li spinlock_t lock; 42e785dfacSXianglai Li struct kvm *kvm; 43e785dfacSXianglai Li struct kvm_io_device device; 44e785dfacSXianglai Li uint64_t mask; /* 1:disable irq, 0:enable irq */ 45e785dfacSXianglai Li uint64_t htmsi_en; /* 1:msi */ 46e785dfacSXianglai Li uint64_t edge; /* 1:edge triggered, 0:level triggered */ 47e785dfacSXianglai Li uint64_t auto_ctrl0; /* only use default value 00b */ 48e785dfacSXianglai Li uint64_t auto_ctrl1; /* only use default value 00b */ 49e785dfacSXianglai Li uint64_t last_intirr; /* edge detection */ 50e785dfacSXianglai Li uint64_t irr; /* interrupt request register */ 51e785dfacSXianglai Li uint64_t isr; /* interrupt service register */ 52e785dfacSXianglai Li uint64_t polarity; /* 0: high level trigger, 1: low level trigger */ 53e785dfacSXianglai Li uint8_t route_entry[64]; /* default value 0, route to int0: eiointc */ 54e785dfacSXianglai Li uint8_t htmsi_vector[64]; /* irq route table for routing to eiointc */ 55e785dfacSXianglai Li uint64_t pch_pic_base; 56e785dfacSXianglai Li }; 57e785dfacSXianglai Li 58e785dfacSXianglai Li int kvm_loongarch_register_pch_pic_device(void); 59*f5f31efaSXianglai Li void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level); 60*f5f31efaSXianglai Li void pch_msi_set_irq(struct kvm *kvm, int irq, int level); 61e785dfacSXianglai Li 62e785dfacSXianglai Li #endif /* __ASM_KVM_PCH_PIC_H */ 63