1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_INST_H 6 #define _ASM_INST_H 7 8 #include <linux/bitops.h> 9 #include <linux/types.h> 10 #include <asm/asm.h> 11 #include <asm/ptrace.h> 12 13 #define INSN_NOP 0x03400000 14 #define INSN_BREAK 0x002a0000 15 16 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000 17 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000 18 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000 19 #define ADDR_IMMMASK_ORI 0x0000000000000FFF 20 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000 21 22 #define ADDR_IMMSHIFT_LU52ID 52 23 #define ADDR_IMMSBIDX_LU52ID 11 24 #define ADDR_IMMSHIFT_LU32ID 32 25 #define ADDR_IMMSBIDX_LU32ID 19 26 #define ADDR_IMMSHIFT_LU12IW 12 27 #define ADDR_IMMSBIDX_LU12IW 19 28 #define ADDR_IMMSHIFT_ORI 0 29 #define ADDR_IMMSBIDX_ORI 63 30 #define ADDR_IMMSHIFT_ADDU16ID 16 31 #define ADDR_IMMSBIDX_ADDU16ID 15 32 33 #define ADDR_IMM(addr, INSN) \ 34 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN)) 35 36 enum reg0i15_op { 37 break_op = 0x54, 38 }; 39 40 enum reg0i26_op { 41 b_op = 0x14, 42 bl_op = 0x15, 43 }; 44 45 enum reg1i20_op { 46 lu12iw_op = 0x0a, 47 lu32id_op = 0x0b, 48 pcaddi_op = 0x0c, 49 pcalau12i_op = 0x0d, 50 pcaddu12i_op = 0x0e, 51 pcaddu18i_op = 0x0f, 52 }; 53 54 enum reg1i21_op { 55 beqz_op = 0x10, 56 bnez_op = 0x11, 57 bceqz_op = 0x12, /* bits[9:8] = 0x00 */ 58 bcnez_op = 0x12, /* bits[9:8] = 0x01 */ 59 }; 60 61 enum reg2_op { 62 revb2h_op = 0x0c, 63 revb4h_op = 0x0d, 64 revb2w_op = 0x0e, 65 revbd_op = 0x0f, 66 revh2w_op = 0x10, 67 revhd_op = 0x11, 68 }; 69 70 enum reg2i5_op { 71 slliw_op = 0x81, 72 srliw_op = 0x89, 73 sraiw_op = 0x91, 74 }; 75 76 enum reg2i6_op { 77 sllid_op = 0x41, 78 srlid_op = 0x45, 79 sraid_op = 0x49, 80 }; 81 82 enum reg2i12_op { 83 addiw_op = 0x0a, 84 addid_op = 0x0b, 85 lu52id_op = 0x0c, 86 andi_op = 0x0d, 87 ori_op = 0x0e, 88 xori_op = 0x0f, 89 ldb_op = 0xa0, 90 ldh_op = 0xa1, 91 ldw_op = 0xa2, 92 ldd_op = 0xa3, 93 stb_op = 0xa4, 94 sth_op = 0xa5, 95 stw_op = 0xa6, 96 std_op = 0xa7, 97 ldbu_op = 0xa8, 98 ldhu_op = 0xa9, 99 ldwu_op = 0xaa, 100 flds_op = 0xac, 101 fsts_op = 0xad, 102 fldd_op = 0xae, 103 fstd_op = 0xaf, 104 }; 105 106 enum reg2i14_op { 107 llw_op = 0x20, 108 scw_op = 0x21, 109 lld_op = 0x22, 110 scd_op = 0x23, 111 ldptrw_op = 0x24, 112 stptrw_op = 0x25, 113 ldptrd_op = 0x26, 114 stptrd_op = 0x27, 115 }; 116 117 enum reg2i16_op { 118 jirl_op = 0x13, 119 beq_op = 0x16, 120 bne_op = 0x17, 121 blt_op = 0x18, 122 bge_op = 0x19, 123 bltu_op = 0x1a, 124 bgeu_op = 0x1b, 125 }; 126 127 enum reg2bstrd_op { 128 bstrinsd_op = 0x2, 129 bstrpickd_op = 0x3, 130 }; 131 132 enum reg3_op { 133 asrtle_op = 0x02, 134 asrtgt_op = 0x03, 135 addw_op = 0x20, 136 addd_op = 0x21, 137 subw_op = 0x22, 138 subd_op = 0x23, 139 nor_op = 0x28, 140 and_op = 0x29, 141 or_op = 0x2a, 142 xor_op = 0x2b, 143 orn_op = 0x2c, 144 andn_op = 0x2d, 145 sllw_op = 0x2e, 146 srlw_op = 0x2f, 147 sraw_op = 0x30, 148 slld_op = 0x31, 149 srld_op = 0x32, 150 srad_op = 0x33, 151 mulw_op = 0x38, 152 mulhw_op = 0x39, 153 mulhwu_op = 0x3a, 154 muld_op = 0x3b, 155 mulhd_op = 0x3c, 156 mulhdu_op = 0x3d, 157 divw_op = 0x40, 158 modw_op = 0x41, 159 divwu_op = 0x42, 160 modwu_op = 0x43, 161 divd_op = 0x44, 162 modd_op = 0x45, 163 divdu_op = 0x46, 164 moddu_op = 0x47, 165 ldxb_op = 0x7000, 166 ldxh_op = 0x7008, 167 ldxw_op = 0x7010, 168 ldxd_op = 0x7018, 169 stxb_op = 0x7020, 170 stxh_op = 0x7028, 171 stxw_op = 0x7030, 172 stxd_op = 0x7038, 173 ldxbu_op = 0x7040, 174 ldxhu_op = 0x7048, 175 ldxwu_op = 0x7050, 176 fldxs_op = 0x7060, 177 fldxd_op = 0x7068, 178 fstxs_op = 0x7070, 179 fstxd_op = 0x7078, 180 amswapw_op = 0x70c0, 181 amswapd_op = 0x70c1, 182 amaddw_op = 0x70c2, 183 amaddd_op = 0x70c3, 184 amandw_op = 0x70c4, 185 amandd_op = 0x70c5, 186 amorw_op = 0x70c6, 187 amord_op = 0x70c7, 188 amxorw_op = 0x70c8, 189 amxord_op = 0x70c9, 190 fldgts_op = 0x70e8, 191 fldgtd_op = 0x70e9, 192 fldles_op = 0x70ea, 193 fldled_op = 0x70eb, 194 fstgts_op = 0x70ec, 195 fstgtd_op = 0x70ed, 196 fstles_op = 0x70ee, 197 fstled_op = 0x70ef, 198 ldgtb_op = 0x70f0, 199 ldgth_op = 0x70f1, 200 ldgtw_op = 0x70f2, 201 ldgtd_op = 0x70f3, 202 ldleb_op = 0x70f4, 203 ldleh_op = 0x70f5, 204 ldlew_op = 0x70f6, 205 ldled_op = 0x70f7, 206 stgtb_op = 0x70f8, 207 stgth_op = 0x70f9, 208 stgtw_op = 0x70fa, 209 stgtd_op = 0x70fb, 210 stleb_op = 0x70fc, 211 stleh_op = 0x70fd, 212 stlew_op = 0x70fe, 213 stled_op = 0x70ff, 214 }; 215 216 enum reg3sa2_op { 217 alslw_op = 0x02, 218 alslwu_op = 0x03, 219 alsld_op = 0x16, 220 }; 221 222 struct reg0i15_format { 223 unsigned int immediate : 15; 224 unsigned int opcode : 17; 225 }; 226 227 struct reg0i26_format { 228 unsigned int immediate_h : 10; 229 unsigned int immediate_l : 16; 230 unsigned int opcode : 6; 231 }; 232 233 struct reg1i20_format { 234 unsigned int rd : 5; 235 unsigned int immediate : 20; 236 unsigned int opcode : 7; 237 }; 238 239 struct reg1i21_format { 240 unsigned int immediate_h : 5; 241 unsigned int rj : 5; 242 unsigned int immediate_l : 16; 243 unsigned int opcode : 6; 244 }; 245 246 struct reg2_format { 247 unsigned int rd : 5; 248 unsigned int rj : 5; 249 unsigned int opcode : 22; 250 }; 251 252 struct reg2i5_format { 253 unsigned int rd : 5; 254 unsigned int rj : 5; 255 unsigned int immediate : 5; 256 unsigned int opcode : 17; 257 }; 258 259 struct reg2i6_format { 260 unsigned int rd : 5; 261 unsigned int rj : 5; 262 unsigned int immediate : 6; 263 unsigned int opcode : 16; 264 }; 265 266 struct reg2i12_format { 267 unsigned int rd : 5; 268 unsigned int rj : 5; 269 unsigned int immediate : 12; 270 unsigned int opcode : 10; 271 }; 272 273 struct reg2i14_format { 274 unsigned int rd : 5; 275 unsigned int rj : 5; 276 unsigned int immediate : 14; 277 unsigned int opcode : 8; 278 }; 279 280 struct reg2i16_format { 281 unsigned int rd : 5; 282 unsigned int rj : 5; 283 unsigned int immediate : 16; 284 unsigned int opcode : 6; 285 }; 286 287 struct reg2bstrd_format { 288 unsigned int rd : 5; 289 unsigned int rj : 5; 290 unsigned int lsbd : 6; 291 unsigned int msbd : 6; 292 unsigned int opcode : 10; 293 }; 294 295 struct reg3_format { 296 unsigned int rd : 5; 297 unsigned int rj : 5; 298 unsigned int rk : 5; 299 unsigned int opcode : 17; 300 }; 301 302 struct reg3sa2_format { 303 unsigned int rd : 5; 304 unsigned int rj : 5; 305 unsigned int rk : 5; 306 unsigned int immediate : 2; 307 unsigned int opcode : 15; 308 }; 309 310 union loongarch_instruction { 311 unsigned int word; 312 struct reg0i15_format reg0i15_format; 313 struct reg0i26_format reg0i26_format; 314 struct reg1i20_format reg1i20_format; 315 struct reg1i21_format reg1i21_format; 316 struct reg2_format reg2_format; 317 struct reg2i5_format reg2i5_format; 318 struct reg2i6_format reg2i6_format; 319 struct reg2i12_format reg2i12_format; 320 struct reg2i14_format reg2i14_format; 321 struct reg2i16_format reg2i16_format; 322 struct reg2bstrd_format reg2bstrd_format; 323 struct reg3_format reg3_format; 324 struct reg3sa2_format reg3sa2_format; 325 }; 326 327 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction) 328 329 enum loongarch_gpr { 330 LOONGARCH_GPR_ZERO = 0, 331 LOONGARCH_GPR_RA = 1, 332 LOONGARCH_GPR_TP = 2, 333 LOONGARCH_GPR_SP = 3, 334 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */ 335 LOONGARCH_GPR_A1, /* Reused as V1 for return value */ 336 LOONGARCH_GPR_A2, 337 LOONGARCH_GPR_A3, 338 LOONGARCH_GPR_A4, 339 LOONGARCH_GPR_A5, 340 LOONGARCH_GPR_A6, 341 LOONGARCH_GPR_A7, 342 LOONGARCH_GPR_T0 = 12, 343 LOONGARCH_GPR_T1, 344 LOONGARCH_GPR_T2, 345 LOONGARCH_GPR_T3, 346 LOONGARCH_GPR_T4, 347 LOONGARCH_GPR_T5, 348 LOONGARCH_GPR_T6, 349 LOONGARCH_GPR_T7, 350 LOONGARCH_GPR_T8, 351 LOONGARCH_GPR_FP = 22, 352 LOONGARCH_GPR_S0 = 23, 353 LOONGARCH_GPR_S1, 354 LOONGARCH_GPR_S2, 355 LOONGARCH_GPR_S3, 356 LOONGARCH_GPR_S4, 357 LOONGARCH_GPR_S5, 358 LOONGARCH_GPR_S6, 359 LOONGARCH_GPR_S7, 360 LOONGARCH_GPR_S8, 361 LOONGARCH_GPR_MAX 362 }; 363 364 #define is_imm12_negative(val) is_imm_negative(val, 12) 365 366 static inline bool is_imm_negative(unsigned long val, unsigned int bit) 367 { 368 return val & (1UL << (bit - 1)); 369 } 370 371 static inline bool is_break_ins(union loongarch_instruction *ip) 372 { 373 return ip->reg0i15_format.opcode == break_op; 374 } 375 376 static inline bool is_pc_ins(union loongarch_instruction *ip) 377 { 378 return ip->reg1i20_format.opcode >= pcaddi_op && 379 ip->reg1i20_format.opcode <= pcaddu18i_op; 380 } 381 382 static inline bool is_branch_ins(union loongarch_instruction *ip) 383 { 384 return ip->reg1i21_format.opcode >= beqz_op && 385 ip->reg1i21_format.opcode <= bgeu_op; 386 } 387 388 static inline bool is_ra_save_ins(union loongarch_instruction *ip) 389 { 390 /* st.d $ra, $sp, offset */ 391 return ip->reg2i12_format.opcode == std_op && 392 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 393 ip->reg2i12_format.rd == LOONGARCH_GPR_RA && 394 !is_imm12_negative(ip->reg2i12_format.immediate); 395 } 396 397 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip) 398 { 399 /* addi.d $sp, $sp, -imm */ 400 return ip->reg2i12_format.opcode == addid_op && 401 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 402 ip->reg2i12_format.rd == LOONGARCH_GPR_SP && 403 is_imm12_negative(ip->reg2i12_format.immediate); 404 } 405 406 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs) 407 { 408 switch (ip->reg0i26_format.opcode) { 409 case b_op: 410 case bl_op: 411 if (ip->reg0i26_format.immediate_l == 0 412 && ip->reg0i26_format.immediate_h == 0) 413 return true; 414 } 415 416 switch (ip->reg1i21_format.opcode) { 417 case beqz_op: 418 case bnez_op: 419 case bceqz_op: 420 if (ip->reg1i21_format.immediate_l == 0 421 && ip->reg1i21_format.immediate_h == 0) 422 return true; 423 } 424 425 switch (ip->reg2i16_format.opcode) { 426 case beq_op: 427 case bne_op: 428 case blt_op: 429 case bge_op: 430 case bltu_op: 431 case bgeu_op: 432 if (ip->reg2i16_format.immediate == 0) 433 return true; 434 break; 435 case jirl_op: 436 if (regs->regs[ip->reg2i16_format.rj] + 437 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip) 438 return true; 439 } 440 441 return false; 442 } 443 444 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn); 445 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn); 446 447 int larch_insn_read(void *addr, u32 *insnp); 448 int larch_insn_write(void *addr, u32 insn); 449 int larch_insn_patch_text(void *addr, u32 insn); 450 451 u32 larch_insn_gen_nop(void); 452 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest); 453 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest); 454 455 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk); 456 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj); 457 458 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm); 459 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm); 460 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 461 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 462 463 static inline bool signed_imm_check(long val, unsigned int bit) 464 { 465 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1)); 466 } 467 468 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit) 469 { 470 return val < (1UL << bit); 471 } 472 473 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \ 474 static inline void emit_##NAME(union loongarch_instruction *insn, \ 475 int offset) \ 476 { \ 477 unsigned int immediate_l, immediate_h; \ 478 \ 479 immediate_l = offset & 0xffff; \ 480 offset >>= 16; \ 481 immediate_h = offset & 0x3ff; \ 482 \ 483 insn->reg0i26_format.opcode = OP; \ 484 insn->reg0i26_format.immediate_l = immediate_l; \ 485 insn->reg0i26_format.immediate_h = immediate_h; \ 486 } 487 488 DEF_EMIT_REG0I26_FORMAT(b, b_op) 489 DEF_EMIT_REG0I26_FORMAT(bl, bl_op) 490 491 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \ 492 static inline void emit_##NAME(union loongarch_instruction *insn, \ 493 enum loongarch_gpr rd, int imm) \ 494 { \ 495 insn->reg1i20_format.opcode = OP; \ 496 insn->reg1i20_format.immediate = imm; \ 497 insn->reg1i20_format.rd = rd; \ 498 } 499 500 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op) 501 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op) 502 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op) 503 504 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \ 505 static inline void emit_##NAME(union loongarch_instruction *insn, \ 506 enum loongarch_gpr rd, \ 507 enum loongarch_gpr rj) \ 508 { \ 509 insn->reg2_format.opcode = OP; \ 510 insn->reg2_format.rd = rd; \ 511 insn->reg2_format.rj = rj; \ 512 } 513 514 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op) 515 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op) 516 DEF_EMIT_REG2_FORMAT(revbd, revbd_op) 517 518 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \ 519 static inline void emit_##NAME(union loongarch_instruction *insn, \ 520 enum loongarch_gpr rd, \ 521 enum loongarch_gpr rj, \ 522 int imm) \ 523 { \ 524 insn->reg2i5_format.opcode = OP; \ 525 insn->reg2i5_format.immediate = imm; \ 526 insn->reg2i5_format.rd = rd; \ 527 insn->reg2i5_format.rj = rj; \ 528 } 529 530 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op) 531 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op) 532 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op) 533 534 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \ 535 static inline void emit_##NAME(union loongarch_instruction *insn, \ 536 enum loongarch_gpr rd, \ 537 enum loongarch_gpr rj, \ 538 int imm) \ 539 { \ 540 insn->reg2i6_format.opcode = OP; \ 541 insn->reg2i6_format.immediate = imm; \ 542 insn->reg2i6_format.rd = rd; \ 543 insn->reg2i6_format.rj = rj; \ 544 } 545 546 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op) 547 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op) 548 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op) 549 550 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \ 551 static inline void emit_##NAME(union loongarch_instruction *insn, \ 552 enum loongarch_gpr rd, \ 553 enum loongarch_gpr rj, \ 554 int imm) \ 555 { \ 556 insn->reg2i12_format.opcode = OP; \ 557 insn->reg2i12_format.immediate = imm; \ 558 insn->reg2i12_format.rd = rd; \ 559 insn->reg2i12_format.rj = rj; \ 560 } 561 562 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op) 563 DEF_EMIT_REG2I12_FORMAT(addid, addid_op) 564 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op) 565 DEF_EMIT_REG2I12_FORMAT(andi, andi_op) 566 DEF_EMIT_REG2I12_FORMAT(ori, ori_op) 567 DEF_EMIT_REG2I12_FORMAT(xori, xori_op) 568 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op) 569 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op) 570 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op) 571 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op) 572 DEF_EMIT_REG2I12_FORMAT(stb, stb_op) 573 DEF_EMIT_REG2I12_FORMAT(sth, sth_op) 574 DEF_EMIT_REG2I12_FORMAT(stw, stw_op) 575 DEF_EMIT_REG2I12_FORMAT(std, std_op) 576 577 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \ 578 static inline void emit_##NAME(union loongarch_instruction *insn, \ 579 enum loongarch_gpr rd, \ 580 enum loongarch_gpr rj, \ 581 int imm) \ 582 { \ 583 insn->reg2i14_format.opcode = OP; \ 584 insn->reg2i14_format.immediate = imm; \ 585 insn->reg2i14_format.rd = rd; \ 586 insn->reg2i14_format.rj = rj; \ 587 } 588 589 DEF_EMIT_REG2I14_FORMAT(llw, llw_op) 590 DEF_EMIT_REG2I14_FORMAT(scw, scw_op) 591 DEF_EMIT_REG2I14_FORMAT(lld, lld_op) 592 DEF_EMIT_REG2I14_FORMAT(scd, scd_op) 593 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op) 594 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op) 595 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op) 596 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op) 597 598 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \ 599 static inline void emit_##NAME(union loongarch_instruction *insn, \ 600 enum loongarch_gpr rj, \ 601 enum loongarch_gpr rd, \ 602 int offset) \ 603 { \ 604 insn->reg2i16_format.opcode = OP; \ 605 insn->reg2i16_format.immediate = offset; \ 606 insn->reg2i16_format.rj = rj; \ 607 insn->reg2i16_format.rd = rd; \ 608 } 609 610 DEF_EMIT_REG2I16_FORMAT(beq, beq_op) 611 DEF_EMIT_REG2I16_FORMAT(bne, bne_op) 612 DEF_EMIT_REG2I16_FORMAT(blt, blt_op) 613 DEF_EMIT_REG2I16_FORMAT(bge, bge_op) 614 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op) 615 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op) 616 DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op) 617 618 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \ 619 static inline void emit_##NAME(union loongarch_instruction *insn, \ 620 enum loongarch_gpr rd, \ 621 enum loongarch_gpr rj, \ 622 int msbd, \ 623 int lsbd) \ 624 { \ 625 insn->reg2bstrd_format.opcode = OP; \ 626 insn->reg2bstrd_format.msbd = msbd; \ 627 insn->reg2bstrd_format.lsbd = lsbd; \ 628 insn->reg2bstrd_format.rj = rj; \ 629 insn->reg2bstrd_format.rd = rd; \ 630 } 631 632 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op) 633 634 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \ 635 static inline void emit_##NAME(union loongarch_instruction *insn, \ 636 enum loongarch_gpr rd, \ 637 enum loongarch_gpr rj, \ 638 enum loongarch_gpr rk) \ 639 { \ 640 insn->reg3_format.opcode = OP; \ 641 insn->reg3_format.rd = rd; \ 642 insn->reg3_format.rj = rj; \ 643 insn->reg3_format.rk = rk; \ 644 } 645 646 DEF_EMIT_REG3_FORMAT(addd, addd_op) 647 DEF_EMIT_REG3_FORMAT(subd, subd_op) 648 DEF_EMIT_REG3_FORMAT(muld, muld_op) 649 DEF_EMIT_REG3_FORMAT(divdu, divdu_op) 650 DEF_EMIT_REG3_FORMAT(moddu, moddu_op) 651 DEF_EMIT_REG3_FORMAT(and, and_op) 652 DEF_EMIT_REG3_FORMAT(or, or_op) 653 DEF_EMIT_REG3_FORMAT(xor, xor_op) 654 DEF_EMIT_REG3_FORMAT(sllw, sllw_op) 655 DEF_EMIT_REG3_FORMAT(slld, slld_op) 656 DEF_EMIT_REG3_FORMAT(srlw, srlw_op) 657 DEF_EMIT_REG3_FORMAT(srld, srld_op) 658 DEF_EMIT_REG3_FORMAT(sraw, sraw_op) 659 DEF_EMIT_REG3_FORMAT(srad, srad_op) 660 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op) 661 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op) 662 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op) 663 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op) 664 DEF_EMIT_REG3_FORMAT(stxb, stxb_op) 665 DEF_EMIT_REG3_FORMAT(stxh, stxh_op) 666 DEF_EMIT_REG3_FORMAT(stxw, stxw_op) 667 DEF_EMIT_REG3_FORMAT(stxd, stxd_op) 668 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op) 669 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op) 670 DEF_EMIT_REG3_FORMAT(amandw, amandw_op) 671 DEF_EMIT_REG3_FORMAT(amandd, amandd_op) 672 DEF_EMIT_REG3_FORMAT(amorw, amorw_op) 673 DEF_EMIT_REG3_FORMAT(amord, amord_op) 674 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op) 675 DEF_EMIT_REG3_FORMAT(amxord, amxord_op) 676 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op) 677 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op) 678 679 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \ 680 static inline void emit_##NAME(union loongarch_instruction *insn, \ 681 enum loongarch_gpr rd, \ 682 enum loongarch_gpr rj, \ 683 enum loongarch_gpr rk, \ 684 int imm) \ 685 { \ 686 insn->reg3sa2_format.opcode = OP; \ 687 insn->reg3sa2_format.immediate = imm; \ 688 insn->reg3sa2_format.rd = rd; \ 689 insn->reg3sa2_format.rj = rj; \ 690 insn->reg3sa2_format.rk = rk; \ 691 } 692 693 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op) 694 695 struct pt_regs; 696 697 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc); 698 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign); 699 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n); 700 701 #endif /* _ASM_INST_H */ 702