1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 4 */ 5 #ifndef _ASM_INST_H 6 #define _ASM_INST_H 7 8 #include <linux/bitops.h> 9 #include <linux/types.h> 10 #include <asm/asm.h> 11 #include <asm/ptrace.h> 12 13 #define INSN_NOP 0x03400000 14 #define INSN_BREAK 0x002a0000 15 #define INSN_HVCL 0x002b8000 16 17 #define ADDR_IMMMASK_LU52ID 0xFFF0000000000000 18 #define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000 19 #define ADDR_IMMMASK_LU12IW 0x00000000FFFFF000 20 #define ADDR_IMMMASK_ORI 0x0000000000000FFF 21 #define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000 22 23 #define ADDR_IMMSHIFT_LU52ID 52 24 #define ADDR_IMMSBIDX_LU52ID 11 25 #define ADDR_IMMSHIFT_LU32ID 32 26 #define ADDR_IMMSBIDX_LU32ID 19 27 #define ADDR_IMMSHIFT_LU12IW 12 28 #define ADDR_IMMSBIDX_LU12IW 19 29 #define ADDR_IMMSHIFT_ORI 0 30 #define ADDR_IMMSBIDX_ORI 63 31 #define ADDR_IMMSHIFT_ADDU16ID 16 32 #define ADDR_IMMSBIDX_ADDU16ID 15 33 34 #define ADDR_IMM(addr, INSN) \ 35 (sign_extend64(((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN), ADDR_IMMSBIDX_##INSN)) 36 37 enum reg0i15_op { 38 break_op = 0x54, 39 }; 40 41 enum reg0i26_op { 42 b_op = 0x14, 43 bl_op = 0x15, 44 }; 45 46 enum reg1i20_op { 47 lu12iw_op = 0x0a, 48 lu32id_op = 0x0b, 49 pcaddi_op = 0x0c, 50 pcalau12i_op = 0x0d, 51 pcaddu12i_op = 0x0e, 52 pcaddu18i_op = 0x0f, 53 }; 54 55 enum reg1i21_op { 56 beqz_op = 0x10, 57 bnez_op = 0x11, 58 bceqz_op = 0x12, /* bits[9:8] = 0x00 */ 59 bcnez_op = 0x12, /* bits[9:8] = 0x01 */ 60 }; 61 62 enum reg2_op { 63 revb2h_op = 0x0c, 64 revb4h_op = 0x0d, 65 revb2w_op = 0x0e, 66 revbd_op = 0x0f, 67 revh2w_op = 0x10, 68 revhd_op = 0x11, 69 extwh_op = 0x16, 70 extwb_op = 0x17, 71 cpucfg_op = 0x1b, 72 iocsrrdb_op = 0x19200, 73 iocsrrdh_op = 0x19201, 74 iocsrrdw_op = 0x19202, 75 iocsrrdd_op = 0x19203, 76 iocsrwrb_op = 0x19204, 77 iocsrwrh_op = 0x19205, 78 iocsrwrw_op = 0x19206, 79 iocsrwrd_op = 0x19207, 80 llacqw_op = 0xe15e0, 81 screlw_op = 0xe15e1, 82 llacqd_op = 0xe15e2, 83 screld_op = 0xe15e3, 84 }; 85 86 enum reg2i5_op { 87 slliw_op = 0x81, 88 srliw_op = 0x89, 89 sraiw_op = 0x91, 90 }; 91 92 enum reg2i6_op { 93 sllid_op = 0x41, 94 srlid_op = 0x45, 95 sraid_op = 0x49, 96 }; 97 98 enum reg2i12_op { 99 addiw_op = 0x0a, 100 addid_op = 0x0b, 101 lu52id_op = 0x0c, 102 andi_op = 0x0d, 103 ori_op = 0x0e, 104 xori_op = 0x0f, 105 ldb_op = 0xa0, 106 ldh_op = 0xa1, 107 ldw_op = 0xa2, 108 ldd_op = 0xa3, 109 stb_op = 0xa4, 110 sth_op = 0xa5, 111 stw_op = 0xa6, 112 std_op = 0xa7, 113 ldbu_op = 0xa8, 114 ldhu_op = 0xa9, 115 ldwu_op = 0xaa, 116 flds_op = 0xac, 117 fsts_op = 0xad, 118 fldd_op = 0xae, 119 fstd_op = 0xaf, 120 }; 121 122 enum reg2i14_op { 123 llw_op = 0x20, 124 scw_op = 0x21, 125 lld_op = 0x22, 126 scd_op = 0x23, 127 ldptrw_op = 0x24, 128 stptrw_op = 0x25, 129 ldptrd_op = 0x26, 130 stptrd_op = 0x27, 131 }; 132 133 enum reg2i16_op { 134 jirl_op = 0x13, 135 beq_op = 0x16, 136 bne_op = 0x17, 137 blt_op = 0x18, 138 bge_op = 0x19, 139 bltu_op = 0x1a, 140 bgeu_op = 0x1b, 141 }; 142 143 enum reg2bstrd_op { 144 bstrinsd_op = 0x2, 145 bstrpickd_op = 0x3, 146 }; 147 148 enum reg3_op { 149 asrtle_op = 0x02, 150 asrtgt_op = 0x03, 151 addw_op = 0x20, 152 addd_op = 0x21, 153 subw_op = 0x22, 154 subd_op = 0x23, 155 nor_op = 0x28, 156 and_op = 0x29, 157 or_op = 0x2a, 158 xor_op = 0x2b, 159 orn_op = 0x2c, 160 andn_op = 0x2d, 161 sllw_op = 0x2e, 162 srlw_op = 0x2f, 163 sraw_op = 0x30, 164 slld_op = 0x31, 165 srld_op = 0x32, 166 srad_op = 0x33, 167 mulw_op = 0x38, 168 mulhw_op = 0x39, 169 mulhwu_op = 0x3a, 170 muld_op = 0x3b, 171 mulhd_op = 0x3c, 172 mulhdu_op = 0x3d, 173 divw_op = 0x40, 174 modw_op = 0x41, 175 divwu_op = 0x42, 176 modwu_op = 0x43, 177 divd_op = 0x44, 178 modd_op = 0x45, 179 divdu_op = 0x46, 180 moddu_op = 0x47, 181 ldxb_op = 0x7000, 182 ldxh_op = 0x7008, 183 ldxw_op = 0x7010, 184 ldxd_op = 0x7018, 185 stxb_op = 0x7020, 186 stxh_op = 0x7028, 187 stxw_op = 0x7030, 188 stxd_op = 0x7038, 189 ldxbu_op = 0x7040, 190 ldxhu_op = 0x7048, 191 ldxwu_op = 0x7050, 192 fldxs_op = 0x7060, 193 fldxd_op = 0x7068, 194 fstxs_op = 0x7070, 195 fstxd_op = 0x7078, 196 scq_op = 0x70ae, 197 amswapw_op = 0x70c0, 198 amswapd_op = 0x70c1, 199 amaddw_op = 0x70c2, 200 amaddd_op = 0x70c3, 201 amandw_op = 0x70c4, 202 amandd_op = 0x70c5, 203 amorw_op = 0x70c6, 204 amord_op = 0x70c7, 205 amxorw_op = 0x70c8, 206 amxord_op = 0x70c9, 207 ammaxw_op = 0x70ca, 208 ammaxd_op = 0x70cb, 209 amminw_op = 0x70cc, 210 ammind_op = 0x70cd, 211 ammaxwu_op = 0x70ce, 212 ammaxdu_op = 0x70cf, 213 amminwu_op = 0x70d0, 214 ammindu_op = 0x70d1, 215 amswapdbw_op = 0x70d2, 216 amswapdbd_op = 0x70d3, 217 amadddbw_op = 0x70d4, 218 amadddbd_op = 0x70d5, 219 amanddbw_op = 0x70d6, 220 amanddbd_op = 0x70d7, 221 amordbw_op = 0x70d8, 222 amordbd_op = 0x70d9, 223 amxordbw_op = 0x70da, 224 amxordbd_op = 0x70db, 225 ammaxdbw_op = 0x70dc, 226 ammaxdbd_op = 0x70dd, 227 ammindbw_op = 0x70de, 228 ammindbd_op = 0x70df, 229 ammaxdbwu_op = 0x70e0, 230 ammaxdbdu_op = 0x70e1, 231 ammindbwu_op = 0x70e2, 232 ammindbdu_op = 0x70e3, 233 fldgts_op = 0x70e8, 234 fldgtd_op = 0x70e9, 235 fldles_op = 0x70ea, 236 fldled_op = 0x70eb, 237 fstgts_op = 0x70ec, 238 fstgtd_op = 0x70ed, 239 fstles_op = 0x70ee, 240 fstled_op = 0x70ef, 241 ldgtb_op = 0x70f0, 242 ldgth_op = 0x70f1, 243 ldgtw_op = 0x70f2, 244 ldgtd_op = 0x70f3, 245 ldleb_op = 0x70f4, 246 ldleh_op = 0x70f5, 247 ldlew_op = 0x70f6, 248 ldled_op = 0x70f7, 249 stgtb_op = 0x70f8, 250 stgth_op = 0x70f9, 251 stgtw_op = 0x70fa, 252 stgtd_op = 0x70fb, 253 stleb_op = 0x70fc, 254 stleh_op = 0x70fd, 255 stlew_op = 0x70fe, 256 stled_op = 0x70ff, 257 }; 258 259 enum reg3sa2_op { 260 alslw_op = 0x02, 261 alslwu_op = 0x03, 262 alsld_op = 0x16, 263 }; 264 265 struct reg0i15_format { 266 unsigned int immediate : 15; 267 unsigned int opcode : 17; 268 }; 269 270 struct reg0i26_format { 271 unsigned int immediate_h : 10; 272 unsigned int immediate_l : 16; 273 unsigned int opcode : 6; 274 }; 275 276 struct reg1i20_format { 277 unsigned int rd : 5; 278 unsigned int immediate : 20; 279 unsigned int opcode : 7; 280 }; 281 282 struct reg1i21_format { 283 unsigned int immediate_h : 5; 284 unsigned int rj : 5; 285 unsigned int immediate_l : 16; 286 unsigned int opcode : 6; 287 }; 288 289 struct reg2_format { 290 unsigned int rd : 5; 291 unsigned int rj : 5; 292 unsigned int opcode : 22; 293 }; 294 295 struct reg2i5_format { 296 unsigned int rd : 5; 297 unsigned int rj : 5; 298 unsigned int immediate : 5; 299 unsigned int opcode : 17; 300 }; 301 302 struct reg2i6_format { 303 unsigned int rd : 5; 304 unsigned int rj : 5; 305 unsigned int immediate : 6; 306 unsigned int opcode : 16; 307 }; 308 309 struct reg2i12_format { 310 unsigned int rd : 5; 311 unsigned int rj : 5; 312 unsigned int immediate : 12; 313 unsigned int opcode : 10; 314 }; 315 316 struct reg2i14_format { 317 unsigned int rd : 5; 318 unsigned int rj : 5; 319 unsigned int immediate : 14; 320 unsigned int opcode : 8; 321 }; 322 323 struct reg2i16_format { 324 unsigned int rd : 5; 325 unsigned int rj : 5; 326 unsigned int immediate : 16; 327 unsigned int opcode : 6; 328 }; 329 330 struct reg2bstrd_format { 331 unsigned int rd : 5; 332 unsigned int rj : 5; 333 unsigned int lsbd : 6; 334 unsigned int msbd : 6; 335 unsigned int opcode : 10; 336 }; 337 338 struct reg2csr_format { 339 unsigned int rd : 5; 340 unsigned int rj : 5; 341 unsigned int csr : 14; 342 unsigned int opcode : 8; 343 }; 344 345 struct reg3_format { 346 unsigned int rd : 5; 347 unsigned int rj : 5; 348 unsigned int rk : 5; 349 unsigned int opcode : 17; 350 }; 351 352 struct reg3sa2_format { 353 unsigned int rd : 5; 354 unsigned int rj : 5; 355 unsigned int rk : 5; 356 unsigned int immediate : 2; 357 unsigned int opcode : 15; 358 }; 359 360 union loongarch_instruction { 361 unsigned int word; 362 struct reg0i15_format reg0i15_format; 363 struct reg0i26_format reg0i26_format; 364 struct reg1i20_format reg1i20_format; 365 struct reg1i21_format reg1i21_format; 366 struct reg2_format reg2_format; 367 struct reg2i5_format reg2i5_format; 368 struct reg2i6_format reg2i6_format; 369 struct reg2i12_format reg2i12_format; 370 struct reg2i14_format reg2i14_format; 371 struct reg2i16_format reg2i16_format; 372 struct reg2bstrd_format reg2bstrd_format; 373 struct reg2csr_format reg2csr_format; 374 struct reg3_format reg3_format; 375 struct reg3sa2_format reg3sa2_format; 376 }; 377 378 #define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction) 379 380 enum loongarch_gpr { 381 LOONGARCH_GPR_ZERO = 0, 382 LOONGARCH_GPR_RA = 1, 383 LOONGARCH_GPR_TP = 2, 384 LOONGARCH_GPR_SP = 3, 385 LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */ 386 LOONGARCH_GPR_A1, /* Reused as V1 for return value */ 387 LOONGARCH_GPR_A2, 388 LOONGARCH_GPR_A3, 389 LOONGARCH_GPR_A4, 390 LOONGARCH_GPR_A5, 391 LOONGARCH_GPR_A6, 392 LOONGARCH_GPR_A7, 393 LOONGARCH_GPR_T0 = 12, 394 LOONGARCH_GPR_T1, 395 LOONGARCH_GPR_T2, 396 LOONGARCH_GPR_T3, 397 LOONGARCH_GPR_T4, 398 LOONGARCH_GPR_T5, 399 LOONGARCH_GPR_T6, 400 LOONGARCH_GPR_T7, 401 LOONGARCH_GPR_T8, 402 LOONGARCH_GPR_FP = 22, 403 LOONGARCH_GPR_S0 = 23, 404 LOONGARCH_GPR_S1, 405 LOONGARCH_GPR_S2, 406 LOONGARCH_GPR_S3, 407 LOONGARCH_GPR_S4, 408 LOONGARCH_GPR_S5, 409 LOONGARCH_GPR_S6, 410 LOONGARCH_GPR_S7, 411 LOONGARCH_GPR_S8, 412 LOONGARCH_GPR_MAX 413 }; 414 415 #define is_imm12_negative(val) is_imm_negative(val, 12) 416 417 static inline bool is_imm_negative(unsigned long val, unsigned int bit) 418 { 419 return val & (1UL << (bit - 1)); 420 } 421 422 static inline bool is_break_ins(union loongarch_instruction *ip) 423 { 424 return ip->reg0i15_format.opcode == break_op; 425 } 426 427 static inline bool is_pc_ins(union loongarch_instruction *ip) 428 { 429 return ip->reg1i20_format.opcode >= pcaddi_op && 430 ip->reg1i20_format.opcode <= pcaddu18i_op; 431 } 432 433 static inline bool is_branch_ins(union loongarch_instruction *ip) 434 { 435 return ip->reg1i21_format.opcode >= beqz_op && 436 ip->reg1i21_format.opcode <= bgeu_op; 437 } 438 439 static inline bool is_ra_save_ins(union loongarch_instruction *ip) 440 { 441 /* st.d $ra, $sp, offset */ 442 return ip->reg2i12_format.opcode == std_op && 443 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 444 ip->reg2i12_format.rd == LOONGARCH_GPR_RA && 445 !is_imm12_negative(ip->reg2i12_format.immediate); 446 } 447 448 static inline bool is_stack_alloc_ins(union loongarch_instruction *ip) 449 { 450 /* addi.d $sp, $sp, -imm */ 451 return ip->reg2i12_format.opcode == addid_op && 452 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && 453 ip->reg2i12_format.rd == LOONGARCH_GPR_SP && 454 is_imm12_negative(ip->reg2i12_format.immediate); 455 } 456 457 static inline bool is_self_loop_ins(union loongarch_instruction *ip, struct pt_regs *regs) 458 { 459 switch (ip->reg0i26_format.opcode) { 460 case b_op: 461 case bl_op: 462 if (ip->reg0i26_format.immediate_l == 0 463 && ip->reg0i26_format.immediate_h == 0) 464 return true; 465 } 466 467 switch (ip->reg1i21_format.opcode) { 468 case beqz_op: 469 case bnez_op: 470 case bceqz_op: 471 if (ip->reg1i21_format.immediate_l == 0 472 && ip->reg1i21_format.immediate_h == 0) 473 return true; 474 } 475 476 switch (ip->reg2i16_format.opcode) { 477 case beq_op: 478 case bne_op: 479 case blt_op: 480 case bge_op: 481 case bltu_op: 482 case bgeu_op: 483 if (ip->reg2i16_format.immediate == 0) 484 return true; 485 break; 486 case jirl_op: 487 if (regs->regs[ip->reg2i16_format.rj] + 488 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip) 489 return true; 490 } 491 492 return false; 493 } 494 495 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn); 496 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn); 497 498 bool insns_not_supported(union loongarch_instruction insn); 499 bool insns_need_simulation(union loongarch_instruction insn); 500 void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs); 501 502 int larch_insn_read(void *addr, u32 *insnp); 503 int larch_insn_write(void *addr, u32 insn); 504 int larch_insn_patch_text(void *addr, u32 insn); 505 int larch_insn_text_copy(void *dst, void *src, size_t len); 506 507 u32 larch_insn_gen_nop(void); 508 u32 larch_insn_gen_b(unsigned long pc, unsigned long dest); 509 u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest); 510 511 u32 larch_insn_gen_break(int imm); 512 513 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk); 514 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj); 515 516 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm); 517 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm); 518 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 519 u32 larch_insn_gen_beq(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 520 u32 larch_insn_gen_bne(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 521 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm); 522 523 static inline bool signed_imm_check(long val, unsigned int bit) 524 { 525 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1)); 526 } 527 528 static inline bool unsigned_imm_check(unsigned long val, unsigned int bit) 529 { 530 return val < (1UL << bit); 531 } 532 533 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \ 534 static inline void emit_##NAME(union loongarch_instruction *insn, \ 535 int imm) \ 536 { \ 537 insn->reg0i15_format.opcode = OP; \ 538 insn->reg0i15_format.immediate = imm; \ 539 } 540 541 DEF_EMIT_REG0I15_FORMAT(break, break_op) 542 543 /* like emit_break(imm) but returns a constant expression */ 544 #define __emit_break(imm) ((u32)((imm) | (break_op << 15))) 545 546 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \ 547 static inline void emit_##NAME(union loongarch_instruction *insn, \ 548 int offset) \ 549 { \ 550 unsigned int immediate_l, immediate_h; \ 551 \ 552 immediate_l = offset & 0xffff; \ 553 offset >>= 16; \ 554 immediate_h = offset & 0x3ff; \ 555 \ 556 insn->reg0i26_format.opcode = OP; \ 557 insn->reg0i26_format.immediate_l = immediate_l; \ 558 insn->reg0i26_format.immediate_h = immediate_h; \ 559 } 560 561 DEF_EMIT_REG0I26_FORMAT(b, b_op) 562 DEF_EMIT_REG0I26_FORMAT(bl, bl_op) 563 564 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \ 565 static inline void emit_##NAME(union loongarch_instruction *insn, \ 566 enum loongarch_gpr rd, int imm) \ 567 { \ 568 insn->reg1i20_format.opcode = OP; \ 569 insn->reg1i20_format.immediate = imm; \ 570 insn->reg1i20_format.rd = rd; \ 571 } 572 573 DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op) 574 DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op) 575 DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op) 576 577 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \ 578 static inline void emit_##NAME(union loongarch_instruction *insn, \ 579 enum loongarch_gpr rd, \ 580 enum loongarch_gpr rj) \ 581 { \ 582 insn->reg2_format.opcode = OP; \ 583 insn->reg2_format.rd = rd; \ 584 insn->reg2_format.rj = rj; \ 585 } 586 587 DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op) 588 DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op) 589 DEF_EMIT_REG2_FORMAT(revbd, revbd_op) 590 DEF_EMIT_REG2_FORMAT(extwh, extwh_op) 591 DEF_EMIT_REG2_FORMAT(extwb, extwb_op) 592 593 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \ 594 static inline void emit_##NAME(union loongarch_instruction *insn, \ 595 enum loongarch_gpr rd, \ 596 enum loongarch_gpr rj, \ 597 int imm) \ 598 { \ 599 insn->reg2i5_format.opcode = OP; \ 600 insn->reg2i5_format.immediate = imm; \ 601 insn->reg2i5_format.rd = rd; \ 602 insn->reg2i5_format.rj = rj; \ 603 } 604 605 DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op) 606 DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op) 607 DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op) 608 609 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \ 610 static inline void emit_##NAME(union loongarch_instruction *insn, \ 611 enum loongarch_gpr rd, \ 612 enum loongarch_gpr rj, \ 613 int imm) \ 614 { \ 615 insn->reg2i6_format.opcode = OP; \ 616 insn->reg2i6_format.immediate = imm; \ 617 insn->reg2i6_format.rd = rd; \ 618 insn->reg2i6_format.rj = rj; \ 619 } 620 621 DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op) 622 DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op) 623 DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op) 624 625 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \ 626 static inline void emit_##NAME(union loongarch_instruction *insn, \ 627 enum loongarch_gpr rd, \ 628 enum loongarch_gpr rj, \ 629 int imm) \ 630 { \ 631 insn->reg2i12_format.opcode = OP; \ 632 insn->reg2i12_format.immediate = imm; \ 633 insn->reg2i12_format.rd = rd; \ 634 insn->reg2i12_format.rj = rj; \ 635 } 636 637 DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op) 638 DEF_EMIT_REG2I12_FORMAT(addid, addid_op) 639 DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op) 640 DEF_EMIT_REG2I12_FORMAT(andi, andi_op) 641 DEF_EMIT_REG2I12_FORMAT(ori, ori_op) 642 DEF_EMIT_REG2I12_FORMAT(xori, xori_op) 643 DEF_EMIT_REG2I12_FORMAT(ldb, ldb_op) 644 DEF_EMIT_REG2I12_FORMAT(ldh, ldh_op) 645 DEF_EMIT_REG2I12_FORMAT(ldw, ldw_op) 646 DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op) 647 DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op) 648 DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op) 649 DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op) 650 DEF_EMIT_REG2I12_FORMAT(stb, stb_op) 651 DEF_EMIT_REG2I12_FORMAT(sth, sth_op) 652 DEF_EMIT_REG2I12_FORMAT(stw, stw_op) 653 DEF_EMIT_REG2I12_FORMAT(std, std_op) 654 655 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \ 656 static inline void emit_##NAME(union loongarch_instruction *insn, \ 657 enum loongarch_gpr rd, \ 658 enum loongarch_gpr rj, \ 659 int imm) \ 660 { \ 661 insn->reg2i14_format.opcode = OP; \ 662 insn->reg2i14_format.immediate = imm; \ 663 insn->reg2i14_format.rd = rd; \ 664 insn->reg2i14_format.rj = rj; \ 665 } 666 667 DEF_EMIT_REG2I14_FORMAT(llw, llw_op) 668 DEF_EMIT_REG2I14_FORMAT(scw, scw_op) 669 DEF_EMIT_REG2I14_FORMAT(lld, lld_op) 670 DEF_EMIT_REG2I14_FORMAT(scd, scd_op) 671 DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op) 672 DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op) 673 DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op) 674 DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op) 675 676 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \ 677 static inline void emit_##NAME(union loongarch_instruction *insn, \ 678 enum loongarch_gpr rj, \ 679 enum loongarch_gpr rd, \ 680 int offset) \ 681 { \ 682 insn->reg2i16_format.opcode = OP; \ 683 insn->reg2i16_format.immediate = offset; \ 684 insn->reg2i16_format.rj = rj; \ 685 insn->reg2i16_format.rd = rd; \ 686 } 687 688 DEF_EMIT_REG2I16_FORMAT(beq, beq_op) 689 DEF_EMIT_REG2I16_FORMAT(bne, bne_op) 690 DEF_EMIT_REG2I16_FORMAT(blt, blt_op) 691 DEF_EMIT_REG2I16_FORMAT(bge, bge_op) 692 DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op) 693 DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op) 694 695 static inline void emit_jirl(union loongarch_instruction *insn, 696 enum loongarch_gpr rd, 697 enum loongarch_gpr rj, 698 int offset) 699 { 700 insn->reg2i16_format.opcode = jirl_op; 701 insn->reg2i16_format.immediate = offset; 702 insn->reg2i16_format.rd = rd; 703 insn->reg2i16_format.rj = rj; 704 } 705 706 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \ 707 static inline void emit_##NAME(union loongarch_instruction *insn, \ 708 enum loongarch_gpr rd, \ 709 enum loongarch_gpr rj, \ 710 int msbd, \ 711 int lsbd) \ 712 { \ 713 insn->reg2bstrd_format.opcode = OP; \ 714 insn->reg2bstrd_format.msbd = msbd; \ 715 insn->reg2bstrd_format.lsbd = lsbd; \ 716 insn->reg2bstrd_format.rj = rj; \ 717 insn->reg2bstrd_format.rd = rd; \ 718 } 719 720 DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op) 721 722 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \ 723 static inline void emit_##NAME(union loongarch_instruction *insn, \ 724 enum loongarch_gpr rd, \ 725 enum loongarch_gpr rj, \ 726 enum loongarch_gpr rk) \ 727 { \ 728 insn->reg3_format.opcode = OP; \ 729 insn->reg3_format.rd = rd; \ 730 insn->reg3_format.rj = rj; \ 731 insn->reg3_format.rk = rk; \ 732 } 733 734 DEF_EMIT_REG3_FORMAT(addw, addw_op) 735 DEF_EMIT_REG3_FORMAT(addd, addd_op) 736 DEF_EMIT_REG3_FORMAT(subd, subd_op) 737 DEF_EMIT_REG3_FORMAT(muld, muld_op) 738 DEF_EMIT_REG3_FORMAT(divd, divd_op) 739 DEF_EMIT_REG3_FORMAT(modd, modd_op) 740 DEF_EMIT_REG3_FORMAT(divdu, divdu_op) 741 DEF_EMIT_REG3_FORMAT(moddu, moddu_op) 742 DEF_EMIT_REG3_FORMAT(and, and_op) 743 DEF_EMIT_REG3_FORMAT(or, or_op) 744 DEF_EMIT_REG3_FORMAT(xor, xor_op) 745 DEF_EMIT_REG3_FORMAT(sllw, sllw_op) 746 DEF_EMIT_REG3_FORMAT(slld, slld_op) 747 DEF_EMIT_REG3_FORMAT(srlw, srlw_op) 748 DEF_EMIT_REG3_FORMAT(srld, srld_op) 749 DEF_EMIT_REG3_FORMAT(sraw, sraw_op) 750 DEF_EMIT_REG3_FORMAT(srad, srad_op) 751 DEF_EMIT_REG3_FORMAT(ldxb, ldxb_op) 752 DEF_EMIT_REG3_FORMAT(ldxh, ldxh_op) 753 DEF_EMIT_REG3_FORMAT(ldxw, ldxw_op) 754 DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op) 755 DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op) 756 DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op) 757 DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op) 758 DEF_EMIT_REG3_FORMAT(stxb, stxb_op) 759 DEF_EMIT_REG3_FORMAT(stxh, stxh_op) 760 DEF_EMIT_REG3_FORMAT(stxw, stxw_op) 761 DEF_EMIT_REG3_FORMAT(stxd, stxd_op) 762 DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op) 763 DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op) 764 DEF_EMIT_REG3_FORMAT(amandw, amandw_op) 765 DEF_EMIT_REG3_FORMAT(amandd, amandd_op) 766 DEF_EMIT_REG3_FORMAT(amorw, amorw_op) 767 DEF_EMIT_REG3_FORMAT(amord, amord_op) 768 DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op) 769 DEF_EMIT_REG3_FORMAT(amxord, amxord_op) 770 DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op) 771 DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op) 772 773 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \ 774 static inline void emit_##NAME(union loongarch_instruction *insn, \ 775 enum loongarch_gpr rd, \ 776 enum loongarch_gpr rj, \ 777 enum loongarch_gpr rk, \ 778 int imm) \ 779 { \ 780 insn->reg3sa2_format.opcode = OP; \ 781 insn->reg3sa2_format.immediate = imm; \ 782 insn->reg3sa2_format.rd = rd; \ 783 insn->reg3sa2_format.rj = rj; \ 784 insn->reg3sa2_format.rk = rk; \ 785 } 786 787 DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op) 788 789 struct pt_regs; 790 791 void emulate_load_store_insn(struct pt_regs *regs, void __user *addr, unsigned int *pc); 792 unsigned long unaligned_read(void __user *addr, void *value, unsigned long n, bool sign); 793 unsigned long unaligned_write(void __user *addr, unsigned long value, unsigned long n); 794 795 #endif /* _ASM_INST_H */ 796