1# SPDX-License-Identifier: GPL-2.0 2config LOONGARCH 3 bool 4 default y 5 select ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_MCFG if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_PPTT if ACPI 10 select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI 11 select ARCH_BINFMT_ELF_STATE 12 select ARCH_DISABLE_KASAN_INLINE 13 select ARCH_ENABLE_MEMORY_HOTPLUG 14 select ARCH_ENABLE_MEMORY_HOTREMOVE 15 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 17 select ARCH_HAS_CPU_FINALIZE_INIT 18 select ARCH_HAS_CURRENT_STACK_POINTER 19 select ARCH_HAS_FAST_MULTIPLIER 20 select ARCH_HAS_FORTIFY_SOURCE 21 select ARCH_HAS_KCOV 22 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 24 select ARCH_HAS_PTE_SPECIAL 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_INLINE_READ_LOCK if !PREEMPTION 27 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 28 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 29 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 30 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 31 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 32 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 33 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 34 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 35 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 36 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 37 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 38 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 39 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 40 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 41 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 42 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 43 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 44 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 45 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 46 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 47 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 48 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 49 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 50 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 51 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 52 select ARCH_KEEP_MEMBLOCK 53 select ARCH_MIGHT_HAVE_PC_PARPORT 54 select ARCH_MIGHT_HAVE_PC_SERIO 55 select ARCH_SPARSEMEM_ENABLE 56 select ARCH_STACKWALK 57 select ARCH_SUPPORTS_ACPI 58 select ARCH_SUPPORTS_ATOMIC_RMW 59 select ARCH_SUPPORTS_HUGETLBFS 60 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 61 select ARCH_SUPPORTS_LTO_CLANG 62 select ARCH_SUPPORTS_LTO_CLANG_THIN 63 select ARCH_SUPPORTS_NUMA_BALANCING 64 select ARCH_USE_BUILTIN_BSWAP 65 select ARCH_USE_CMPXCHG_LOCKREF 66 select ARCH_USE_QUEUED_RWLOCKS 67 select ARCH_USE_QUEUED_SPINLOCKS 68 select ARCH_WANT_DEFAULT_BPF_JIT 69 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 70 select ARCH_WANT_LD_ORPHAN_WARN 71 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP 72 select ARCH_WANTS_NO_INSTR 73 select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE 74 select BUILDTIME_TABLE_SORT 75 select COMMON_CLK 76 select CPU_PM 77 select EFI 78 select GENERIC_CLOCKEVENTS 79 select GENERIC_CMOS_UPDATE 80 select GENERIC_CPU_AUTOPROBE 81 select GENERIC_CPU_DEVICES 82 select GENERIC_ENTRY 83 select GENERIC_GETTIMEOFDAY 84 select GENERIC_IOREMAP if !ARCH_IOREMAP 85 select GENERIC_IRQ_MULTI_HANDLER 86 select GENERIC_IRQ_PROBE 87 select GENERIC_IRQ_SHOW 88 select GENERIC_LIB_ASHLDI3 89 select GENERIC_LIB_ASHRDI3 90 select GENERIC_LIB_CMPDI2 91 select GENERIC_LIB_LSHRDI3 92 select GENERIC_LIB_UCMPDI2 93 select GENERIC_LIB_DEVMEM_IS_ALLOWED 94 select GENERIC_PCI_IOMAP 95 select GENERIC_SCHED_CLOCK 96 select GENERIC_SMP_IDLE_THREAD 97 select GENERIC_TIME_VSYSCALL 98 select GENERIC_VDSO_TIME_NS 99 select GPIOLIB 100 select HAS_IOPORT 101 select HAVE_ARCH_AUDITSYSCALL 102 select HAVE_ARCH_JUMP_LABEL 103 select HAVE_ARCH_JUMP_LABEL_RELATIVE 104 select HAVE_ARCH_KASAN 105 select HAVE_ARCH_KFENCE 106 select HAVE_ARCH_KGDB if PERF_EVENTS 107 select HAVE_ARCH_MMAP_RND_BITS if MMU 108 select HAVE_ARCH_SECCOMP 109 select HAVE_ARCH_SECCOMP_FILTER 110 select HAVE_ARCH_TRACEHOOK 111 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 112 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 113 select HAVE_ASM_MODVERSIONS 114 select HAVE_CONTEXT_TRACKING_USER 115 select HAVE_C_RECORDMCOUNT 116 select HAVE_DEBUG_KMEMLEAK 117 select HAVE_DEBUG_STACKOVERFLOW 118 select HAVE_DMA_CONTIGUOUS 119 select HAVE_DYNAMIC_FTRACE 120 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 121 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS 122 select HAVE_DYNAMIC_FTRACE_WITH_REGS 123 select HAVE_EBPF_JIT 124 select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN 125 select HAVE_EXIT_THREAD 126 select HAVE_FAST_GUP 127 select HAVE_FTRACE_MCOUNT_RECORD 128 select HAVE_FUNCTION_ARG_ACCESS_API 129 select HAVE_FUNCTION_ERROR_INJECTION 130 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 131 select HAVE_FUNCTION_GRAPH_TRACER 132 select HAVE_FUNCTION_TRACER 133 select HAVE_GCC_PLUGINS 134 select HAVE_GENERIC_VDSO 135 select HAVE_HW_BREAKPOINT if PERF_EVENTS 136 select HAVE_IOREMAP_PROT 137 select HAVE_IRQ_EXIT_ON_IRQ_STACK 138 select HAVE_IRQ_TIME_ACCOUNTING 139 select HAVE_KPROBES 140 select HAVE_KPROBES_ON_FTRACE 141 select HAVE_KRETPROBES 142 select HAVE_LIVEPATCH 143 select HAVE_MOD_ARCH_SPECIFIC 144 select HAVE_NMI 145 select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS 146 select HAVE_PCI 147 select HAVE_PERF_EVENTS 148 select HAVE_PERF_REGS 149 select HAVE_PERF_USER_STACK_DUMP 150 select HAVE_PREEMPT_DYNAMIC_KEY 151 select HAVE_REGS_AND_STACK_ACCESS_API 152 select HAVE_RELIABLE_STACKTRACE if UNWINDER_ORC 153 select HAVE_RETHOOK 154 select HAVE_RSEQ 155 select HAVE_RUST 156 select HAVE_SAMPLE_FTRACE_DIRECT 157 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 158 select HAVE_SETUP_PER_CPU_AREA if NUMA 159 select HAVE_STACK_VALIDATION if HAVE_OBJTOOL 160 select HAVE_STACKPROTECTOR 161 select HAVE_SYSCALL_TRACEPOINTS 162 select HAVE_TIF_NOHZ 163 select HAVE_VIRT_CPU_ACCOUNTING_GEN if !SMP 164 select IRQ_FORCED_THREADING 165 select IRQ_LOONGARCH_CPU 166 select LOCK_MM_AND_FIND_VMA 167 select MMU_GATHER_MERGE_VMAS if MMU 168 select MODULES_USE_ELF_RELA if MODULES 169 select NEED_PER_CPU_EMBED_FIRST_CHUNK 170 select NEED_PER_CPU_PAGE_FIRST_CHUNK 171 select OF 172 select OF_EARLY_FLATTREE 173 select PCI 174 select PCI_DOMAINS_GENERIC 175 select PCI_ECAM if ACPI 176 select PCI_LOONGSON 177 select PCI_MSI_ARCH_FALLBACKS 178 select PCI_QUIRKS 179 select PERF_USE_VMALLOC 180 select RTC_LIB 181 select SPARSE_IRQ 182 select SYSCTL_ARCH_UNALIGN_ALLOW 183 select SYSCTL_ARCH_UNALIGN_NO_WARN 184 select SYSCTL_EXCEPTION_TRACE 185 select SWIOTLB 186 select TRACE_IRQFLAGS_SUPPORT 187 select USE_PERCPU_NUMA_NODE_ID 188 select USER_STACKTRACE_SUPPORT 189 select ZONE_DMA32 190 191config 32BIT 192 bool 193 194config 64BIT 195 def_bool y 196 197config GENERIC_BUG 198 def_bool y 199 depends on BUG 200 201config GENERIC_BUG_RELATIVE_POINTERS 202 def_bool y 203 depends on GENERIC_BUG 204 205config GENERIC_CALIBRATE_DELAY 206 def_bool y 207 208config GENERIC_CSUM 209 def_bool y 210 211config GENERIC_HWEIGHT 212 def_bool y 213 214config L1_CACHE_SHIFT 215 int 216 default "6" 217 218config LOCKDEP_SUPPORT 219 bool 220 default y 221 222config STACKTRACE_SUPPORT 223 bool 224 default y 225 226# MACH_LOONGSON32 and MACH_LOONGSON64 are deliberately carried over from the 227# MIPS Loongson code, to preserve Loongson-specific code paths in drivers that 228# are shared between architectures, and specifically expecting the symbols. 229config MACH_LOONGSON32 230 def_bool 32BIT 231 232config MACH_LOONGSON64 233 def_bool 64BIT 234 235config FIX_EARLYCON_MEM 236 def_bool y 237 238config PGTABLE_2LEVEL 239 bool 240 241config PGTABLE_3LEVEL 242 bool 243 244config PGTABLE_4LEVEL 245 bool 246 247config PGTABLE_LEVELS 248 int 249 default 2 if PGTABLE_2LEVEL 250 default 3 if PGTABLE_3LEVEL 251 default 4 if PGTABLE_4LEVEL 252 253config SCHED_OMIT_FRAME_POINTER 254 bool 255 default y 256 257config AS_HAS_EXPLICIT_RELOCS 258 def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x)) 259 260config AS_HAS_FCSR_CLASS 261 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0) 262 263config AS_HAS_LSX_EXTENSION 264 def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0) 265 266config AS_HAS_LASX_EXTENSION 267 def_bool $(as-instr,xvld \$xr0$(comma)\$a0$(comma)0) 268 269config AS_HAS_LBT_EXTENSION 270 def_bool $(as-instr,movscr2gr \$a0$(comma)\$scr0) 271 272config AS_HAS_LVZ_EXTENSION 273 def_bool $(as-instr,hvcl 0) 274 275menu "Kernel type and options" 276 277source "kernel/Kconfig.hz" 278 279choice 280 prompt "Page Table Layout" 281 default 16KB_2LEVEL if 32BIT 282 default 16KB_3LEVEL if 64BIT 283 help 284 Allows choosing the page table layout, which is a combination 285 of page size and page table levels. The size of virtual memory 286 address space are determined by the page table layout. 287 288config 4KB_3LEVEL 289 bool "4KB with 3 levels" 290 select HAVE_PAGE_SIZE_4KB 291 select PGTABLE_3LEVEL 292 help 293 This option selects 4KB page size with 3 level page tables, which 294 support a maximum of 39 bits of application virtual memory. 295 296config 4KB_4LEVEL 297 bool "4KB with 4 levels" 298 select HAVE_PAGE_SIZE_4KB 299 select PGTABLE_4LEVEL 300 help 301 This option selects 4KB page size with 4 level page tables, which 302 support a maximum of 48 bits of application virtual memory. 303 304config 16KB_2LEVEL 305 bool "16KB with 2 levels" 306 select HAVE_PAGE_SIZE_16KB 307 select PGTABLE_2LEVEL 308 help 309 This option selects 16KB page size with 2 level page tables, which 310 support a maximum of 36 bits of application virtual memory. 311 312config 16KB_3LEVEL 313 bool "16KB with 3 levels" 314 select HAVE_PAGE_SIZE_16KB 315 select PGTABLE_3LEVEL 316 help 317 This option selects 16KB page size with 3 level page tables, which 318 support a maximum of 47 bits of application virtual memory. 319 320config 64KB_2LEVEL 321 bool "64KB with 2 levels" 322 select HAVE_PAGE_SIZE_64KB 323 select PGTABLE_2LEVEL 324 help 325 This option selects 64KB page size with 2 level page tables, which 326 support a maximum of 42 bits of application virtual memory. 327 328config 64KB_3LEVEL 329 bool "64KB with 3 levels" 330 select HAVE_PAGE_SIZE_64KB 331 select PGTABLE_3LEVEL 332 help 333 This option selects 64KB page size with 3 level page tables, which 334 support a maximum of 55 bits of application virtual memory. 335 336endchoice 337 338config CMDLINE 339 string "Built-in kernel command line" 340 help 341 For most platforms, the arguments for the kernel's command line 342 are provided at run-time, during boot. However, there are cases 343 where either no arguments are being provided or the provided 344 arguments are insufficient or even invalid. 345 346 When that occurs, it is possible to define a built-in command 347 line here and choose how the kernel should use it later on. 348 349choice 350 prompt "Kernel command line type" 351 default CMDLINE_BOOTLOADER 352 help 353 Choose how the kernel will handle the provided built-in command 354 line. 355 356config CMDLINE_BOOTLOADER 357 bool "Use bootloader kernel arguments if available" 358 help 359 Prefer the command-line passed by the boot loader if available. 360 Use the built-in command line as fallback in case we get nothing 361 during boot. This is the default behaviour. 362 363config CMDLINE_EXTEND 364 bool "Use built-in to extend bootloader kernel arguments" 365 help 366 The command-line arguments provided during boot will be 367 appended to the built-in command line. This is useful in 368 cases where the provided arguments are insufficient and 369 you don't want to or cannot modify them. 370 371config CMDLINE_FORCE 372 bool "Always use the built-in kernel command string" 373 help 374 Always use the built-in command line, even if we get one during 375 boot. This is useful in case you need to override the provided 376 command line on systems where you don't have or want control 377 over it. 378 379endchoice 380 381config BUILTIN_DTB 382 bool "Enable built-in dtb in kernel" 383 depends on OF 384 help 385 Some existing systems do not provide a canonical device tree to 386 the kernel at boot time. Let's provide a device tree table in the 387 kernel, keyed by the dts filename, containing the relevant DTBs. 388 389 Built-in DTBs are generic enough and can be used as references. 390 391config BUILTIN_DTB_NAME 392 string "Source file for built-in dtb" 393 depends on BUILTIN_DTB 394 help 395 Base name (without suffix, relative to arch/loongarch/boot/dts/) 396 for the DTS file that will be used to produce the DTB linked into 397 the kernel. 398 399config DMI 400 bool "Enable DMI scanning" 401 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK 402 default y 403 help 404 This enables SMBIOS/DMI feature for systems, and scanning of 405 DMI to identify machine quirks. 406 407config EFI 408 bool "EFI runtime service support" 409 select UCS2_STRING 410 select EFI_RUNTIME_WRAPPERS 411 help 412 This enables the kernel to use EFI runtime services that are 413 available (such as the EFI variable services). 414 415config EFI_STUB 416 bool "EFI boot stub support" 417 default y 418 depends on EFI 419 select EFI_GENERIC_STUB 420 help 421 This kernel feature allows the kernel to be loaded directly by 422 EFI firmware without the use of a bootloader. 423 424config SCHED_SMT 425 bool "SMT scheduler support" 426 depends on SMP 427 default y 428 help 429 Improves scheduler's performance when there are multiple 430 threads in one physical core. 431 432config SMP 433 bool "Multi-Processing support" 434 help 435 This enables support for systems with more than one CPU. If you have 436 a system with only one CPU, say N. If you have a system with more 437 than one CPU, say Y. 438 439 If you say N here, the kernel will run on uni- and multiprocessor 440 machines, but will use only one CPU of a multiprocessor machine. If 441 you say Y here, the kernel will run on many, but not all, 442 uniprocessor machines. On a uniprocessor machine, the kernel 443 will run faster if you say N here. 444 445 See also the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>. 446 447 If you don't know what to do here, say N. 448 449config HOTPLUG_CPU 450 bool "Support for hot-pluggable CPUs" 451 depends on SMP 452 select GENERIC_IRQ_MIGRATION 453 help 454 Say Y here to allow turning CPUs off and on. CPUs can be 455 controlled through /sys/devices/system/cpu. 456 (Note: power management support will enable this option 457 automatically on SMP systems. ) 458 Say N if you want to disable CPU hotplug. 459 460config NR_CPUS 461 int "Maximum number of CPUs (2-256)" 462 range 2 256 463 depends on SMP 464 default "64" 465 help 466 This allows you to specify the maximum number of CPUs which this 467 kernel will support. 468 469config NUMA 470 bool "NUMA Support" 471 select SMP 472 select ACPI_NUMA if ACPI 473 help 474 Say Y to compile the kernel with NUMA (Non-Uniform Memory Access) 475 support. This option improves performance on systems with more 476 than one NUMA node; on single node systems it is generally better 477 to leave it disabled. 478 479config NODES_SHIFT 480 int 481 default "6" 482 depends on NUMA 483 484config ARCH_FORCE_MAX_ORDER 485 int "Maximum zone order" 486 default "13" if PAGE_SIZE_64KB 487 default "11" if PAGE_SIZE_16KB 488 default "10" 489 help 490 The kernel memory allocator divides physically contiguous memory 491 blocks into "zones", where each zone is a power of two number of 492 pages. This option selects the largest power of two that the kernel 493 keeps in the memory allocator. If you need to allocate very large 494 blocks of physically contiguous memory, then you may need to 495 increase this value. 496 497 The page size is not necessarily 4KB. Keep this in mind 498 when choosing a value for this option. 499 500config ARCH_IOREMAP 501 bool "Enable LoongArch DMW-based ioremap()" 502 help 503 We use generic TLB-based ioremap() by default since it has page 504 protection support. However, you can enable LoongArch DMW-based 505 ioremap() for better performance. 506 507config ARCH_WRITECOMBINE 508 bool "Enable WriteCombine (WUC) for ioremap()" 509 help 510 LoongArch maintains cache coherency in hardware, but when paired 511 with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which 512 is similar to WriteCombine) is out of the scope of cache coherency 513 machanism for PCIe devices (this is a PCIe protocol violation, which 514 may be fixed in newer chipsets). 515 516 This means WUC can only used for write-only memory regions now, so 517 this option is disabled by default, making WUC silently fallback to 518 SUC for ioremap(). You can enable this option if the kernel is ensured 519 to run on hardware without this bug. 520 521 You can override this setting via writecombine=on/off boot parameter. 522 523config ARCH_STRICT_ALIGN 524 bool "Enable -mstrict-align to prevent unaligned accesses" if EXPERT 525 default y 526 help 527 Not all LoongArch cores support h/w unaligned access, we can use 528 -mstrict-align build parameter to prevent unaligned accesses. 529 530 CPUs with h/w unaligned access support: 531 Loongson-2K2000/2K3000/3A5000/3C5000/3D5000. 532 533 CPUs without h/w unaligned access support: 534 Loongson-2K500/2K1000. 535 536 This option is enabled by default to make the kernel be able to run 537 on all LoongArch systems. But you can disable it manually if you want 538 to run kernel only on systems with h/w unaligned access support in 539 order to optimise for performance. 540 541config CPU_HAS_FPU 542 bool 543 default y 544 545config CPU_HAS_LSX 546 bool "Support for the Loongson SIMD Extension" 547 depends on AS_HAS_LSX_EXTENSION 548 help 549 Loongson SIMD Extension (LSX) introduces 128 bit wide vector registers 550 and a set of SIMD instructions to operate on them. When this option 551 is enabled the kernel will support allocating & switching LSX 552 vector register contexts. If you know that your kernel will only be 553 running on CPUs which do not support LSX or that your userland will 554 not be making use of it then you may wish to say N here to reduce 555 the size & complexity of your kernel. 556 557 If unsure, say Y. 558 559config CPU_HAS_LASX 560 bool "Support for the Loongson Advanced SIMD Extension" 561 depends on CPU_HAS_LSX 562 depends on AS_HAS_LASX_EXTENSION 563 help 564 Loongson Advanced SIMD Extension (LASX) introduces 256 bit wide vector 565 registers and a set of SIMD instructions to operate on them. When this 566 option is enabled the kernel will support allocating & switching LASX 567 vector register contexts. If you know that your kernel will only be 568 running on CPUs which do not support LASX or that your userland will 569 not be making use of it then you may wish to say N here to reduce 570 the size & complexity of your kernel. 571 572 If unsure, say Y. 573 574config CPU_HAS_LBT 575 bool "Support for the Loongson Binary Translation Extension" 576 depends on AS_HAS_LBT_EXTENSION 577 help 578 Loongson Binary Translation (LBT) introduces 4 scratch registers (SCR0 579 to SCR3), x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop). 580 Enabling this option allows the kernel to allocate and switch registers 581 specific to LBT. 582 583 If you want to use this feature, such as the Loongson Architecture 584 Translator (LAT), say Y. 585 586config CPU_HAS_PREFETCH 587 bool 588 default y 589 590config ARCH_SUPPORTS_KEXEC 591 def_bool y 592 593config ARCH_SUPPORTS_CRASH_DUMP 594 def_bool y 595 596config ARCH_SELECTS_CRASH_DUMP 597 def_bool y 598 depends on CRASH_DUMP 599 select RELOCATABLE 600 601config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 602 def_bool CRASH_RESERVE 603 604config RELOCATABLE 605 bool "Relocatable kernel" 606 help 607 This builds the kernel as a Position Independent Executable (PIE), 608 which retains all relocation metadata required, so as to relocate 609 the kernel binary at runtime to a different virtual address from 610 its link address. 611 612config RANDOMIZE_BASE 613 bool "Randomize the address of the kernel (KASLR)" 614 depends on RELOCATABLE 615 help 616 Randomizes the physical and virtual address at which the 617 kernel image is loaded, as a security feature that 618 deters exploit attempts relying on knowledge of the location 619 of kernel internals. 620 621 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET. 622 623 If unsure, say N. 624 625config RANDOMIZE_BASE_MAX_OFFSET 626 hex "Maximum KASLR offset" if EXPERT 627 depends on RANDOMIZE_BASE 628 range 0x0 0x10000000 629 default "0x01000000" 630 help 631 When KASLR is active, this provides the maximum offset that will 632 be applied to the kernel image. It should be set according to the 633 amount of physical RAM available in the target system. 634 635 This is limited by the size of the lower address memory, 256MB. 636 637source "kernel/livepatch/Kconfig" 638 639endmenu 640 641config ARCH_SELECT_MEMORY_MODEL 642 def_bool y 643 644config ARCH_FLATMEM_ENABLE 645 def_bool y 646 depends on !NUMA 647 648config ARCH_SPARSEMEM_ENABLE 649 def_bool y 650 select SPARSEMEM_VMEMMAP_ENABLE 651 help 652 Say Y to support efficient handling of sparse physical memory, 653 for architectures which are either NUMA (Non-Uniform Memory Access) 654 or have huge holes in the physical address space for other reasons. 655 See <file:Documentation/mm/numa.rst> for more. 656 657config ARCH_MEMORY_PROBE 658 def_bool y 659 depends on MEMORY_HOTPLUG 660 661config MMU 662 bool 663 default y 664 665config ARCH_MMAP_RND_BITS_MIN 666 default 12 667 668config ARCH_MMAP_RND_BITS_MAX 669 default 18 670 671config ARCH_SUPPORTS_UPROBES 672 def_bool y 673 674config KASAN_SHADOW_OFFSET 675 hex 676 default 0x0 677 depends on KASAN 678 679menu "Power management options" 680 681config ARCH_SUSPEND_POSSIBLE 682 def_bool y 683 684config ARCH_HIBERNATION_POSSIBLE 685 def_bool y 686 687source "kernel/power/Kconfig" 688source "drivers/acpi/Kconfig" 689 690endmenu 691 692source "arch/loongarch/kvm/Kconfig" 693