1# SPDX-License-Identifier: GPL-2.0 2config LOONGARCH 3 bool 4 default y 5 select ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_MCFG if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_PPTT if ACPI 10 select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI 11 select ARCH_BINFMT_ELF_STATE 12 select ARCH_DISABLE_KASAN_INLINE 13 select ARCH_ENABLE_MEMORY_HOTPLUG 14 select ARCH_ENABLE_MEMORY_HOTREMOVE 15 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 17 select ARCH_HAS_CPU_FINALIZE_INIT 18 select ARCH_HAS_CURRENT_STACK_POINTER 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_KCOV 21 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 22 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 23 select ARCH_HAS_PTE_SPECIAL 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_INLINE_READ_LOCK if !PREEMPTION 26 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 27 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 28 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 29 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 30 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 31 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 32 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 33 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 34 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 35 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 36 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 37 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 38 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 39 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 40 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 41 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 42 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 43 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 44 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 45 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 46 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 47 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 48 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 49 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 50 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 51 select ARCH_KEEP_MEMBLOCK 52 select ARCH_MIGHT_HAVE_PC_PARPORT 53 select ARCH_MIGHT_HAVE_PC_SERIO 54 select ARCH_SPARSEMEM_ENABLE 55 select ARCH_STACKWALK 56 select ARCH_SUPPORTS_ACPI 57 select ARCH_SUPPORTS_ATOMIC_RMW 58 select ARCH_SUPPORTS_HUGETLBFS 59 select ARCH_SUPPORTS_LTO_CLANG 60 select ARCH_SUPPORTS_LTO_CLANG_THIN 61 select ARCH_SUPPORTS_NUMA_BALANCING 62 select ARCH_USE_BUILTIN_BSWAP 63 select ARCH_USE_CMPXCHG_LOCKREF 64 select ARCH_USE_QUEUED_RWLOCKS 65 select ARCH_USE_QUEUED_SPINLOCKS 66 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 67 select ARCH_WANT_LD_ORPHAN_WARN 68 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP 69 select ARCH_WANTS_NO_INSTR 70 select BUILDTIME_TABLE_SORT 71 select COMMON_CLK 72 select CPU_PM 73 select EFI 74 select GENERIC_CLOCKEVENTS 75 select GENERIC_CMOS_UPDATE 76 select GENERIC_CPU_AUTOPROBE 77 select GENERIC_CPU_DEVICES 78 select GENERIC_ENTRY 79 select GENERIC_GETTIMEOFDAY 80 select GENERIC_IOREMAP if !ARCH_IOREMAP 81 select GENERIC_IRQ_MULTI_HANDLER 82 select GENERIC_IRQ_PROBE 83 select GENERIC_IRQ_SHOW 84 select GENERIC_LIB_ASHLDI3 85 select GENERIC_LIB_ASHRDI3 86 select GENERIC_LIB_CMPDI2 87 select GENERIC_LIB_LSHRDI3 88 select GENERIC_LIB_UCMPDI2 89 select GENERIC_LIB_DEVMEM_IS_ALLOWED 90 select GENERIC_PCI_IOMAP 91 select GENERIC_SCHED_CLOCK 92 select GENERIC_SMP_IDLE_THREAD 93 select GENERIC_TIME_VSYSCALL 94 select GENERIC_VDSO_TIME_NS 95 select GPIOLIB 96 select HAS_IOPORT 97 select HAVE_ARCH_AUDITSYSCALL 98 select HAVE_ARCH_JUMP_LABEL 99 select HAVE_ARCH_JUMP_LABEL_RELATIVE 100 select HAVE_ARCH_KASAN 101 select HAVE_ARCH_KFENCE 102 select HAVE_ARCH_KGDB if PERF_EVENTS 103 select HAVE_ARCH_MMAP_RND_BITS if MMU 104 select HAVE_ARCH_SECCOMP 105 select HAVE_ARCH_SECCOMP_FILTER 106 select HAVE_ARCH_TRACEHOOK 107 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 108 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 109 select HAVE_ASM_MODVERSIONS 110 select HAVE_CONTEXT_TRACKING_USER 111 select HAVE_C_RECORDMCOUNT 112 select HAVE_DEBUG_KMEMLEAK 113 select HAVE_DEBUG_STACKOVERFLOW 114 select HAVE_DMA_CONTIGUOUS 115 select HAVE_DYNAMIC_FTRACE 116 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 117 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS 118 select HAVE_DYNAMIC_FTRACE_WITH_REGS 119 select HAVE_EBPF_JIT 120 select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN 121 select HAVE_EXIT_THREAD 122 select HAVE_FAST_GUP 123 select HAVE_FTRACE_MCOUNT_RECORD 124 select HAVE_FUNCTION_ARG_ACCESS_API 125 select HAVE_FUNCTION_ERROR_INJECTION 126 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 127 select HAVE_FUNCTION_GRAPH_TRACER 128 select HAVE_FUNCTION_TRACER 129 select HAVE_GCC_PLUGINS 130 select HAVE_GENERIC_VDSO 131 select HAVE_HW_BREAKPOINT if PERF_EVENTS 132 select HAVE_IOREMAP_PROT 133 select HAVE_IRQ_EXIT_ON_IRQ_STACK 134 select HAVE_IRQ_TIME_ACCOUNTING 135 select HAVE_KPROBES 136 select HAVE_KPROBES_ON_FTRACE 137 select HAVE_KRETPROBES 138 select HAVE_LIVEPATCH 139 select HAVE_MOD_ARCH_SPECIFIC 140 select HAVE_NMI 141 select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS 142 select HAVE_PCI 143 select HAVE_PERF_EVENTS 144 select HAVE_PERF_REGS 145 select HAVE_PERF_USER_STACK_DUMP 146 select HAVE_PREEMPT_DYNAMIC_KEY 147 select HAVE_REGS_AND_STACK_ACCESS_API 148 select HAVE_RELIABLE_STACKTRACE if UNWINDER_ORC 149 select HAVE_RETHOOK 150 select HAVE_RSEQ 151 select HAVE_RUST 152 select HAVE_SAMPLE_FTRACE_DIRECT 153 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 154 select HAVE_SETUP_PER_CPU_AREA if NUMA 155 select HAVE_STACK_VALIDATION if HAVE_OBJTOOL 156 select HAVE_STACKPROTECTOR 157 select HAVE_SYSCALL_TRACEPOINTS 158 select HAVE_TIF_NOHZ 159 select HAVE_VIRT_CPU_ACCOUNTING_GEN if !SMP 160 select IRQ_FORCED_THREADING 161 select IRQ_LOONGARCH_CPU 162 select LOCK_MM_AND_FIND_VMA 163 select MMU_GATHER_MERGE_VMAS if MMU 164 select MODULES_USE_ELF_RELA if MODULES 165 select NEED_PER_CPU_EMBED_FIRST_CHUNK 166 select NEED_PER_CPU_PAGE_FIRST_CHUNK 167 select OF 168 select OF_EARLY_FLATTREE 169 select PCI 170 select PCI_DOMAINS_GENERIC 171 select PCI_ECAM if ACPI 172 select PCI_LOONGSON 173 select PCI_MSI_ARCH_FALLBACKS 174 select PCI_QUIRKS 175 select PERF_USE_VMALLOC 176 select RTC_LIB 177 select SMP 178 select SPARSE_IRQ 179 select SYSCTL_ARCH_UNALIGN_ALLOW 180 select SYSCTL_ARCH_UNALIGN_NO_WARN 181 select SYSCTL_EXCEPTION_TRACE 182 select SWIOTLB 183 select TRACE_IRQFLAGS_SUPPORT 184 select USE_PERCPU_NUMA_NODE_ID 185 select USER_STACKTRACE_SUPPORT 186 select ZONE_DMA32 187 188config 32BIT 189 bool 190 191config 64BIT 192 def_bool y 193 194config GENERIC_BUG 195 def_bool y 196 depends on BUG 197 198config GENERIC_BUG_RELATIVE_POINTERS 199 def_bool y 200 depends on GENERIC_BUG 201 202config GENERIC_CALIBRATE_DELAY 203 def_bool y 204 205config GENERIC_CSUM 206 def_bool y 207 208config GENERIC_HWEIGHT 209 def_bool y 210 211config L1_CACHE_SHIFT 212 int 213 default "6" 214 215config LOCKDEP_SUPPORT 216 bool 217 default y 218 219config STACKTRACE_SUPPORT 220 bool 221 default y 222 223# MACH_LOONGSON32 and MACH_LOONGSON64 are deliberately carried over from the 224# MIPS Loongson code, to preserve Loongson-specific code paths in drivers that 225# are shared between architectures, and specifically expecting the symbols. 226config MACH_LOONGSON32 227 def_bool 32BIT 228 229config MACH_LOONGSON64 230 def_bool 64BIT 231 232config FIX_EARLYCON_MEM 233 def_bool y 234 235config PGTABLE_2LEVEL 236 bool 237 238config PGTABLE_3LEVEL 239 bool 240 241config PGTABLE_4LEVEL 242 bool 243 244config PGTABLE_LEVELS 245 int 246 default 2 if PGTABLE_2LEVEL 247 default 3 if PGTABLE_3LEVEL 248 default 4 if PGTABLE_4LEVEL 249 250config SCHED_OMIT_FRAME_POINTER 251 bool 252 default y 253 254config AS_HAS_EXPLICIT_RELOCS 255 def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x)) 256 257config AS_HAS_FCSR_CLASS 258 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0) 259 260config AS_HAS_LSX_EXTENSION 261 def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0) 262 263config AS_HAS_LASX_EXTENSION 264 def_bool $(as-instr,xvld \$xr0$(comma)\$a0$(comma)0) 265 266config AS_HAS_LBT_EXTENSION 267 def_bool $(as-instr,movscr2gr \$a0$(comma)\$scr0) 268 269config AS_HAS_LVZ_EXTENSION 270 def_bool $(as-instr,hvcl 0) 271 272menu "Kernel type and options" 273 274source "kernel/Kconfig.hz" 275 276choice 277 prompt "Page Table Layout" 278 default 16KB_2LEVEL if 32BIT 279 default 16KB_3LEVEL if 64BIT 280 help 281 Allows choosing the page table layout, which is a combination 282 of page size and page table levels. The size of virtual memory 283 address space are determined by the page table layout. 284 285config 4KB_3LEVEL 286 bool "4KB with 3 levels" 287 select HAVE_PAGE_SIZE_4KB 288 select PGTABLE_3LEVEL 289 help 290 This option selects 4KB page size with 3 level page tables, which 291 support a maximum of 39 bits of application virtual memory. 292 293config 4KB_4LEVEL 294 bool "4KB with 4 levels" 295 select HAVE_PAGE_SIZE_4KB 296 select PGTABLE_4LEVEL 297 help 298 This option selects 4KB page size with 4 level page tables, which 299 support a maximum of 48 bits of application virtual memory. 300 301config 16KB_2LEVEL 302 bool "16KB with 2 levels" 303 select HAVE_PAGE_SIZE_16KB 304 select PGTABLE_2LEVEL 305 help 306 This option selects 16KB page size with 2 level page tables, which 307 support a maximum of 36 bits of application virtual memory. 308 309config 16KB_3LEVEL 310 bool "16KB with 3 levels" 311 select HAVE_PAGE_SIZE_16KB 312 select PGTABLE_3LEVEL 313 help 314 This option selects 16KB page size with 3 level page tables, which 315 support a maximum of 47 bits of application virtual memory. 316 317config 64KB_2LEVEL 318 bool "64KB with 2 levels" 319 select HAVE_PAGE_SIZE_64KB 320 select PGTABLE_2LEVEL 321 help 322 This option selects 64KB page size with 2 level page tables, which 323 support a maximum of 42 bits of application virtual memory. 324 325config 64KB_3LEVEL 326 bool "64KB with 3 levels" 327 select HAVE_PAGE_SIZE_64KB 328 select PGTABLE_3LEVEL 329 help 330 This option selects 64KB page size with 3 level page tables, which 331 support a maximum of 55 bits of application virtual memory. 332 333endchoice 334 335config CMDLINE 336 string "Built-in kernel command line" 337 help 338 For most platforms, the arguments for the kernel's command line 339 are provided at run-time, during boot. However, there are cases 340 where either no arguments are being provided or the provided 341 arguments are insufficient or even invalid. 342 343 When that occurs, it is possible to define a built-in command 344 line here and choose how the kernel should use it later on. 345 346choice 347 prompt "Kernel command line type" 348 default CMDLINE_BOOTLOADER 349 help 350 Choose how the kernel will handle the provided built-in command 351 line. 352 353config CMDLINE_BOOTLOADER 354 bool "Use bootloader kernel arguments if available" 355 help 356 Prefer the command-line passed by the boot loader if available. 357 Use the built-in command line as fallback in case we get nothing 358 during boot. This is the default behaviour. 359 360config CMDLINE_EXTEND 361 bool "Use built-in to extend bootloader kernel arguments" 362 help 363 The command-line arguments provided during boot will be 364 appended to the built-in command line. This is useful in 365 cases where the provided arguments are insufficient and 366 you don't want to or cannot modify them. 367 368config CMDLINE_FORCE 369 bool "Always use the built-in kernel command string" 370 help 371 Always use the built-in command line, even if we get one during 372 boot. This is useful in case you need to override the provided 373 command line on systems where you don't have or want control 374 over it. 375 376endchoice 377 378config BUILTIN_DTB 379 bool "Enable built-in dtb in kernel" 380 depends on OF 381 help 382 Some existing systems do not provide a canonical device tree to 383 the kernel at boot time. Let's provide a device tree table in the 384 kernel, keyed by the dts filename, containing the relevant DTBs. 385 386 Built-in DTBs are generic enough and can be used as references. 387 388config BUILTIN_DTB_NAME 389 string "Source file for built-in dtb" 390 depends on BUILTIN_DTB 391 help 392 Base name (without suffix, relative to arch/loongarch/boot/dts/) 393 for the DTS file that will be used to produce the DTB linked into 394 the kernel. 395 396config DMI 397 bool "Enable DMI scanning" 398 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK 399 default y 400 help 401 This enables SMBIOS/DMI feature for systems, and scanning of 402 DMI to identify machine quirks. 403 404config EFI 405 bool "EFI runtime service support" 406 select UCS2_STRING 407 select EFI_RUNTIME_WRAPPERS 408 help 409 This enables the kernel to use EFI runtime services that are 410 available (such as the EFI variable services). 411 412config EFI_STUB 413 bool "EFI boot stub support" 414 default y 415 depends on EFI 416 select EFI_GENERIC_STUB 417 help 418 This kernel feature allows the kernel to be loaded directly by 419 EFI firmware without the use of a bootloader. 420 421config SCHED_SMT 422 bool "SMT scheduler support" 423 default y 424 help 425 Improves scheduler's performance when there are multiple 426 threads in one physical core. 427 428config SMP 429 bool "Multi-Processing support" 430 help 431 This enables support for systems with more than one CPU. If you have 432 a system with only one CPU, say N. If you have a system with more 433 than one CPU, say Y. 434 435 If you say N here, the kernel will run on uni- and multiprocessor 436 machines, but will use only one CPU of a multiprocessor machine. If 437 you say Y here, the kernel will run on many, but not all, 438 uniprocessor machines. On a uniprocessor machine, the kernel 439 will run faster if you say N here. 440 441 See also the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>. 442 443 If you don't know what to do here, say N. 444 445config HOTPLUG_CPU 446 bool "Support for hot-pluggable CPUs" 447 depends on SMP 448 select GENERIC_IRQ_MIGRATION 449 help 450 Say Y here to allow turning CPUs off and on. CPUs can be 451 controlled through /sys/devices/system/cpu. 452 (Note: power management support will enable this option 453 automatically on SMP systems. ) 454 Say N if you want to disable CPU hotplug. 455 456config NR_CPUS 457 int "Maximum number of CPUs (2-256)" 458 range 2 256 459 depends on SMP 460 default "64" 461 help 462 This allows you to specify the maximum number of CPUs which this 463 kernel will support. 464 465config NUMA 466 bool "NUMA Support" 467 select SMP 468 select ACPI_NUMA if ACPI 469 help 470 Say Y to compile the kernel with NUMA (Non-Uniform Memory Access) 471 support. This option improves performance on systems with more 472 than one NUMA node; on single node systems it is generally better 473 to leave it disabled. 474 475config NODES_SHIFT 476 int 477 default "6" 478 depends on NUMA 479 480config ARCH_FORCE_MAX_ORDER 481 int "Maximum zone order" 482 default "13" if PAGE_SIZE_64KB 483 default "11" if PAGE_SIZE_16KB 484 default "10" 485 help 486 The kernel memory allocator divides physically contiguous memory 487 blocks into "zones", where each zone is a power of two number of 488 pages. This option selects the largest power of two that the kernel 489 keeps in the memory allocator. If you need to allocate very large 490 blocks of physically contiguous memory, then you may need to 491 increase this value. 492 493 The page size is not necessarily 4KB. Keep this in mind 494 when choosing a value for this option. 495 496config ARCH_IOREMAP 497 bool "Enable LoongArch DMW-based ioremap()" 498 help 499 We use generic TLB-based ioremap() by default since it has page 500 protection support. However, you can enable LoongArch DMW-based 501 ioremap() for better performance. 502 503config ARCH_WRITECOMBINE 504 bool "Enable WriteCombine (WUC) for ioremap()" 505 help 506 LoongArch maintains cache coherency in hardware, but when paired 507 with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which 508 is similar to WriteCombine) is out of the scope of cache coherency 509 machanism for PCIe devices (this is a PCIe protocol violation, which 510 may be fixed in newer chipsets). 511 512 This means WUC can only used for write-only memory regions now, so 513 this option is disabled by default, making WUC silently fallback to 514 SUC for ioremap(). You can enable this option if the kernel is ensured 515 to run on hardware without this bug. 516 517 You can override this setting via writecombine=on/off boot parameter. 518 519config ARCH_STRICT_ALIGN 520 bool "Enable -mstrict-align to prevent unaligned accesses" if EXPERT 521 default y 522 help 523 Not all LoongArch cores support h/w unaligned access, we can use 524 -mstrict-align build parameter to prevent unaligned accesses. 525 526 CPUs with h/w unaligned access support: 527 Loongson-2K2000/2K3000/3A5000/3C5000/3D5000. 528 529 CPUs without h/w unaligned access support: 530 Loongson-2K500/2K1000. 531 532 This option is enabled by default to make the kernel be able to run 533 on all LoongArch systems. But you can disable it manually if you want 534 to run kernel only on systems with h/w unaligned access support in 535 order to optimise for performance. 536 537config CPU_HAS_FPU 538 bool 539 default y 540 541config CPU_HAS_LSX 542 bool "Support for the Loongson SIMD Extension" 543 depends on AS_HAS_LSX_EXTENSION 544 help 545 Loongson SIMD Extension (LSX) introduces 128 bit wide vector registers 546 and a set of SIMD instructions to operate on them. When this option 547 is enabled the kernel will support allocating & switching LSX 548 vector register contexts. If you know that your kernel will only be 549 running on CPUs which do not support LSX or that your userland will 550 not be making use of it then you may wish to say N here to reduce 551 the size & complexity of your kernel. 552 553 If unsure, say Y. 554 555config CPU_HAS_LASX 556 bool "Support for the Loongson Advanced SIMD Extension" 557 depends on CPU_HAS_LSX 558 depends on AS_HAS_LASX_EXTENSION 559 help 560 Loongson Advanced SIMD Extension (LASX) introduces 256 bit wide vector 561 registers and a set of SIMD instructions to operate on them. When this 562 option is enabled the kernel will support allocating & switching LASX 563 vector register contexts. If you know that your kernel will only be 564 running on CPUs which do not support LASX or that your userland will 565 not be making use of it then you may wish to say N here to reduce 566 the size & complexity of your kernel. 567 568 If unsure, say Y. 569 570config CPU_HAS_LBT 571 bool "Support for the Loongson Binary Translation Extension" 572 depends on AS_HAS_LBT_EXTENSION 573 help 574 Loongson Binary Translation (LBT) introduces 4 scratch registers (SCR0 575 to SCR3), x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop). 576 Enabling this option allows the kernel to allocate and switch registers 577 specific to LBT. 578 579 If you want to use this feature, such as the Loongson Architecture 580 Translator (LAT), say Y. 581 582config CPU_HAS_PREFETCH 583 bool 584 default y 585 586config ARCH_SUPPORTS_KEXEC 587 def_bool y 588 589config ARCH_SUPPORTS_CRASH_DUMP 590 def_bool y 591 592config ARCH_SELECTS_CRASH_DUMP 593 def_bool y 594 depends on CRASH_DUMP 595 select RELOCATABLE 596 597config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 598 def_bool CRASH_CORE 599 600config RELOCATABLE 601 bool "Relocatable kernel" 602 help 603 This builds the kernel as a Position Independent Executable (PIE), 604 which retains all relocation metadata required, so as to relocate 605 the kernel binary at runtime to a different virtual address from 606 its link address. 607 608config RANDOMIZE_BASE 609 bool "Randomize the address of the kernel (KASLR)" 610 depends on RELOCATABLE 611 help 612 Randomizes the physical and virtual address at which the 613 kernel image is loaded, as a security feature that 614 deters exploit attempts relying on knowledge of the location 615 of kernel internals. 616 617 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET. 618 619 If unsure, say N. 620 621config RANDOMIZE_BASE_MAX_OFFSET 622 hex "Maximum KASLR offset" if EXPERT 623 depends on RANDOMIZE_BASE 624 range 0x0 0x10000000 625 default "0x01000000" 626 help 627 When KASLR is active, this provides the maximum offset that will 628 be applied to the kernel image. It should be set according to the 629 amount of physical RAM available in the target system. 630 631 This is limited by the size of the lower address memory, 256MB. 632 633source "kernel/livepatch/Kconfig" 634 635endmenu 636 637config ARCH_SELECT_MEMORY_MODEL 638 def_bool y 639 640config ARCH_FLATMEM_ENABLE 641 def_bool y 642 depends on !NUMA 643 644config ARCH_SPARSEMEM_ENABLE 645 def_bool y 646 select SPARSEMEM_VMEMMAP_ENABLE 647 help 648 Say Y to support efficient handling of sparse physical memory, 649 for architectures which are either NUMA (Non-Uniform Memory Access) 650 or have huge holes in the physical address space for other reasons. 651 See <file:Documentation/mm/numa.rst> for more. 652 653config ARCH_MEMORY_PROBE 654 def_bool y 655 depends on MEMORY_HOTPLUG 656 657config MMU 658 bool 659 default y 660 661config ARCH_MMAP_RND_BITS_MIN 662 default 12 663 664config ARCH_MMAP_RND_BITS_MAX 665 default 18 666 667config ARCH_SUPPORTS_UPROBES 668 def_bool y 669 670config KASAN_SHADOW_OFFSET 671 hex 672 default 0x0 673 depends on KASAN 674 675menu "Power management options" 676 677config ARCH_SUSPEND_POSSIBLE 678 def_bool y 679 680config ARCH_HIBERNATION_POSSIBLE 681 def_bool y 682 683source "kernel/power/Kconfig" 684source "drivers/acpi/Kconfig" 685 686endmenu 687 688source "arch/loongarch/kvm/Kconfig" 689