xref: /linux/arch/loongarch/Kconfig (revision a45728fd4120011c78af1d056e571b84d47dfcc1)

# SPDX-License-Identifier: GPL-2.0
config LOONGARCH
	bool
	default y
	select ACPI
	select ACPI_GENERIC_GSI if ACPI
	select ACPI_MCFG if ACPI
	select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU
	select ACPI_PPTT if ACPI
	select ACPI_SYSTEM_POWER_STATES_SUPPORT	if ACPI
	select ARCH_BINFMT_ELF_STATE
	select ARCH_DISABLE_KASAN_INLINE
	select ARCH_ENABLE_MEMORY_HOTPLUG
	select ARCH_ENABLE_MEMORY_HOTREMOVE
	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
	select ARCH_HAS_ACPI_TABLE_UPGRADE	if ACPI
	select ARCH_HAS_CPU_FINALIZE_INIT
	select ARCH_HAS_CRC32
	select ARCH_HAS_CURRENT_STACK_POINTER
	select ARCH_HAS_DEBUG_VM_PGTABLE
	select ARCH_HAS_FAST_MULTIPLIER
	select ARCH_HAS_FORTIFY_SOURCE
	select ARCH_HAS_KCOV
	select ARCH_HAS_KERNEL_FPU_SUPPORT if CPU_HAS_FPU
	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
	select ARCH_HAS_PREEMPT_LAZY
	select ARCH_HAS_PTE_DEVMAP
	select ARCH_HAS_PTE_SPECIAL
	select ARCH_HAS_SET_MEMORY
	select ARCH_HAS_SET_DIRECT_MAP
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	select ARCH_HAS_UBSAN
	select ARCH_HAS_VDSO_ARCH_DATA
	select ARCH_INLINE_READ_LOCK if !PREEMPTION
	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
	select ARCH_KEEP_MEMBLOCK
	select ARCH_MIGHT_HAVE_PC_PARPORT
	select ARCH_MIGHT_HAVE_PC_SERIO
	select ARCH_SPARSEMEM_ENABLE
	select ARCH_STACKWALK
	select ARCH_SUPPORTS_ACPI
	select ARCH_SUPPORTS_ATOMIC_RMW
	select ARCH_SUPPORTS_HUGETLBFS
	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
	select ARCH_SUPPORTS_LTO_CLANG
	select ARCH_SUPPORTS_LTO_CLANG_THIN
	select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS
	select ARCH_SUPPORTS_NUMA_BALANCING
	select ARCH_SUPPORTS_RT
	select ARCH_USE_BUILTIN_BSWAP
	select ARCH_USE_CMPXCHG_LOCKREF
	select ARCH_USE_MEMTEST
	select ARCH_USE_QUEUED_RWLOCKS
	select ARCH_USE_QUEUED_SPINLOCKS
	select ARCH_WANT_DEFAULT_BPF_JIT
	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
	select ARCH_WANT_LD_ORPHAN_WARN
	select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
	select ARCH_WANTS_NO_INSTR
	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
	select BUILDTIME_TABLE_SORT
	select COMMON_CLK
	select CPU_PM
	select EDAC_SUPPORT
	select EFI
	select GENERIC_CLOCKEVENTS
	select GENERIC_CMOS_UPDATE
	select GENERIC_CPU_AUTOPROBE
	select GENERIC_CPU_DEVICES
	select GENERIC_CPU_VULNERABILITIES
	select GENERIC_ENTRY
	select GENERIC_GETTIMEOFDAY
	select GENERIC_IOREMAP if !ARCH_IOREMAP
	select GENERIC_IRQ_MATRIX_ALLOCATOR
	select GENERIC_IRQ_MULTI_HANDLER
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_LIB_ASHLDI3
	select GENERIC_LIB_ASHRDI3
	select GENERIC_LIB_CMPDI2
	select GENERIC_LIB_LSHRDI3
	select GENERIC_LIB_UCMPDI2
	select GENERIC_LIB_DEVMEM_IS_ALLOWED
	select GENERIC_PCI_IOMAP
	select GENERIC_SCHED_CLOCK
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_TIME_VSYSCALL
	select GENERIC_VDSO_DATA_STORE
	select GENERIC_VDSO_TIME_NS
	select GPIOLIB
	select HAS_IOPORT
	select HAVE_ARCH_AUDITSYSCALL
	select HAVE_ARCH_JUMP_LABEL
	select HAVE_ARCH_JUMP_LABEL_RELATIVE
	select HAVE_ARCH_KASAN
	select HAVE_ARCH_KFENCE
	select HAVE_ARCH_KGDB if PERF_EVENTS
	select HAVE_ARCH_MMAP_RND_BITS if MMU
	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
	select HAVE_ARCH_SECCOMP
	select HAVE_ARCH_SECCOMP_FILTER
	select HAVE_ARCH_STACKLEAK
	select HAVE_ARCH_TRACEHOOK
	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
	select HAVE_ASM_MODVERSIONS
	select HAVE_CONTEXT_TRACKING_USER
	select HAVE_C_RECORDMCOUNT
	select HAVE_DEBUG_KMEMLEAK
	select HAVE_DEBUG_STACKOVERFLOW
	select HAVE_DMA_CONTIGUOUS
	select HAVE_DYNAMIC_FTRACE
	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
	select HAVE_FTRACE_REGS_HAVING_PT_REGS
	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS
	select HAVE_DYNAMIC_FTRACE_WITH_REGS
	select HAVE_EBPF_JIT
	select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN
	select HAVE_EXIT_THREAD
	select HAVE_GUP_FAST
	select HAVE_FTRACE_GRAPH_FUNC
	select HAVE_FTRACE_MCOUNT_RECORD
	select HAVE_FUNCTION_ARG_ACCESS_API
	select HAVE_FUNCTION_ERROR_INJECTION
	select HAVE_FUNCTION_GRAPH_FREGS
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_FUNCTION_TRACER
	select HAVE_GCC_PLUGINS
	select HAVE_GENERIC_VDSO
	select HAVE_HW_BREAKPOINT if PERF_EVENTS
	select HAVE_IOREMAP_PROT
	select HAVE_IRQ_EXIT_ON_IRQ_STACK
	select HAVE_IRQ_TIME_ACCOUNTING
	select HAVE_KPROBES
	select HAVE_KPROBES_ON_FTRACE
	select HAVE_KRETPROBES
	select HAVE_LIVEPATCH
	select HAVE_MOD_ARCH_SPECIFIC
	select HAVE_NMI
	select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB
	select HAVE_PCI
	select HAVE_PERF_EVENTS
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
	select HAVE_PREEMPT_DYNAMIC_KEY
	select HAVE_REGS_AND_STACK_ACCESS_API
	select HAVE_RELIABLE_STACKTRACE if UNWINDER_ORC
	select HAVE_RETHOOK
	select HAVE_RSEQ
	select HAVE_RUST
	select HAVE_SAMPLE_FTRACE_DIRECT
	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
	select HAVE_SETUP_PER_CPU_AREA if NUMA
	select HAVE_STACK_VALIDATION if HAVE_OBJTOOL
	select HAVE_STACKPROTECTOR
	select HAVE_SYSCALL_TRACEPOINTS
	select HAVE_TIF_NOHZ
	select HAVE_VIRT_CPU_ACCOUNTING_GEN
	select IRQ_FORCED_THREADING
	select IRQ_LOONGARCH_CPU
	select LOCK_MM_AND_FIND_VMA
	select MMU_GATHER_MERGE_VMAS if MMU
	select MODULES_USE_ELF_RELA if MODULES
	select NEED_PER_CPU_EMBED_FIRST_CHUNK
	select NEED_PER_CPU_PAGE_FIRST_CHUNK
	select OF
	select OF_EARLY_FLATTREE
	select PCI
	select PCI_DOMAINS_GENERIC
	select PCI_ECAM if ACPI
	select PCI_LOONGSON
	select PCI_MSI_ARCH_FALLBACKS
	select PCI_QUIRKS
	select PERF_USE_VMALLOC
	select RTC_LIB
	select SPARSE_IRQ
	select SYSCTL_ARCH_UNALIGN_ALLOW
	select SYSCTL_ARCH_UNALIGN_NO_WARN
	select SYSCTL_EXCEPTION_TRACE
	select SWIOTLB
	select TRACE_IRQFLAGS_SUPPORT
	select USE_PERCPU_NUMA_NODE_ID
	select USER_STACKTRACE_SUPPORT
	select VDSO_GETRANDOM
	select ZONE_DMA32

config 32BIT
	bool

config 64BIT
	def_bool y

config GENERIC_BUG
	def_bool y
	depends on BUG

config GENERIC_BUG_RELATIVE_POINTERS
	def_bool y
	depends on GENERIC_BUG

config GENERIC_CALIBRATE_DELAY
	def_bool y

config GENERIC_CSUM
	def_bool y

config GENERIC_HWEIGHT
	def_bool y

config L1_CACHE_SHIFT
	int
	default "6"

config LOCKDEP_SUPPORT
	bool
	default y

config STACKTRACE_SUPPORT
	bool
	default y

# MACH_LOONGSON32 and MACH_LOONGSON64 are deliberately carried over from the
# MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
# are shared between architectures, and specifically expecting the symbols.
config MACH_LOONGSON32
	def_bool 32BIT

config MACH_LOONGSON64
	def_bool 64BIT

config FIX_EARLYCON_MEM
	def_bool !ARCH_IOREMAP

config PGTABLE_2LEVEL
	bool

config PGTABLE_3LEVEL
	bool

config PGTABLE_4LEVEL
	bool

config PGTABLE_LEVELS
	int
	default 2 if PGTABLE_2LEVEL
	default 3 if PGTABLE_3LEVEL
	default 4 if PGTABLE_4LEVEL

config SCHED_OMIT_FRAME_POINTER
	bool
	default y

config AS_HAS_EXPLICIT_RELOCS
	def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))

config AS_HAS_FCSR_CLASS
	def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)

config AS_HAS_THIN_ADD_SUB
	def_bool $(cc-option,-Wa$(comma)-mthin-add-sub) || AS_IS_LLVM

config AS_HAS_LSX_EXTENSION
	def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0)

config AS_HAS_LASX_EXTENSION
	def_bool $(as-instr,xvld \$xr0$(comma)\$a0$(comma)0)

config AS_HAS_LBT_EXTENSION
	def_bool $(as-instr,movscr2gr \$a0$(comma)\$scr0)

config AS_HAS_LVZ_EXTENSION
	def_bool $(as-instr,hvcl 0)

config CC_HAS_ANNOTATE_TABLEJUMP
	def_bool $(cc-option,-mannotate-tablejump)

menu "Kernel type and options"

source "kernel/Kconfig.hz"

choice
	prompt "Page Table Layout"
	default 16KB_2LEVEL if 32BIT
	default 16KB_3LEVEL if 64BIT
	help
	  Allows choosing the page table layout, which is a combination
	  of page size and page table levels. The size of virtual memory
	  address space are determined by the page table layout.

config 4KB_3LEVEL
	bool "4KB with 3 levels"
	select HAVE_PAGE_SIZE_4KB
	select PGTABLE_3LEVEL
	help
	  This option selects 4KB page size with 3 level page tables, which
	  support a maximum of 39 bits of application virtual memory.

config 4KB_4LEVEL
	bool "4KB with 4 levels"
	select HAVE_PAGE_SIZE_4KB
	select PGTABLE_4LEVEL
	help
	  This option selects 4KB page size with 4 level page tables, which
	  support a maximum of 48 bits of application virtual memory.

config 16KB_2LEVEL
	bool "16KB with 2 levels"
	select HAVE_PAGE_SIZE_16KB
	select PGTABLE_2LEVEL
	help
	  This option selects 16KB page size with 2 level page tables, which
	  support a maximum of 36 bits of application virtual memory.

config 16KB_3LEVEL
	bool "16KB with 3 levels"
	select HAVE_PAGE_SIZE_16KB
	select PGTABLE_3LEVEL
	help
	  This option selects 16KB page size with 3 level page tables, which
	  support a maximum of 47 bits of application virtual memory.

config 64KB_2LEVEL
	bool "64KB with 2 levels"
	select HAVE_PAGE_SIZE_64KB
	select PGTABLE_2LEVEL
	help
	  This option selects 64KB page size with 2 level page tables, which
	  support a maximum of 42 bits of application virtual memory.

config 64KB_3LEVEL
	bool "64KB with 3 levels"
	select HAVE_PAGE_SIZE_64KB
	select PGTABLE_3LEVEL
	help
	  This option selects 64KB page size with 3 level page tables, which
	  support a maximum of 55 bits of application virtual memory.

endchoice

config CMDLINE
	string "Built-in kernel command line"
	help
	  For most platforms, the arguments for the kernel's command line
	  are provided at run-time, during boot. However, there are cases
	  where either no arguments are being provided or the provided
	  arguments are insufficient or even invalid.

	  When that occurs, it is possible to define a built-in command
	  line here and choose how the kernel should use it later on.

choice
	prompt "Kernel command line type"
	default CMDLINE_BOOTLOADER
	help
	  Choose how the kernel will handle the provided built-in command
	  line.

config CMDLINE_BOOTLOADER
	bool "Use bootloader kernel arguments if available"
	help
	  Prefer the command-line passed by the boot loader if available.
	  Use the built-in command line as fallback in case we get nothing
	  during boot. This is the default behaviour.

config CMDLINE_EXTEND
	bool "Use built-in to extend bootloader kernel arguments"
	help
	  The built-in command line will be appended to the command-
	  line arguments provided during boot. This is useful in
	  cases where the provided arguments are insufficient and
	  you don't want to or cannot modify them.

config CMDLINE_FORCE
	bool "Always use the built-in kernel command string"
	help
	  Always use the built-in command line, even if we get one during
	  boot. This is useful in case you need to override the provided
	  command line on systems where you don't have or want control
	  over it.

endchoice

config BUILTIN_DTB
	bool "Enable built-in dtb in kernel"
	depends on OF
	select GENERIC_BUILTIN_DTB
	help
	  Some existing systems do not provide a canonical device tree to
	  the kernel at boot time. Let's provide a device tree table in the
	  kernel, keyed by the dts filename, containing the relevant DTBs.

	  Built-in DTBs are generic enough and can be used as references.

config BUILTIN_DTB_NAME
	string "Source file for built-in dtb"
	depends on BUILTIN_DTB
	help
	  Base name (without suffix, relative to arch/loongarch/boot/dts/)
	  for the DTS file that will be used to produce the DTB linked into
	  the kernel.

config DMI
	bool "Enable DMI scanning"
	select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
	default y
	help
	  This enables SMBIOS/DMI feature for systems, and scanning of
	  DMI to identify machine quirks.

config EFI
	bool "EFI runtime service support"
	select UCS2_STRING
	select EFI_RUNTIME_WRAPPERS
	help
	  This enables the kernel to use EFI runtime services that are
	  available (such as the EFI variable services).

config EFI_STUB
	bool "EFI boot stub support"
	default y
	depends on EFI
	select EFI_GENERIC_STUB
	help
	  This kernel feature allows the kernel to be loaded directly by
	  EFI firmware without the use of a bootloader.

config SCHED_SMT
	bool "SMT scheduler support"
	depends on SMP
	default y
	help
	  Improves scheduler's performance when there are multiple
	  threads in one physical core.

config SCHED_MC
	bool "Multi-core scheduler support"
	depends on SMP
	default y
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places.

config SMP
	bool "Multi-Processing support"
	help
	  This enables support for systems with more than one CPU. If you have
	  a system with only one CPU, say N. If you have a system with more
	  than one CPU, say Y.

	  If you say N here, the kernel will run on uni- and multiprocessor
	  machines, but will use only one CPU of a multiprocessor machine. If
	  you say Y here, the kernel will run on many, but not all,
	  uniprocessor machines. On a uniprocessor machine, the kernel
	  will run faster if you say N here.

	  See also the SMP-HOWTO available at <http://www.tldp.org/docs.html#howto>.

	  If you don't know what to do here, say N.

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP
	select GENERIC_IRQ_MIGRATION
	help
	  Say Y here to allow turning CPUs off and on. CPUs can be
	  controlled through /sys/devices/system/cpu.
	  (Note: power management support will enable this option
	    automatically on SMP systems. )
	  Say N if you want to disable CPU hotplug.

config NR_CPUS
	int "Maximum number of CPUs (2-256)"
	range 2 256
	depends on SMP
	default "64"
	help
	  This allows you to specify the maximum number of CPUs which this
	  kernel will support.

config NUMA
	bool "NUMA Support"
	select SMP
	help
	  Say Y to compile the kernel with NUMA (Non-Uniform Memory Access)
	  support.  This option improves performance on systems with more
	  than one NUMA node; on single node systems it is generally better
	  to leave it disabled.

config NODES_SHIFT
	int
	default "6"
	depends on NUMA

config ARCH_FORCE_MAX_ORDER
	int "Maximum zone order"
	default "13" if PAGE_SIZE_64KB
	default "11" if PAGE_SIZE_16KB
	default "10"
	help
	  The kernel memory allocator divides physically contiguous memory
	  blocks into "zones", where each zone is a power of two number of
	  pages.  This option selects the largest power of two that the kernel
	  keeps in the memory allocator.  If you need to allocate very large
	  blocks of physically contiguous memory, then you may need to
	  increase this value.

	  The page size is not necessarily 4KB.  Keep this in mind
	  when choosing a value for this option.

config ARCH_IOREMAP
	bool "Enable LoongArch DMW-based ioremap()"
	help
	  We use generic TLB-based ioremap() by default since it has page
	  protection support. However, you can enable LoongArch DMW-based
	  ioremap() for better performance.

config ARCH_WRITECOMBINE
	bool "Enable WriteCombine (WUC) for ioremap()"
	help
	  LoongArch maintains cache coherency in hardware, but when paired
	  with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which
	  is similar to WriteCombine) is out of the scope of cache coherency
	  machanism for PCIe devices (this is a PCIe protocol violation, which
	  may be fixed in newer chipsets).

	  This means WUC can only used for write-only memory regions now, so
	  this option is disabled by default, making WUC silently fallback to
	  SUC for ioremap(). You can enable this option if the kernel is ensured
	  to run on hardware without this bug.

	  You can override this setting via writecombine=on/off boot parameter.

config ARCH_STRICT_ALIGN
	bool "Enable -mstrict-align to prevent unaligned accesses" if EXPERT
	default y
	help
	  Not all LoongArch cores support h/w unaligned access, we can use
	  -mstrict-align build parameter to prevent unaligned accesses.

	  CPUs with h/w unaligned access support:
	  Loongson-2K2000/2K3000/3A5000/3C5000/3D5000.

	  CPUs without h/w unaligned access support:
	  Loongson-2K500/2K1000.

	  This option is enabled by default to make the kernel be able to run
	  on all LoongArch systems. But you can disable it manually if you want
	  to run kernel only on systems with h/w unaligned access support in
	  order to optimise for performance.

config CPU_HAS_FPU
	bool
	default y

config CPU_HAS_LSX
	bool "Support for the Loongson SIMD Extension"
	depends on AS_HAS_LSX_EXTENSION
	help
	  Loongson SIMD Extension (LSX) introduces 128 bit wide vector registers
	  and a set of SIMD instructions to operate on them. When this option
	  is enabled the kernel will support allocating & switching LSX
	  vector register contexts. If you know that your kernel will only be
	  running on CPUs which do not support LSX or that your userland will
	  not be making use of it then you may wish to say N here to reduce
	  the size & complexity of your kernel.

	  If unsure, say Y.

config CPU_HAS_LASX
	bool "Support for the Loongson Advanced SIMD Extension"
	depends on CPU_HAS_LSX
	depends on AS_HAS_LASX_EXTENSION
	help
	  Loongson Advanced SIMD Extension (LASX) introduces 256 bit wide vector
	  registers and a set of SIMD instructions to operate on them. When this
	  option is enabled the kernel will support allocating & switching LASX
	  vector register contexts. If you know that your kernel will only be
	  running on CPUs which do not support LASX or that your userland will
	  not be making use of it then you may wish to say N here to reduce
	  the size & complexity of your kernel.

	  If unsure, say Y.

config CPU_HAS_LBT
	bool "Support for the Loongson Binary Translation Extension"
	depends on AS_HAS_LBT_EXTENSION
	help
	  Loongson Binary Translation (LBT) introduces 4 scratch registers (SCR0
	  to SCR3), x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop).
	  Enabling this option allows the kernel to allocate and switch registers
	  specific to LBT.

	  If you want to use this feature, such as the Loongson Architecture
	  Translator (LAT), say Y.

config CPU_HAS_PREFETCH
	bool
	default y

config ARCH_SUPPORTS_KEXEC
	def_bool y

config ARCH_SUPPORTS_CRASH_DUMP
	def_bool y

config ARCH_DEFAULT_CRASH_DUMP
	def_bool y

config ARCH_SELECTS_CRASH_DUMP
	def_bool y
	depends on CRASH_DUMP
	select RELOCATABLE

config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
	def_bool CRASH_RESERVE

config RELOCATABLE
	bool "Relocatable kernel"
	select ARCH_HAS_RELR
	help
	  This builds the kernel as a Position Independent Executable (PIE),
	  which retains all relocation metadata required, so as to relocate
	  the kernel binary at runtime to a different virtual address from
	  its link address.

config RANDOMIZE_BASE
	bool "Randomize the address of the kernel (KASLR)"
	depends on RELOCATABLE
	help
	   Randomizes the physical and virtual address at which the
	   kernel image is loaded, as a security feature that
	   deters exploit attempts relying on knowledge of the location
	   of kernel internals.

	   The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.

	   If unsure, say N.

config RANDOMIZE_BASE_MAX_OFFSET
	hex "Maximum KASLR offset" if EXPERT
	depends on RANDOMIZE_BASE
	range 0x0 0x10000000
	default "0x01000000"
	help
	  When KASLR is active, this provides the maximum offset that will
	  be applied to the kernel image. It should be set according to the
	  amount of physical RAM available in the target system.

	  This is limited by the size of the lower address memory, 256MB.

source "kernel/livepatch/Kconfig"

config PARAVIRT
	bool "Enable paravirtualization code"
	depends on AS_HAS_LVZ_EXTENSION
	help
	  This changes the kernel so it can modify itself when it is run
	  under a hypervisor, potentially improving performance significantly
	  over full virtualization.  However, when run without a hypervisor
	  the kernel is theoretically slower and slightly larger.

config PARAVIRT_TIME_ACCOUNTING
	bool "Paravirtual steal time accounting"
	depends on PARAVIRT
	help
	  Select this option to enable fine granularity task steal time
	  accounting. Time spent executing other tasks in parallel with
	  the current vCPU is discounted from the vCPU power. To account for
	  that, there can be a small performance impact.

	  If in doubt, say N here.

endmenu

config ARCH_SELECT_MEMORY_MODEL
	def_bool y

config ARCH_FLATMEM_ENABLE
	def_bool y
	depends on !NUMA

config ARCH_SPARSEMEM_ENABLE
	def_bool y
	select SPARSEMEM_VMEMMAP_ENABLE
	help
	  Say Y to support efficient handling of sparse physical memory,
	  for architectures which are either NUMA (Non-Uniform Memory Access)
	  or have huge holes in the physical address space for other reasons.
	  See <file:Documentation/mm/numa.rst> for more.

config ARCH_MEMORY_PROBE
	def_bool y
	depends on MEMORY_HOTPLUG

config MMU
	bool
	default y

config ARCH_MMAP_RND_BITS_MIN
	default 12

config ARCH_MMAP_RND_BITS_MAX
	default 18

config ARCH_SUPPORTS_UPROBES
	def_bool y

config KASAN_SHADOW_OFFSET
	hex
	default 0x0
	depends on KASAN

menu "Power management options"

config ARCH_SUSPEND_POSSIBLE
	def_bool y

config ARCH_HIBERNATION_POSSIBLE
	def_bool y

source "kernel/power/Kconfig"
source "drivers/acpi/Kconfig"
source "drivers/cpufreq/Kconfig"

endmenu

source "arch/loongarch/kvm/Kconfig"