1 /* 2 * DMA implementation for Hexagon 3 * 4 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 18 * 02110-1301, USA. 19 */ 20 21 #include <linux/dma-mapping.h> 22 #include <linux/bootmem.h> 23 #include <linux/genalloc.h> 24 #include <asm/dma-mapping.h> 25 26 struct dma_map_ops *dma_ops; 27 EXPORT_SYMBOL(dma_ops); 28 29 int bad_dma_address; /* globals are automatically initialized to zero */ 30 31 int dma_supported(struct device *dev, u64 mask) 32 { 33 if (mask == DMA_BIT_MASK(32)) 34 return 1; 35 else 36 return 0; 37 } 38 EXPORT_SYMBOL(dma_supported); 39 40 int dma_set_mask(struct device *dev, u64 mask) 41 { 42 if (!dev->dma_mask || !dma_supported(dev, mask)) 43 return -EIO; 44 45 *dev->dma_mask = mask; 46 47 return 0; 48 } 49 EXPORT_SYMBOL(dma_set_mask); 50 51 static struct gen_pool *coherent_pool; 52 53 54 /* Allocates from a pool of uncached memory that was reserved at boot time */ 55 56 void *hexagon_dma_alloc_coherent(struct device *dev, size_t size, 57 dma_addr_t *dma_addr, gfp_t flag, 58 struct dma_attrs *attrs) 59 { 60 void *ret; 61 62 if (coherent_pool == NULL) { 63 coherent_pool = gen_pool_create(PAGE_SHIFT, -1); 64 65 if (coherent_pool == NULL) 66 panic("Can't create %s() memory pool!", __func__); 67 else 68 gen_pool_add(coherent_pool, 69 (PAGE_OFFSET + (max_low_pfn << PAGE_SHIFT)), 70 hexagon_coherent_pool_size, -1); 71 } 72 73 ret = (void *) gen_pool_alloc(coherent_pool, size); 74 75 if (ret) { 76 memset(ret, 0, size); 77 *dma_addr = (dma_addr_t) (ret - PAGE_OFFSET); 78 } else 79 *dma_addr = ~0; 80 81 return ret; 82 } 83 84 static void hexagon_free_coherent(struct device *dev, size_t size, void *vaddr, 85 dma_addr_t dma_addr, struct dma_attrs *attrs) 86 { 87 gen_pool_free(coherent_pool, (unsigned long) vaddr, size); 88 } 89 90 static int check_addr(const char *name, struct device *hwdev, 91 dma_addr_t bus, size_t size) 92 { 93 if (hwdev && hwdev->dma_mask && !dma_capable(hwdev, bus, size)) { 94 if (*hwdev->dma_mask >= DMA_BIT_MASK(32)) 95 printk(KERN_ERR 96 "%s: overflow %Lx+%zu of device mask %Lx\n", 97 name, (long long)bus, size, 98 (long long)*hwdev->dma_mask); 99 return 0; 100 } 101 return 1; 102 } 103 104 static int hexagon_map_sg(struct device *hwdev, struct scatterlist *sg, 105 int nents, enum dma_data_direction dir, 106 struct dma_attrs *attrs) 107 { 108 struct scatterlist *s; 109 int i; 110 111 WARN_ON(nents == 0 || sg[0].length == 0); 112 113 for_each_sg(sg, s, nents, i) { 114 s->dma_address = sg_phys(s); 115 if (!check_addr("map_sg", hwdev, s->dma_address, s->length)) 116 return 0; 117 118 s->dma_length = s->length; 119 120 flush_dcache_range(PAGE_OFFSET + s->dma_address, 121 PAGE_OFFSET + s->dma_address + s->length); 122 } 123 124 return nents; 125 } 126 127 /* 128 * address is virtual 129 */ 130 static inline void dma_sync(void *addr, size_t size, 131 enum dma_data_direction dir) 132 { 133 switch (dir) { 134 case DMA_TO_DEVICE: 135 hexagon_clean_dcache_range((unsigned long) addr, 136 (unsigned long) addr + size); 137 break; 138 case DMA_FROM_DEVICE: 139 hexagon_inv_dcache_range((unsigned long) addr, 140 (unsigned long) addr + size); 141 break; 142 case DMA_BIDIRECTIONAL: 143 flush_dcache_range((unsigned long) addr, 144 (unsigned long) addr + size); 145 break; 146 default: 147 BUG(); 148 } 149 } 150 151 static inline void *dma_addr_to_virt(dma_addr_t dma_addr) 152 { 153 return phys_to_virt((unsigned long) dma_addr); 154 } 155 156 /** 157 * hexagon_map_page() - maps an address for device DMA 158 * @dev: pointer to DMA device 159 * @page: pointer to page struct of DMA memory 160 * @offset: offset within page 161 * @size: size of memory to map 162 * @dir: transfer direction 163 * @attrs: pointer to DMA attrs (not used) 164 * 165 * Called to map a memory address to a DMA address prior 166 * to accesses to/from device. 167 * 168 * We don't particularly have many hoops to jump through 169 * so far. Straight translation between phys and virtual. 170 * 171 * DMA is not cache coherent so sync is necessary; this 172 * seems to be a convenient place to do it. 173 * 174 */ 175 static dma_addr_t hexagon_map_page(struct device *dev, struct page *page, 176 unsigned long offset, size_t size, 177 enum dma_data_direction dir, 178 struct dma_attrs *attrs) 179 { 180 dma_addr_t bus = page_to_phys(page) + offset; 181 WARN_ON(size == 0); 182 183 if (!check_addr("map_single", dev, bus, size)) 184 return bad_dma_address; 185 186 dma_sync(dma_addr_to_virt(bus), size, dir); 187 188 return bus; 189 } 190 191 static void hexagon_sync_single_for_cpu(struct device *dev, 192 dma_addr_t dma_handle, size_t size, 193 enum dma_data_direction dir) 194 { 195 dma_sync(dma_addr_to_virt(dma_handle), size, dir); 196 } 197 198 static void hexagon_sync_single_for_device(struct device *dev, 199 dma_addr_t dma_handle, size_t size, 200 enum dma_data_direction dir) 201 { 202 dma_sync(dma_addr_to_virt(dma_handle), size, dir); 203 } 204 205 struct dma_map_ops hexagon_dma_ops = { 206 .alloc = hexagon_dma_alloc_coherent, 207 .free = hexagon_free_coherent, 208 .map_sg = hexagon_map_sg, 209 .map_page = hexagon_map_page, 210 .sync_single_for_cpu = hexagon_sync_single_for_cpu, 211 .sync_single_for_device = hexagon_sync_single_for_device, 212 .is_phys = 1, 213 }; 214 215 void __init hexagon_dma_init(void) 216 { 217 if (dma_ops) 218 return; 219 220 dma_ops = &hexagon_dma_ops; 221 } 222