1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Page table support for the Hexagon architecture 4 * 5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _ASM_PGTABLE_H 9 #define _ASM_PGTABLE_H 10 11 /* 12 * Page table definitions for Qualcomm Hexagon processor. 13 */ 14 #include <asm/page.h> 15 #include <asm-generic/pgtable-nopmd.h> 16 17 /* 18 * The PTE model described here is that of the Hexagon Virtual Machine, 19 * which autonomously walks 2-level page tables. At a lower level, we 20 * also describe the RISCish software-loaded TLB entry structure of 21 * the underlying Hexagon processor. A kernel built to run on the 22 * virtual machine has no need to know about the underlying hardware. 23 */ 24 #include <asm/vm_mmu.h> 25 26 /* 27 * To maximize the comfort level for the PTE manipulation macros, 28 * define the "well known" architecture-specific bits. 29 */ 30 #define _PAGE_READ __HVM_PTE_R 31 #define _PAGE_WRITE __HVM_PTE_W 32 #define _PAGE_EXECUTE __HVM_PTE_X 33 #define _PAGE_USER __HVM_PTE_U 34 35 /* 36 * We have a total of 4 "soft" bits available in the abstract PTE. 37 * The two mandatory software bits are Dirty and Accessed. 38 * To make nonlinear swap work according to the more recent 39 * model, we want a low order "Present" bit to indicate whether 40 * the PTE describes MMU programming or swap space. 41 */ 42 #define _PAGE_PRESENT (1<<0) 43 #define _PAGE_DIRTY (1<<1) 44 #define _PAGE_ACCESSED (1<<2) 45 46 /* 47 * For now, let's say that Valid and Present are the same thing. 48 * Alternatively, we could say that it's the "or" of R, W, and X 49 * permissions. 50 */ 51 #define _PAGE_VALID _PAGE_PRESENT 52 53 /* 54 * We're not defining _PAGE_GLOBAL here, since there's no concept 55 * of global pages or ASIDs exposed to the Hexagon Virtual Machine, 56 * and we want to use the same page table structures and macros in 57 * the native kernel as we do in the virtual machine kernel. 58 * So we'll put up with a bit of inefficiency for now... 59 */ 60 61 /* We borrow bit 6 to store the exclusive marker in swap PTEs. */ 62 #define _PAGE_SWP_EXCLUSIVE (1<<6) 63 64 /* 65 * Top "FOURTH" level (pgd), which for the Hexagon VM is really 66 * only the second from the bottom, pgd and pud both being collapsed. 67 * Each entry represents 4MB of virtual address space, 4K of table 68 * thus maps the full 4GB. 69 */ 70 #define PGDIR_SHIFT 22 71 #define PTRS_PER_PGD 1024 72 73 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 74 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 75 76 #ifdef CONFIG_PAGE_SIZE_4KB 77 #define PTRS_PER_PTE 1024 78 #endif 79 80 #ifdef CONFIG_PAGE_SIZE_16KB 81 #define PTRS_PER_PTE 256 82 #endif 83 84 #ifdef CONFIG_PAGE_SIZE_64KB 85 #define PTRS_PER_PTE 64 86 #endif 87 88 #ifdef CONFIG_PAGE_SIZE_256KB 89 #define PTRS_PER_PTE 16 90 #endif 91 92 #ifdef CONFIG_PAGE_SIZE_1MB 93 #define PTRS_PER_PTE 4 94 #endif 95 96 /* Any bigger and the PTE disappears. */ 97 #define pgd_ERROR(e) \ 98 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__,\ 99 pgd_val(e)) 100 101 /* 102 * Page Protection Constants. Includes (in this variant) cache attributes. 103 */ 104 extern unsigned long _dflt_cache_att; 105 106 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 107 _dflt_cache_att) 108 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 109 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att) 110 #define PAGE_COPY PAGE_READONLY 111 #define PAGE_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 112 _PAGE_READ | _PAGE_EXECUTE | _dflt_cache_att) 113 #define PAGE_COPY_EXEC PAGE_EXEC 114 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | \ 115 _PAGE_EXECUTE | _PAGE_WRITE | _dflt_cache_att) 116 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 117 _PAGE_WRITE | _PAGE_EXECUTE | _dflt_cache_att) 118 119 120 /* 121 * Aliases for mapping mmap() protection bits to page protections. 122 * These get used for static initialization, so using the _dflt_cache_att 123 * variable for the default cache attribute isn't workable. If the 124 * default gets changed at boot time, the boot option code has to 125 * update data structures like the protaction_map[] array. 126 */ 127 #define CACHEDEF (CACHE_DEFAULT << 6) 128 129 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* located in head.S */ 130 131 /* HUGETLB not working currently */ 132 #ifdef CONFIG_HUGETLB_PAGE 133 #define pte_mkhuge(pte) __pte((pte_val(pte) & ~0x3) | HVM_HUGEPAGE_SIZE) 134 #endif 135 136 /* 137 * For now, assume that higher-level code will do TLB/MMU invalidations 138 * and don't insert that overhead into this low-level function. 139 */ 140 extern void sync_icache_dcache(pte_t pte); 141 142 #define pte_present_exec_user(pte) \ 143 ((pte_val(pte) & (_PAGE_EXECUTE | _PAGE_USER)) == \ 144 (_PAGE_EXECUTE | _PAGE_USER)) 145 146 static inline void set_pte(pte_t *ptep, pte_t pteval) 147 { 148 /* should really be using pte_exec, if it weren't declared later. */ 149 if (pte_present_exec_user(pteval)) 150 sync_icache_dcache(pteval); 151 152 *ptep = pteval; 153 } 154 155 /* 156 * For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid 157 * L1 PTE (PMD/PGD) has 7 in the least significant bits. For the L2 PTE 158 * (Linux PTE), the key is to have bits 11..9 all zero. We'd use 0x7 159 * as a universal null entry, but some of those least significant bits 160 * are interpreted by software. 161 */ 162 #define _NULL_PMD 0x7 163 #define _NULL_PTE 0x0 164 165 static inline void pmd_clear(pmd_t *pmd_entry_ptr) 166 { 167 pmd_val(*pmd_entry_ptr) = _NULL_PMD; 168 } 169 170 /* 171 * Conveniently, a null PTE value is invalid. 172 */ 173 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 174 pte_t *ptep) 175 { 176 pte_val(*ptep) = _NULL_PTE; 177 } 178 179 /** 180 * pmd_none - check if pmd_entry is mapped 181 * @pmd_entry: pmd entry 182 * 183 * MIPS checks it against that "invalid pte table" thing. 184 */ 185 static inline int pmd_none(pmd_t pmd) 186 { 187 return pmd_val(pmd) == _NULL_PMD; 188 } 189 190 /** 191 * pmd_present - is there a page table behind this? 192 * Essentially the inverse of pmd_none. We maybe 193 * save an inline instruction by defining it this 194 * way, instead of simply "!pmd_none". 195 */ 196 static inline int pmd_present(pmd_t pmd) 197 { 198 return pmd_val(pmd) != (unsigned long)_NULL_PMD; 199 } 200 201 /** 202 * pmd_bad - check if a PMD entry is "bad". That might mean swapped out. 203 * As we have no known cause of badness, it's null, as it is for many 204 * architectures. 205 */ 206 static inline int pmd_bad(pmd_t pmd) 207 { 208 return 0; 209 } 210 211 /* 212 * pmd_pfn - converts a PMD entry to a page frame number 213 */ 214 #define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT) 215 216 /* 217 * pmd_page - converts a PMD entry to a page pointer 218 */ 219 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) 220 221 /** 222 * pte_none - check if pte is mapped 223 * @pte: pte_t entry 224 */ 225 static inline int pte_none(pte_t pte) 226 { 227 return pte_val(pte) == _NULL_PTE; 228 }; 229 230 /* 231 * pte_present - check if page is present 232 */ 233 static inline int pte_present(pte_t pte) 234 { 235 return pte_val(pte) & _PAGE_PRESENT; 236 } 237 238 /* pte_page - returns a page (frame pointer/descriptor?) based on a PTE */ 239 #define pte_page(x) pfn_to_page(pte_pfn(x)) 240 241 /* pte_mkold - mark PTE as not recently accessed */ 242 static inline pte_t pte_mkold(pte_t pte) 243 { 244 pte_val(pte) &= ~_PAGE_ACCESSED; 245 return pte; 246 } 247 248 /* pte_mkyoung - mark PTE as recently accessed */ 249 static inline pte_t pte_mkyoung(pte_t pte) 250 { 251 pte_val(pte) |= _PAGE_ACCESSED; 252 return pte; 253 } 254 255 /* pte_mkclean - mark page as in sync with backing store */ 256 static inline pte_t pte_mkclean(pte_t pte) 257 { 258 pte_val(pte) &= ~_PAGE_DIRTY; 259 return pte; 260 } 261 262 /* pte_mkdirty - mark page as modified */ 263 static inline pte_t pte_mkdirty(pte_t pte) 264 { 265 pte_val(pte) |= _PAGE_DIRTY; 266 return pte; 267 } 268 269 /* pte_young - "is PTE marked as accessed"? */ 270 static inline int pte_young(pte_t pte) 271 { 272 return pte_val(pte) & _PAGE_ACCESSED; 273 } 274 275 /* pte_dirty - "is PTE dirty?" */ 276 static inline int pte_dirty(pte_t pte) 277 { 278 return pte_val(pte) & _PAGE_DIRTY; 279 } 280 281 /* pte_modify - set protection bits on PTE */ 282 static inline pte_t pte_modify(pte_t pte, pgprot_t prot) 283 { 284 pte_val(pte) &= PAGE_MASK; 285 pte_val(pte) |= pgprot_val(prot); 286 return pte; 287 } 288 289 /* pte_wrprotect - mark page as not writable */ 290 static inline pte_t pte_wrprotect(pte_t pte) 291 { 292 pte_val(pte) &= ~_PAGE_WRITE; 293 return pte; 294 } 295 296 /* pte_mkwrite - mark page as writable */ 297 static inline pte_t pte_mkwrite_novma(pte_t pte) 298 { 299 pte_val(pte) |= _PAGE_WRITE; 300 return pte; 301 } 302 303 /* pte_mkexec - mark PTE as executable */ 304 static inline pte_t pte_mkexec(pte_t pte) 305 { 306 pte_val(pte) |= _PAGE_EXECUTE; 307 return pte; 308 } 309 310 /* pte_read - "is PTE marked as readable?" */ 311 static inline int pte_read(pte_t pte) 312 { 313 return pte_val(pte) & _PAGE_READ; 314 } 315 316 /* pte_write - "is PTE marked as writable?" */ 317 static inline int pte_write(pte_t pte) 318 { 319 return pte_val(pte) & _PAGE_WRITE; 320 } 321 322 323 /* pte_exec - "is PTE marked as executable?" */ 324 static inline int pte_exec(pte_t pte) 325 { 326 return pte_val(pte) & _PAGE_EXECUTE; 327 } 328 329 /* __pte_to_swp_entry - extract swap entry from PTE */ 330 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 331 332 /* __swp_entry_to_pte - extract PTE from swap entry */ 333 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 334 335 #define PFN_PTE_SHIFT PAGE_SHIFT 336 /* pfn_pte - convert page number and protection value to page table entry */ 337 #define pfn_pte(pfn, pgprot) __pte((pfn << PAGE_SHIFT) | pgprot_val(pgprot)) 338 339 /* pte_pfn - convert pte to page frame number */ 340 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 341 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval)) 342 343 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 344 { 345 return (unsigned long)__va(pmd_val(pmd) & PAGE_MASK); 346 } 347 348 /* 349 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 350 * are !pte_none() && !pte_present(). 351 * 352 * Swap/file PTE definitions. If _PAGE_PRESENT is zero, the rest of the PTE is 353 * interpreted as swap information. The remaining free bits are interpreted as 354 * listed below. Rather than have the TLB fill handler test 355 * _PAGE_PRESENT, we're going to reserve the permissions bits and set them to 356 * all zeros for swap entries, which speeds up the miss handler at the cost of 357 * 3 bits of offset. That trade-off can be revisited if necessary, but Hexagon 358 * processor architecture and target applications suggest a lot of TLB misses 359 * and not much swap space. 360 * 361 * Format of swap PTE: 362 * bit 0: Present (zero) 363 * bits 1-5: swap type (arch independent layer uses 5 bits max) 364 * bit 6: exclusive marker 365 * bits 7-9: bits 2:0 of offset 366 * bits 10-12: effectively _PAGE_PROTNONE (all zero) 367 * bits 13-31: bits 21:3 of swap offset 368 * 369 * The split offset makes some of the following macros a little gnarly, 370 * but there's plenty of precedent for this sort of thing. 371 */ 372 373 /* Used for swap PTEs */ 374 #define __swp_type(swp_pte) (((swp_pte).val >> 1) & 0x1f) 375 376 #define __swp_offset(swp_pte) \ 377 ((((swp_pte).val >> 7) & 0x7) | (((swp_pte).val >> 10) & 0x3ffff8)) 378 379 #define __swp_entry(type, offset) \ 380 ((swp_entry_t) { \ 381 (((type & 0x1f) << 1) | \ 382 ((offset & 0x3ffff8) << 10) | ((offset & 0x7) << 7)) }) 383 384 static inline bool pte_swp_exclusive(pte_t pte) 385 { 386 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 387 } 388 389 static inline pte_t pte_swp_mkexclusive(pte_t pte) 390 { 391 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE; 392 return pte; 393 } 394 395 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 396 { 397 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE; 398 return pte; 399 } 400 401 #endif 402