1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_BARRIER_H 5 #define __ASM_CSKY_BARRIER_H 6 7 #ifndef __ASSEMBLY__ 8 9 #define nop() asm volatile ("nop\n":::"memory") 10 11 #ifdef CONFIG_SMP 12 13 /* 14 * bar.brwarws: ordering barrier for all load/store instructions 15 * before/after 16 * 17 * |31|30 26|25 21|20 16|15 10|9 5|4 0| 18 * 1 10000 00000 00000 100001 00001 0 bw br aw ar 19 * 20 * b: before 21 * a: after 22 * r: read 23 * w: write 24 * 25 * Here are all combinations: 26 * 27 * bar.brw 28 * bar.br 29 * bar.bw 30 * bar.arw 31 * bar.ar 32 * bar.aw 33 * bar.brwarw 34 * bar.brarw 35 * bar.bwarw 36 * bar.brwar 37 * bar.brwaw 38 * bar.brar 39 * bar.bwaw 40 */ 41 #define __bar_brw() asm volatile (".long 0x842cc000\n":::"memory") 42 #define __bar_br() asm volatile (".long 0x8424c000\n":::"memory") 43 #define __bar_bw() asm volatile (".long 0x8428c000\n":::"memory") 44 #define __bar_arw() asm volatile (".long 0x8423c000\n":::"memory") 45 #define __bar_ar() asm volatile (".long 0x8421c000\n":::"memory") 46 #define __bar_aw() asm volatile (".long 0x8422c000\n":::"memory") 47 #define __bar_brwarw() asm volatile (".long 0x842fc000\n":::"memory") 48 #define __bar_brarw() asm volatile (".long 0x8427c000\n":::"memory") 49 #define __bar_bwarw() asm volatile (".long 0x842bc000\n":::"memory") 50 #define __bar_brwar() asm volatile (".long 0x842dc000\n":::"memory") 51 #define __bar_brwaw() asm volatile (".long 0x842ec000\n":::"memory") 52 #define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory") 53 #define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory") 54 #define __bar_bwaw() asm volatile (".long 0x842ac000\n":::"memory") 55 56 #define __smp_mb() __bar_brwarw() 57 #define __smp_rmb() __bar_brar() 58 #define __smp_wmb() __bar_bwaw() 59 60 #define ACQUIRE_FENCE ".long 0x8427c000\n" 61 #define __smp_acquire_fence() __bar_brarw() 62 #define __smp_release_fence() __bar_brwaw() 63 64 #endif /* CONFIG_SMP */ 65 66 /* 67 * sync: completion barrier, all sync.xx instructions 68 * guarantee the last response recieved by bus transaction 69 * made by ld/st instructions before sync.s 70 * sync.s: inherit from sync, but also shareable to other cores 71 * sync.i: inherit from sync, but also flush cpu pipeline 72 * sync.is: the same with sync.i + sync.s 73 */ 74 #define mb() asm volatile ("sync\n":::"memory") 75 76 #ifdef CONFIG_CPU_HAS_CACHEV2 77 /* 78 * Using three sync.is to prevent speculative PTW 79 */ 80 #define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory") 81 #endif 82 83 #include <asm-generic/barrier.h> 84 85 #endif /* __ASSEMBLY__ */ 86 #endif /* __ASM_CSKY_BARRIER_H */ 87