1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_ENTRY_H 5 #define __ASM_CSKY_ENTRY_H 6 7 #include <asm/setup.h> 8 #include <abi/regdef.h> 9 10 #define LSAVE_PC 8 11 #define LSAVE_PSR 12 12 #define LSAVE_A0 24 13 #define LSAVE_A1 28 14 #define LSAVE_A2 32 15 #define LSAVE_A3 36 16 17 #define EPC_INCREASE 4 18 #define EPC_KEEP 0 19 20 #define KSPTOUSP 21 #define USPTOKSP 22 23 #define usp cr<14, 1> 24 25 .macro INCTRAP rx 26 addi \rx, EPC_INCREASE 27 .endm 28 29 .macro SAVE_ALL epc_inc 30 subi sp, 152 31 stw tls, (sp, 0) 32 stw lr, (sp, 4) 33 34 mfcr lr, epc 35 movi tls, \epc_inc 36 add lr, tls 37 stw lr, (sp, 8) 38 39 mfcr lr, epsr 40 stw lr, (sp, 12) 41 mfcr lr, usp 42 stw lr, (sp, 16) 43 44 stw a0, (sp, 20) 45 stw a0, (sp, 24) 46 stw a1, (sp, 28) 47 stw a2, (sp, 32) 48 stw a3, (sp, 36) 49 50 addi sp, 40 51 stm r4-r13, (sp) 52 53 addi sp, 40 54 stm r16-r30, (sp) 55 #ifdef CONFIG_CPU_HAS_HILO 56 mfhi lr 57 stw lr, (sp, 60) 58 mflo lr 59 stw lr, (sp, 64) 60 mfcr lr, cr14 61 stw lr, (sp, 68) 62 #endif 63 subi sp, 80 64 .endm 65 66 .macro RESTORE_ALL 67 psrclr ie 68 ldw tls, (sp, 0) 69 ldw lr, (sp, 4) 70 ldw a0, (sp, 8) 71 mtcr a0, epc 72 ldw a0, (sp, 12) 73 mtcr a0, epsr 74 ldw a0, (sp, 16) 75 mtcr a0, usp 76 77 #ifdef CONFIG_CPU_HAS_HILO 78 ldw a0, (sp, 140) 79 mthi a0 80 ldw a0, (sp, 144) 81 mtlo a0 82 ldw a0, (sp, 148) 83 mtcr a0, cr14 84 #endif 85 86 ldw a0, (sp, 24) 87 ldw a1, (sp, 28) 88 ldw a2, (sp, 32) 89 ldw a3, (sp, 36) 90 91 addi sp, 40 92 ldm r4-r13, (sp) 93 addi sp, 40 94 ldm r16-r30, (sp) 95 addi sp, 72 96 rte 97 .endm 98 99 .macro SAVE_SWITCH_STACK 100 subi sp, 64 101 stm r4-r11, (sp) 102 stw lr, (sp, 32) 103 stw r16, (sp, 36) 104 stw r17, (sp, 40) 105 stw r26, (sp, 44) 106 stw r27, (sp, 48) 107 stw r28, (sp, 52) 108 stw r29, (sp, 56) 109 stw r30, (sp, 60) 110 #ifdef CONFIG_CPU_HAS_HILO 111 subi sp, 16 112 mfhi lr 113 stw lr, (sp, 0) 114 mflo lr 115 stw lr, (sp, 4) 116 mfcr lr, cr14 117 stw lr, (sp, 8) 118 #endif 119 .endm 120 121 .macro RESTORE_SWITCH_STACK 122 #ifdef CONFIG_CPU_HAS_HILO 123 ldw lr, (sp, 0) 124 mthi lr 125 ldw lr, (sp, 4) 126 mtlo lr 127 ldw lr, (sp, 8) 128 mtcr lr, cr14 129 addi sp, 16 130 #endif 131 ldm r4-r11, (sp) 132 ldw lr, (sp, 32) 133 ldw r16, (sp, 36) 134 ldw r17, (sp, 40) 135 ldw r26, (sp, 44) 136 ldw r27, (sp, 48) 137 ldw r28, (sp, 52) 138 ldw r29, (sp, 56) 139 ldw r30, (sp, 60) 140 addi sp, 64 141 .endm 142 143 /* MMU registers operators. */ 144 .macro RD_MIR rx 145 mfcr \rx, cr<0, 15> 146 .endm 147 148 .macro RD_MEH rx 149 mfcr \rx, cr<4, 15> 150 .endm 151 152 .macro RD_MCIR rx 153 mfcr \rx, cr<8, 15> 154 .endm 155 156 .macro RD_PGDR rx 157 mfcr \rx, cr<29, 15> 158 .endm 159 160 .macro RD_PGDR_K rx 161 mfcr \rx, cr<28, 15> 162 .endm 163 164 .macro WR_MEH rx 165 mtcr \rx, cr<4, 15> 166 .endm 167 168 .macro WR_MCIR rx 169 mtcr \rx, cr<8, 15> 170 .endm 171 172 .macro SETUP_MMU rx 173 lrw \rx, PHYS_OFFSET | 0xe 174 mtcr \rx, cr<30, 15> 175 lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe 176 mtcr \rx, cr<31, 15> 177 .endm 178 #endif /* __ASM_CSKY_ENTRY_H */ 179