1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_CKMMUV2_H 5 #define __ASM_CSKY_CKMMUV2_H 6 7 #include <abi/reg_ops.h> 8 #include <asm/barrier.h> 9 10 static inline int read_mmu_index(void) 11 { 12 return mfcr("cr<0, 15>"); 13 } 14 15 static inline void write_mmu_index(int value) 16 { 17 mtcr("cr<0, 15>", value); 18 } 19 20 static inline int read_mmu_entrylo0(void) 21 { 22 return mfcr("cr<2, 15>"); 23 } 24 25 static inline int read_mmu_entrylo1(void) 26 { 27 return mfcr("cr<3, 15>"); 28 } 29 30 static inline void write_mmu_pagemask(int value) 31 { 32 mtcr("cr<6, 15>", value); 33 } 34 35 static inline int read_mmu_entryhi(void) 36 { 37 return mfcr("cr<4, 15>"); 38 } 39 40 static inline void write_mmu_entryhi(int value) 41 { 42 mtcr("cr<4, 15>", value); 43 } 44 45 static inline unsigned long read_mmu_msa0(void) 46 { 47 return mfcr("cr<30, 15>"); 48 } 49 50 static inline void write_mmu_msa0(unsigned long value) 51 { 52 mtcr("cr<30, 15>", value); 53 } 54 55 static inline unsigned long read_mmu_msa1(void) 56 { 57 return mfcr("cr<31, 15>"); 58 } 59 60 static inline void write_mmu_msa1(unsigned long value) 61 { 62 mtcr("cr<31, 15>", value); 63 } 64 65 /* 66 * TLB operations. 67 */ 68 static inline void tlb_probe(void) 69 { 70 mtcr("cr<8, 15>", 0x80000000); 71 } 72 73 static inline void tlb_read(void) 74 { 75 mtcr("cr<8, 15>", 0x40000000); 76 } 77 78 static inline void tlb_invalid_all(void) 79 { 80 #ifdef CONFIG_CPU_HAS_TLBI 81 asm volatile("tlbi.alls\n":::"memory"); 82 sync_is(); 83 #else 84 mtcr("cr<8, 15>", 0x04000000); 85 #endif 86 } 87 88 static inline void tlb_invalid_indexed(void) 89 { 90 mtcr("cr<8, 15>", 0x02000000); 91 } 92 93 static inline void setup_pgd(unsigned long pgd, bool kernel) 94 { 95 if (kernel) 96 mtcr("cr<28, 15>", pgd | BIT(0)); 97 else 98 mtcr("cr<29, 15>", pgd | BIT(0)); 99 } 100 101 static inline unsigned long get_pgd(void) 102 { 103 return mfcr("cr<29, 15>") & ~BIT(0); 104 } 105 #endif /* __ASM_CSKY_CKMMUV2_H */ 106