1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler for ARM64 4 * 5 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "bpf_jit: " fmt 9 10 #include <linux/arm-smccc.h> 11 #include <linux/bitfield.h> 12 #include <linux/bpf.h> 13 #include <linux/cfi.h> 14 #include <linux/filter.h> 15 #include <linux/memory.h> 16 #include <linux/printk.h> 17 #include <linux/slab.h> 18 19 #include <asm/asm-extable.h> 20 #include <asm/byteorder.h> 21 #include <asm/cpufeature.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/insn.h> 24 #include <asm/text-patching.h> 25 #include <asm/set_memory.h> 26 27 #include "bpf_jit.h" 28 29 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 30 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 31 #define TCCNT_PTR (MAX_BPF_JIT_REG + 2) 32 #define TMP_REG_3 (MAX_BPF_JIT_REG + 3) 33 #define PRIVATE_SP (MAX_BPF_JIT_REG + 4) 34 #define ARENA_VM_START (MAX_BPF_JIT_REG + 5) 35 36 #define check_imm(bits, imm) do { \ 37 if ((((imm) > 0) && ((imm) >> ((bits) - 1))) || \ 38 (((imm) < 0) && (~(imm) >> ((bits) - 1)))) { \ 39 pr_info("[%2d] imm=%d(0x%x) out of range\n", \ 40 i, imm, imm); \ 41 return -EINVAL; \ 42 } \ 43 } while (0) 44 #define check_imm19(imm) check_imm(19, imm) 45 #define check_imm26(imm) check_imm(26, imm) 46 47 /* Map BPF registers to A64 registers */ 48 static const int bpf2a64[] = { 49 /* return value from in-kernel function, and exit value from eBPF */ 50 [BPF_REG_0] = A64_R(8), 51 /* arguments from eBPF program to in-kernel function */ 52 [BPF_REG_1] = A64_R(0), 53 [BPF_REG_2] = A64_R(1), 54 [BPF_REG_3] = A64_R(2), 55 [BPF_REG_4] = A64_R(3), 56 [BPF_REG_5] = A64_R(4), 57 /* callee saved registers that in-kernel function will preserve */ 58 [BPF_REG_6] = A64_R(19), 59 [BPF_REG_7] = A64_R(20), 60 [BPF_REG_8] = A64_R(21), 61 [BPF_REG_9] = A64_R(22), 62 /* read-only frame pointer to access stack */ 63 [BPF_REG_FP] = A64_R(25), 64 /* temporary registers for BPF JIT */ 65 [TMP_REG_1] = A64_R(10), 66 [TMP_REG_2] = A64_R(11), 67 [TMP_REG_3] = A64_R(12), 68 /* tail_call_cnt_ptr */ 69 [TCCNT_PTR] = A64_R(26), 70 /* temporary register for blinding constants */ 71 [BPF_REG_AX] = A64_R(9), 72 /* callee saved register for private stack pointer */ 73 [PRIVATE_SP] = A64_R(27), 74 /* callee saved register for kern_vm_start address */ 75 [ARENA_VM_START] = A64_R(28), 76 }; 77 78 struct jit_ctx { 79 const struct bpf_prog *prog; 80 int idx; 81 int epilogue_offset; 82 int *offset; 83 int exentry_idx; 84 int nr_used_callee_reg; 85 u8 used_callee_reg[8]; /* r6~r9, fp, arena_vm_start */ 86 __le32 *image; 87 __le32 *ro_image; 88 u32 stack_size; 89 u16 stack_arg_size; 90 u64 user_vm_start; 91 u64 arena_vm_start; 92 bool fp_used; 93 bool priv_sp_used; 94 bool write; 95 }; 96 97 struct bpf_plt { 98 u32 insn_ldr; /* load target */ 99 u32 insn_br; /* branch to target */ 100 u64 target; /* target value */ 101 }; 102 103 #define PLT_TARGET_SIZE sizeof_field(struct bpf_plt, target) 104 #define PLT_TARGET_OFFSET offsetof(struct bpf_plt, target) 105 106 /* Memory size/value to protect private stack overflow/underflow */ 107 #define PRIV_STACK_GUARD_SZ 16 108 #define PRIV_STACK_GUARD_VAL 0xEB9F12345678eb9fULL 109 110 static inline void emit(const u32 insn, struct jit_ctx *ctx) 111 { 112 if (ctx->image != NULL && ctx->write) 113 ctx->image[ctx->idx] = cpu_to_le32(insn); 114 115 ctx->idx++; 116 } 117 118 static inline void emit_u32_data(const u32 data, struct jit_ctx *ctx) 119 { 120 if (ctx->image != NULL && ctx->write) 121 ctx->image[ctx->idx] = (__force __le32)data; 122 123 ctx->idx++; 124 } 125 126 static inline void emit_a64_mov_i(const int is64, const int reg, 127 const s32 val, struct jit_ctx *ctx) 128 { 129 u16 hi = val >> 16; 130 u16 lo = val & 0xffff; 131 132 if (hi & 0x8000) { 133 if (hi == 0xffff) { 134 emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx); 135 } else { 136 emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx); 137 if (lo != 0xffff) 138 emit(A64_MOVK(is64, reg, lo, 0), ctx); 139 } 140 } else { 141 emit(A64_MOVZ(is64, reg, lo, 0), ctx); 142 if (hi) 143 emit(A64_MOVK(is64, reg, hi, 16), ctx); 144 } 145 } 146 147 static int i64_i16_blocks(const u64 val, bool inverse) 148 { 149 return (((val >> 0) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 150 (((val >> 16) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 151 (((val >> 32) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 152 (((val >> 48) & 0xffff) != (inverse ? 0xffff : 0x0000)); 153 } 154 155 static inline void emit_a64_mov_i64(const int reg, const u64 val, 156 struct jit_ctx *ctx) 157 { 158 u64 nrm_tmp = val, rev_tmp = ~val; 159 bool inverse; 160 int shift; 161 162 if (!(nrm_tmp >> 32)) 163 return emit_a64_mov_i(0, reg, (u32)val, ctx); 164 165 inverse = i64_i16_blocks(nrm_tmp, true) < i64_i16_blocks(nrm_tmp, false); 166 shift = max(round_down((inverse ? (fls64(rev_tmp) - 1) : 167 (fls64(nrm_tmp) - 1)), 16), 0); 168 if (inverse) 169 emit(A64_MOVN(1, reg, (rev_tmp >> shift) & 0xffff, shift), ctx); 170 else 171 emit(A64_MOVZ(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); 172 shift -= 16; 173 while (shift >= 0) { 174 if (((nrm_tmp >> shift) & 0xffff) != (inverse ? 0xffff : 0x0000)) 175 emit(A64_MOVK(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); 176 shift -= 16; 177 } 178 } 179 180 static inline void emit_bti(u32 insn, struct jit_ctx *ctx) 181 { 182 if (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL)) 183 emit(insn, ctx); 184 } 185 186 static inline void emit_kcfi(u32 hash, struct jit_ctx *ctx) 187 { 188 if (IS_ENABLED(CONFIG_CFI)) 189 emit_u32_data(hash, ctx); 190 } 191 192 /* 193 * Kernel addresses in the vmalloc space use at most 48 bits, and the 194 * remaining bits are guaranteed to be 0x1. So we can compose the address 195 * with a fixed length movn/movk/movk sequence. 196 */ 197 static inline void emit_addr_mov_i64(const int reg, const u64 val, 198 struct jit_ctx *ctx) 199 { 200 u64 tmp = val; 201 int shift = 0; 202 203 emit(A64_MOVN(1, reg, ~tmp & 0xffff, shift), ctx); 204 while (shift < 32) { 205 tmp >>= 16; 206 shift += 16; 207 emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx); 208 } 209 } 210 211 static bool should_emit_indirect_call(long target, const struct jit_ctx *ctx) 212 { 213 long offset; 214 215 /* when ctx->ro_image is not allocated or the target is unknown, 216 * emit indirect call 217 */ 218 if (!ctx->ro_image || !target) 219 return true; 220 221 offset = target - (long)&ctx->ro_image[ctx->idx]; 222 return offset < -SZ_128M || offset >= SZ_128M; 223 } 224 225 static void emit_direct_call(u64 target, struct jit_ctx *ctx) 226 { 227 u32 insn; 228 unsigned long pc; 229 230 pc = (unsigned long)&ctx->ro_image[ctx->idx]; 231 insn = aarch64_insn_gen_branch_imm(pc, target, AARCH64_INSN_BRANCH_LINK); 232 emit(insn, ctx); 233 } 234 235 static void emit_indirect_call(u64 target, struct jit_ctx *ctx) 236 { 237 u8 tmp; 238 239 tmp = bpf2a64[TMP_REG_1]; 240 emit_addr_mov_i64(tmp, target, ctx); 241 emit(A64_BLR(tmp), ctx); 242 } 243 244 static void emit_call(u64 target, struct jit_ctx *ctx) 245 { 246 if (should_emit_indirect_call((long)target, ctx)) 247 emit_indirect_call(target, ctx); 248 else 249 emit_direct_call(target, ctx); 250 } 251 252 static inline int bpf2a64_offset(int bpf_insn, int off, 253 const struct jit_ctx *ctx) 254 { 255 /* BPF JMP offset is relative to the next instruction */ 256 bpf_insn++; 257 /* 258 * Whereas arm64 branch instructions encode the offset 259 * from the branch itself, so we must subtract 1 from the 260 * instruction offset. 261 */ 262 return ctx->offset[bpf_insn + off] - (ctx->offset[bpf_insn] - 1); 263 } 264 265 static void jit_fill_hole(void *area, unsigned int size) 266 { 267 __le32 *ptr; 268 /* We are guaranteed to have aligned memory. */ 269 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) 270 *ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT); 271 } 272 273 int bpf_arch_text_invalidate(void *dst, size_t len) 274 { 275 if (!aarch64_insn_set(dst, AARCH64_BREAK_FAULT, len)) 276 return -EINVAL; 277 278 return 0; 279 } 280 281 static inline int epilogue_offset(const struct jit_ctx *ctx) 282 { 283 int to = ctx->epilogue_offset; 284 int from = ctx->idx; 285 286 return to - from; 287 } 288 289 static bool is_addsub_imm(u32 imm) 290 { 291 /* Either imm12 or shifted imm12. */ 292 return !(imm & ~0xfff) || !(imm & ~0xfff000); 293 } 294 295 static inline void emit_a64_add_i(const bool is64, const int dst, const int src, 296 const int tmp, const s32 imm, struct jit_ctx *ctx) 297 { 298 if (is_addsub_imm(imm)) { 299 emit(A64_ADD_I(is64, dst, src, imm), ctx); 300 } else if (is_addsub_imm(-(u32)imm)) { 301 emit(A64_SUB_I(is64, dst, src, -imm), ctx); 302 } else { 303 emit_a64_mov_i(is64, tmp, imm, ctx); 304 emit(A64_ADD(is64, dst, src, tmp), ctx); 305 } 306 } 307 308 /* 309 * There are 3 types of AArch64 LDR/STR (immediate) instruction: 310 * Post-index, Pre-index, Unsigned offset. 311 * 312 * For BPF ldr/str, the "unsigned offset" type is sufficient. 313 * 314 * "Unsigned offset" type LDR(immediate) format: 315 * 316 * 3 2 1 0 317 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 318 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 319 * |x x|1 1 1 0 0 1 0 1| imm12 | Rn | Rt | 320 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 321 * scale 322 * 323 * "Unsigned offset" type STR(immediate) format: 324 * 3 2 1 0 325 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 326 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 327 * |x x|1 1 1 0 0 1 0 0| imm12 | Rn | Rt | 328 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 329 * scale 330 * 331 * The offset is calculated from imm12 and scale in the following way: 332 * 333 * offset = (u64)imm12 << scale 334 */ 335 static bool is_lsi_offset(int offset, int scale) 336 { 337 if (offset < 0) 338 return false; 339 340 if (offset > (0xFFF << scale)) 341 return false; 342 343 if (offset & ((1 << scale) - 1)) 344 return false; 345 346 return true; 347 } 348 349 /* generated main prog prologue: 350 * bti c // if CONFIG_ARM64_BTI_KERNEL 351 * mov x9, lr 352 * nop // POKE_OFFSET 353 * paciasp // if CONFIG_ARM64_PTR_AUTH_KERNEL 354 * stp x29, lr, [sp, #-16]! 355 * mov x29, sp 356 * stp xzr, x26, [sp, #-16]! 357 * mov x26, sp 358 * // PROLOGUE_OFFSET 359 * // save callee-saved registers 360 */ 361 static void prepare_bpf_tail_call_cnt(struct jit_ctx *ctx) 362 { 363 const bool is_main_prog = !bpf_is_subprog(ctx->prog); 364 const u8 ptr = bpf2a64[TCCNT_PTR]; 365 366 if (is_main_prog) { 367 /* Initialize tail_call_cnt. */ 368 emit(A64_PUSH(A64_ZR, ptr, A64_SP), ctx); 369 emit(A64_MOV(1, ptr, A64_SP), ctx); 370 } else 371 emit(A64_PUSH(ptr, ptr, A64_SP), ctx); 372 } 373 374 static void find_used_callee_regs(struct jit_ctx *ctx) 375 { 376 int i; 377 const struct bpf_prog *prog = ctx->prog; 378 const struct bpf_insn *insn = &prog->insnsi[0]; 379 int reg_used = 0; 380 381 for (i = 0; i < prog->len; i++, insn++) { 382 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 383 reg_used |= 1; 384 385 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 386 reg_used |= 2; 387 388 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 389 reg_used |= 4; 390 391 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 392 reg_used |= 8; 393 394 if (insn->dst_reg == BPF_REG_FP || insn->src_reg == BPF_REG_FP) { 395 ctx->fp_used = true; 396 reg_used |= 16; 397 } 398 } 399 400 i = 0; 401 if (reg_used & 1) 402 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_6]; 403 404 if (reg_used & 2) 405 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_7]; 406 407 if (reg_used & 4) 408 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_8]; 409 410 if (reg_used & 8) 411 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_9]; 412 413 if (reg_used & 16) { 414 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_FP]; 415 if (ctx->priv_sp_used) 416 ctx->used_callee_reg[i++] = bpf2a64[PRIVATE_SP]; 417 } 418 419 if (ctx->arena_vm_start) 420 ctx->used_callee_reg[i++] = bpf2a64[ARENA_VM_START]; 421 422 ctx->nr_used_callee_reg = i; 423 } 424 425 /* Save callee-saved registers */ 426 static void push_callee_regs(struct jit_ctx *ctx) 427 { 428 int reg1, reg2, i; 429 430 /* 431 * Program acting as exception boundary should save all ARM64 432 * Callee-saved registers as the exception callback needs to recover 433 * all ARM64 Callee-saved registers in its epilogue. 434 */ 435 if (ctx->prog->aux->exception_boundary) { 436 emit(A64_PUSH(A64_R(19), A64_R(20), A64_SP), ctx); 437 emit(A64_PUSH(A64_R(21), A64_R(22), A64_SP), ctx); 438 emit(A64_PUSH(A64_R(23), A64_R(24), A64_SP), ctx); 439 emit(A64_PUSH(A64_R(25), A64_R(26), A64_SP), ctx); 440 emit(A64_PUSH(A64_R(27), A64_R(28), A64_SP), ctx); 441 ctx->fp_used = true; 442 } else { 443 find_used_callee_regs(ctx); 444 for (i = 0; i + 1 < ctx->nr_used_callee_reg; i += 2) { 445 reg1 = ctx->used_callee_reg[i]; 446 reg2 = ctx->used_callee_reg[i + 1]; 447 emit(A64_PUSH(reg1, reg2, A64_SP), ctx); 448 } 449 if (i < ctx->nr_used_callee_reg) { 450 reg1 = ctx->used_callee_reg[i]; 451 /* keep SP 16-byte aligned */ 452 emit(A64_PUSH(reg1, A64_ZR, A64_SP), ctx); 453 } 454 } 455 } 456 457 /* Restore callee-saved registers */ 458 static void pop_callee_regs(struct jit_ctx *ctx) 459 { 460 struct bpf_prog_aux *aux = ctx->prog->aux; 461 int reg1, reg2, i; 462 463 /* 464 * Program acting as exception boundary pushes R23 and R24 in addition 465 * to BPF callee-saved registers. Exception callback uses the boundary 466 * program's stack frame, so recover these extra registers in the above 467 * two cases. 468 */ 469 if (aux->exception_boundary || aux->exception_cb) { 470 emit(A64_POP(A64_R(27), A64_R(28), A64_SP), ctx); 471 emit(A64_POP(A64_R(25), A64_R(26), A64_SP), ctx); 472 emit(A64_POP(A64_R(23), A64_R(24), A64_SP), ctx); 473 emit(A64_POP(A64_R(21), A64_R(22), A64_SP), ctx); 474 emit(A64_POP(A64_R(19), A64_R(20), A64_SP), ctx); 475 } else { 476 i = ctx->nr_used_callee_reg - 1; 477 if (ctx->nr_used_callee_reg % 2 != 0) { 478 reg1 = ctx->used_callee_reg[i]; 479 emit(A64_POP(reg1, A64_ZR, A64_SP), ctx); 480 i--; 481 } 482 while (i > 0) { 483 reg1 = ctx->used_callee_reg[i - 1]; 484 reg2 = ctx->used_callee_reg[i]; 485 emit(A64_POP(reg1, reg2, A64_SP), ctx); 486 i -= 2; 487 } 488 } 489 } 490 491 static void emit_percpu_ptr(const u8 dst_reg, void __percpu *ptr, 492 struct jit_ctx *ctx) 493 { 494 const u8 tmp = bpf2a64[TMP_REG_1]; 495 496 emit_a64_mov_i64(dst_reg, (__force const u64)ptr, ctx); 497 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) 498 emit(A64_MRS_TPIDR_EL2(tmp), ctx); 499 else 500 emit(A64_MRS_TPIDR_EL1(tmp), ctx); 501 emit(A64_ADD(1, dst_reg, dst_reg, tmp), ctx); 502 } 503 504 #define BTI_INSNS (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) ? 1 : 0) 505 #define PAC_INSNS (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL) ? 1 : 0) 506 507 /* Offset of nop instruction in bpf prog entry to be poked */ 508 #define POKE_OFFSET (BTI_INSNS + 1) 509 510 /* Tail call offset to jump into */ 511 #define PROLOGUE_OFFSET (BTI_INSNS + 2 + PAC_INSNS + 4) 512 513 static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) 514 { 515 const struct bpf_prog *prog = ctx->prog; 516 const bool is_main_prog = !bpf_is_subprog(prog); 517 const u8 fp = bpf2a64[BPF_REG_FP]; 518 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 519 const u8 priv_sp = bpf2a64[PRIVATE_SP]; 520 void __percpu *priv_stack_ptr; 521 int cur_offset; 522 523 /* 524 * BPF prog stack layout 525 * 526 * high 527 * original A64_SP => 0:+-----+ BPF prologue 528 * |FP/LR| 529 * current A64_FP => -16:+-----+ 530 * | ... | callee saved registers 531 * BPF fp register => -64:+-----+ <= (BPF_FP) 532 * | | 533 * | ... | BPF prog stack 534 * | | 535 * +-----+ <= (BPF_FP - prog->aux->stack_depth) 536 * |RSVD | padding 537 * +-----+ <= (BPF_FP - ctx->stack_size) 538 * | | 539 * | ... | outgoing stack args (9+, if any) 540 * | | 541 * current A64_SP => +-----+ 542 * | | 543 * | ... | Function call stack 544 * | | 545 * +-----+ 546 * low 547 * 548 * Stack args 6-8 are passed in x5-x7, args 9+ at [SP]. 549 * Incoming args 9+ are at [A64_FP + 16], [A64_FP + 24], ... 550 * (above the saved FP/LR pair pushed in the callee prologue). 551 */ 552 553 emit_kcfi(is_main_prog ? cfi_bpf_hash : cfi_bpf_subprog_hash, ctx); 554 const int idx0 = ctx->idx; 555 556 /* bpf function may be invoked by 3 instruction types: 557 * 1. bl, attached via freplace to bpf prog via short jump 558 * 2. br, attached via freplace to bpf prog via long jump 559 * 3. blr, working as a function pointer, used by emit_call. 560 * So BTI_JC should used here to support both br and blr. 561 */ 562 emit_bti(A64_BTI_JC, ctx); 563 564 emit(A64_MOV(1, A64_R(9), A64_LR), ctx); 565 emit(A64_NOP, ctx); 566 567 if (!prog->aux->exception_cb) { 568 /* Sign lr */ 569 if (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL)) 570 emit(A64_PACIASP, ctx); 571 572 /* Save FP and LR registers to stay align with ARM64 AAPCS */ 573 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); 574 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 575 576 prepare_bpf_tail_call_cnt(ctx); 577 578 if (!ebpf_from_cbpf && is_main_prog) { 579 cur_offset = ctx->idx - idx0; 580 if (cur_offset != PROLOGUE_OFFSET) { 581 pr_err_once("PROLOGUE_OFFSET = %d, expected %d!\n", 582 cur_offset, PROLOGUE_OFFSET); 583 return -1; 584 } 585 /* BTI landing pad for the tail call, done with a BR */ 586 emit_bti(A64_BTI_J, ctx); 587 } 588 push_callee_regs(ctx); 589 } else { 590 /* 591 * Exception callback receives FP of Main Program as third 592 * parameter 593 */ 594 emit(A64_MOV(1, A64_FP, A64_R(2)), ctx); 595 /* 596 * Main Program already pushed the frame record and the 597 * callee-saved registers. The exception callback will not push 598 * anything and re-use the main program's stack. 599 * 600 * 12 registers are on the stack 601 */ 602 emit(A64_SUB_I(1, A64_SP, A64_FP, 96), ctx); 603 /* The callback may use its own BPF stack, set up fp for it. */ 604 ctx->fp_used = true; 605 } 606 607 /* Stack must be multiples of 16B */ 608 ctx->stack_size = round_up(prog->aux->stack_depth, 16); 609 610 if (ctx->fp_used) { 611 if (ctx->priv_sp_used) { 612 /* Set up private stack pointer */ 613 priv_stack_ptr = prog->aux->priv_stack_ptr + PRIV_STACK_GUARD_SZ; 614 emit_percpu_ptr(priv_sp, priv_stack_ptr, ctx); 615 emit(A64_ADD_I(1, fp, priv_sp, ctx->stack_size), ctx); 616 } else { 617 /* Set up BPF prog stack base register */ 618 emit(A64_MOV(1, fp, A64_SP), ctx); 619 } 620 } 621 622 /* Set up function call stack */ 623 if (ctx->stack_size && !ctx->priv_sp_used) 624 emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 625 626 if (ctx->stack_arg_size) 627 emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 628 629 if (ctx->arena_vm_start) 630 emit_a64_mov_i64(arena_vm_base, ctx->arena_vm_start, ctx); 631 632 return 0; 633 } 634 635 static int emit_bpf_tail_call(struct jit_ctx *ctx) 636 { 637 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */ 638 const u8 r2 = bpf2a64[BPF_REG_2]; 639 const u8 r3 = bpf2a64[BPF_REG_3]; 640 641 const u8 tmp = bpf2a64[TMP_REG_1]; 642 const u8 prg = bpf2a64[TMP_REG_2]; 643 const u8 tcc = bpf2a64[TMP_REG_3]; 644 const u8 ptr = bpf2a64[TCCNT_PTR]; 645 size_t off; 646 __le32 *branch1 = NULL; 647 __le32 *branch2 = NULL; 648 __le32 *branch3 = NULL; 649 650 /* if (index >= array->map.max_entries) 651 * goto out; 652 */ 653 off = offsetof(struct bpf_array, map.max_entries); 654 emit_a64_mov_i64(tmp, off, ctx); 655 emit(A64_LDR32(tmp, r2, tmp), ctx); 656 emit(A64_MOV(0, r3, r3), ctx); 657 emit(A64_CMP(0, r3, tmp), ctx); 658 branch1 = ctx->image + ctx->idx; 659 emit(A64_NOP, ctx); 660 661 /* 662 * if ((*tail_call_cnt_ptr) >= MAX_TAIL_CALL_CNT) 663 * goto out; 664 */ 665 emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx); 666 emit(A64_LDR64I(tcc, ptr, 0), ctx); 667 emit(A64_CMP(1, tcc, tmp), ctx); 668 branch2 = ctx->image + ctx->idx; 669 emit(A64_NOP, ctx); 670 671 /* (*tail_call_cnt_ptr)++; */ 672 emit(A64_ADD_I(1, tcc, tcc, 1), ctx); 673 674 /* prog = array->ptrs[index]; 675 * if (prog == NULL) 676 * goto out; 677 */ 678 off = offsetof(struct bpf_array, ptrs); 679 emit_a64_mov_i64(tmp, off, ctx); 680 emit(A64_ADD(1, tmp, r2, tmp), ctx); 681 emit(A64_LSL(1, prg, r3, 3), ctx); 682 emit(A64_LDR64(prg, tmp, prg), ctx); 683 branch3 = ctx->image + ctx->idx; 684 emit(A64_NOP, ctx); 685 686 /* Update tail_call_cnt if the slot is populated. */ 687 emit(A64_STR64I(tcc, ptr, 0), ctx); 688 689 if (ctx->stack_arg_size) 690 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 691 692 /* restore SP */ 693 if (ctx->stack_size && !ctx->priv_sp_used) 694 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 695 696 pop_callee_regs(ctx); 697 698 /* goto *(prog->bpf_func + prologue_offset); */ 699 off = offsetof(struct bpf_prog, bpf_func); 700 emit_a64_mov_i64(tmp, off, ctx); 701 emit(A64_LDR64(tmp, prg, tmp), ctx); 702 emit(A64_ADD_I(1, tmp, tmp, sizeof(u32) * PROLOGUE_OFFSET), ctx); 703 emit(A64_BR(tmp), ctx); 704 705 if (ctx->image) { 706 off = &ctx->image[ctx->idx] - branch1; 707 *branch1 = cpu_to_le32(A64_B_(A64_COND_CS, off)); 708 709 off = &ctx->image[ctx->idx] - branch2; 710 *branch2 = cpu_to_le32(A64_B_(A64_COND_CS, off)); 711 712 off = &ctx->image[ctx->idx] - branch3; 713 *branch3 = cpu_to_le32(A64_CBZ(1, prg, off)); 714 } 715 716 return 0; 717 } 718 719 static int emit_atomic_ld_st(const struct bpf_insn *insn, struct jit_ctx *ctx) 720 { 721 const s32 imm = insn->imm; 722 const s16 off = insn->off; 723 const u8 code = insn->code; 724 const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC; 725 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 726 const u8 dst = bpf2a64[insn->dst_reg]; 727 const u8 src = bpf2a64[insn->src_reg]; 728 const u8 tmp = bpf2a64[TMP_REG_1]; 729 u8 reg; 730 731 switch (imm) { 732 case BPF_LOAD_ACQ: 733 reg = src; 734 break; 735 case BPF_STORE_REL: 736 reg = dst; 737 break; 738 default: 739 pr_err_once("unknown atomic load/store op code %02x\n", imm); 740 return -EINVAL; 741 } 742 743 if (off) { 744 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 745 reg = tmp; 746 } 747 if (arena) { 748 emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx); 749 reg = tmp; 750 } 751 752 switch (imm) { 753 case BPF_LOAD_ACQ: 754 switch (BPF_SIZE(code)) { 755 case BPF_B: 756 emit(A64_LDARB(dst, reg), ctx); 757 break; 758 case BPF_H: 759 emit(A64_LDARH(dst, reg), ctx); 760 break; 761 case BPF_W: 762 emit(A64_LDAR32(dst, reg), ctx); 763 break; 764 case BPF_DW: 765 emit(A64_LDAR64(dst, reg), ctx); 766 break; 767 } 768 break; 769 case BPF_STORE_REL: 770 switch (BPF_SIZE(code)) { 771 case BPF_B: 772 emit(A64_STLRB(src, reg), ctx); 773 break; 774 case BPF_H: 775 emit(A64_STLRH(src, reg), ctx); 776 break; 777 case BPF_W: 778 emit(A64_STLR32(src, reg), ctx); 779 break; 780 case BPF_DW: 781 emit(A64_STLR64(src, reg), ctx); 782 break; 783 } 784 break; 785 default: 786 pr_err_once("unexpected atomic load/store op code %02x\n", 787 imm); 788 return -EINVAL; 789 } 790 791 return 0; 792 } 793 794 static int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 795 { 796 const u8 code = insn->code; 797 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 798 const u8 dst = bpf2a64[insn->dst_reg]; 799 const u8 src = bpf2a64[insn->src_reg]; 800 const u8 tmp = bpf2a64[TMP_REG_1]; 801 const u8 tmp2 = bpf2a64[TMP_REG_2]; 802 const bool isdw = BPF_SIZE(code) == BPF_DW; 803 const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC; 804 const s16 off = insn->off; 805 u8 reg = dst; 806 807 if (off) { 808 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 809 reg = tmp; 810 } 811 if (arena) { 812 emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx); 813 reg = tmp; 814 } 815 816 switch (insn->imm) { 817 /* lock *(u32/u64 *)(dst_reg + off) <op>= src_reg */ 818 case BPF_ADD: 819 emit(A64_STADD(isdw, reg, src), ctx); 820 break; 821 case BPF_AND: 822 emit(A64_MVN(isdw, tmp2, src), ctx); 823 emit(A64_STCLR(isdw, reg, tmp2), ctx); 824 break; 825 case BPF_OR: 826 emit(A64_STSET(isdw, reg, src), ctx); 827 break; 828 case BPF_XOR: 829 emit(A64_STEOR(isdw, reg, src), ctx); 830 break; 831 /* src_reg = atomic_fetch_<op>(dst_reg + off, src_reg) */ 832 case BPF_ADD | BPF_FETCH: 833 emit(A64_LDADDAL(isdw, src, reg, src), ctx); 834 break; 835 case BPF_AND | BPF_FETCH: 836 emit(A64_MVN(isdw, tmp2, src), ctx); 837 emit(A64_LDCLRAL(isdw, src, reg, tmp2), ctx); 838 break; 839 case BPF_OR | BPF_FETCH: 840 emit(A64_LDSETAL(isdw, src, reg, src), ctx); 841 break; 842 case BPF_XOR | BPF_FETCH: 843 emit(A64_LDEORAL(isdw, src, reg, src), ctx); 844 break; 845 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 846 case BPF_XCHG: 847 emit(A64_SWPAL(isdw, src, reg, src), ctx); 848 break; 849 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 850 case BPF_CMPXCHG: 851 emit(A64_CASAL(isdw, src, reg, bpf2a64[BPF_REG_0]), ctx); 852 break; 853 default: 854 pr_err_once("unknown atomic op code %02x\n", insn->imm); 855 return -EINVAL; 856 } 857 858 return 0; 859 } 860 861 static int emit_ll_sc_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 862 { 863 const u8 code = insn->code; 864 const u8 dst = bpf2a64[insn->dst_reg]; 865 const u8 src = bpf2a64[insn->src_reg]; 866 const u8 tmp = bpf2a64[TMP_REG_1]; 867 const u8 tmp2 = bpf2a64[TMP_REG_2]; 868 const u8 tmp3 = bpf2a64[TMP_REG_3]; 869 const int i = insn - ctx->prog->insnsi; 870 const s32 imm = insn->imm; 871 const s16 off = insn->off; 872 const bool isdw = BPF_SIZE(code) == BPF_DW; 873 u8 reg = dst; 874 s32 jmp_offset; 875 876 if (BPF_MODE(code) == BPF_PROBE_ATOMIC) { 877 /* ll_sc based atomics don't support unsafe pointers yet. */ 878 pr_err_once("unknown atomic opcode %02x\n", code); 879 return -EINVAL; 880 } 881 882 if (off) { 883 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 884 reg = tmp; 885 } 886 887 if (imm == BPF_ADD || imm == BPF_AND || 888 imm == BPF_OR || imm == BPF_XOR) { 889 /* lock *(u32/u64 *)(dst_reg + off) <op>= src_reg */ 890 emit(A64_LDXR(isdw, tmp2, reg), ctx); 891 if (imm == BPF_ADD) 892 emit(A64_ADD(isdw, tmp2, tmp2, src), ctx); 893 else if (imm == BPF_AND) 894 emit(A64_AND(isdw, tmp2, tmp2, src), ctx); 895 else if (imm == BPF_OR) 896 emit(A64_ORR(isdw, tmp2, tmp2, src), ctx); 897 else 898 emit(A64_EOR(isdw, tmp2, tmp2, src), ctx); 899 emit(A64_STXR(isdw, tmp2, reg, tmp3), ctx); 900 jmp_offset = -3; 901 check_imm19(jmp_offset); 902 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 903 } else if (imm == (BPF_ADD | BPF_FETCH) || 904 imm == (BPF_AND | BPF_FETCH) || 905 imm == (BPF_OR | BPF_FETCH) || 906 imm == (BPF_XOR | BPF_FETCH)) { 907 /* src_reg = atomic_fetch_<op>(dst_reg + off, src_reg) */ 908 const u8 ax = bpf2a64[BPF_REG_AX]; 909 910 emit(A64_MOV(isdw, ax, src), ctx); 911 emit(A64_LDXR(isdw, src, reg), ctx); 912 if (imm == (BPF_ADD | BPF_FETCH)) 913 emit(A64_ADD(isdw, tmp2, src, ax), ctx); 914 else if (imm == (BPF_AND | BPF_FETCH)) 915 emit(A64_AND(isdw, tmp2, src, ax), ctx); 916 else if (imm == (BPF_OR | BPF_FETCH)) 917 emit(A64_ORR(isdw, tmp2, src, ax), ctx); 918 else 919 emit(A64_EOR(isdw, tmp2, src, ax), ctx); 920 emit(A64_STLXR(isdw, tmp2, reg, tmp3), ctx); 921 jmp_offset = -3; 922 check_imm19(jmp_offset); 923 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 924 emit(A64_DMB_ISH, ctx); 925 } else if (imm == BPF_XCHG) { 926 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 927 emit(A64_MOV(isdw, tmp2, src), ctx); 928 emit(A64_LDXR(isdw, src, reg), ctx); 929 emit(A64_STLXR(isdw, tmp2, reg, tmp3), ctx); 930 jmp_offset = -2; 931 check_imm19(jmp_offset); 932 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 933 emit(A64_DMB_ISH, ctx); 934 } else if (imm == BPF_CMPXCHG) { 935 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 936 const u8 r0 = bpf2a64[BPF_REG_0]; 937 938 emit(A64_MOV(isdw, tmp2, r0), ctx); 939 emit(A64_LDXR(isdw, r0, reg), ctx); 940 emit(A64_EOR(isdw, tmp3, r0, tmp2), ctx); 941 jmp_offset = 4; 942 check_imm19(jmp_offset); 943 emit(A64_CBNZ(isdw, tmp3, jmp_offset), ctx); 944 emit(A64_STLXR(isdw, src, reg, tmp3), ctx); 945 jmp_offset = -4; 946 check_imm19(jmp_offset); 947 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 948 emit(A64_DMB_ISH, ctx); 949 } else { 950 pr_err_once("unknown atomic op code %02x\n", imm); 951 return -EINVAL; 952 } 953 954 return 0; 955 } 956 957 void dummy_tramp(void); 958 959 asm ( 960 " .pushsection .text, \"ax\", @progbits\n" 961 " .global dummy_tramp\n" 962 " .type dummy_tramp, %function\n" 963 "dummy_tramp:" 964 #if IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) 965 " bti j\n" /* dummy_tramp is called via "br x10" */ 966 #endif 967 " mov x10, x30\n" 968 " mov x30, x9\n" 969 " ret x10\n" 970 " .size dummy_tramp, .-dummy_tramp\n" 971 " .popsection\n" 972 ); 973 974 /* build a plt initialized like this: 975 * 976 * plt: 977 * ldr tmp, target 978 * br tmp 979 * target: 980 * .quad dummy_tramp 981 * 982 * when a long jump trampoline is attached, target is filled with the 983 * trampoline address, and when the trampoline is removed, target is 984 * restored to dummy_tramp address. 985 */ 986 static void build_plt(struct jit_ctx *ctx) 987 { 988 const u8 tmp = bpf2a64[TMP_REG_1]; 989 struct bpf_plt *plt = NULL; 990 991 /* make sure target is 64-bit aligned */ 992 if ((ctx->idx + PLT_TARGET_OFFSET / AARCH64_INSN_SIZE) % 2) 993 emit(A64_NOP, ctx); 994 995 plt = (struct bpf_plt *)(ctx->image + ctx->idx); 996 /* plt is called via bl, no BTI needed here */ 997 emit(A64_LDR64LIT(tmp, 2 * AARCH64_INSN_SIZE), ctx); 998 emit(A64_BR(tmp), ctx); 999 1000 if (ctx->image) 1001 plt->target = (u64)&dummy_tramp; 1002 } 1003 1004 /* Clobbers BPF registers 1-4, aka x0-x3 */ 1005 static void __maybe_unused build_bhb_mitigation(struct jit_ctx *ctx) 1006 { 1007 const u8 r1 = bpf2a64[BPF_REG_1]; /* aka x0 */ 1008 u8 k = get_spectre_bhb_loop_value(); 1009 1010 if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY) || 1011 cpu_mitigations_off() || __nospectre_bhb || 1012 arm64_get_spectre_v2_state() == SPECTRE_VULNERABLE) 1013 return; 1014 1015 if (ns_capable_noaudit(&init_user_ns, CAP_SYS_ADMIN)) 1016 return; 1017 1018 if (supports_clearbhb(SCOPE_SYSTEM)) { 1019 emit(aarch64_insn_gen_hint(AARCH64_INSN_HINT_CLEARBHB), ctx); 1020 return; 1021 } 1022 1023 if (k) { 1024 emit_a64_mov_i64(r1, k, ctx); 1025 emit(A64_B(1), ctx); 1026 emit(A64_SUBS_I(true, r1, r1, 1), ctx); 1027 emit(A64_B_(A64_COND_NE, -2), ctx); 1028 emit(aarch64_insn_gen_dsb(AARCH64_INSN_MB_ISH), ctx); 1029 emit(aarch64_insn_get_isb_value(), ctx); 1030 } 1031 1032 if (is_spectre_bhb_fw_mitigated()) { 1033 emit(A64_ORR_I(false, r1, AARCH64_INSN_REG_ZR, 1034 ARM_SMCCC_ARCH_WORKAROUND_3), ctx); 1035 switch (arm_smccc_1_1_get_conduit()) { 1036 case SMCCC_CONDUIT_HVC: 1037 emit(aarch64_insn_get_hvc_value(), ctx); 1038 break; 1039 case SMCCC_CONDUIT_SMC: 1040 emit(aarch64_insn_get_smc_value(), ctx); 1041 break; 1042 default: 1043 pr_err_once("Firmware mitigation enabled with unknown conduit\n"); 1044 } 1045 } 1046 } 1047 1048 static void build_epilogue(struct jit_ctx *ctx, bool was_classic) 1049 { 1050 const u8 r0 = bpf2a64[BPF_REG_0]; 1051 const u8 ptr = bpf2a64[TCCNT_PTR]; 1052 1053 if (ctx->stack_arg_size) 1054 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 1055 1056 /* We're done with BPF stack */ 1057 if (ctx->stack_size && !ctx->priv_sp_used) 1058 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 1059 1060 pop_callee_regs(ctx); 1061 1062 emit(A64_POP(A64_ZR, ptr, A64_SP), ctx); 1063 1064 if (was_classic) 1065 build_bhb_mitigation(ctx); 1066 1067 /* Restore FP/LR registers */ 1068 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 1069 1070 /* Move the return value from bpf:r0 (aka x8) to x0 */ 1071 emit(A64_MOV(1, A64_R(0), r0), ctx); 1072 1073 /* Authenticate lr */ 1074 if (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL)) 1075 emit(A64_AUTIASP, ctx); 1076 1077 emit(A64_RET(A64_LR), ctx); 1078 } 1079 1080 /* 1081 * Metadata encoding for exception handling in JITed code. 1082 * 1083 * Format of `fixup` field in `struct exception_table_entry`: 1084 * 1085 * Bit layout of `fixup` (32-bit): 1086 * 1087 * +-----------+--------+-------------+-----------+-----------+----------+ 1088 * | 31-27 | 26-23 | 22 | 21 | 20-16 | 15-0 | 1089 * | | | | | | | 1090 * | FIXUP_REG | Unused | ARENA_WRITE | ARENA_ACC | ARENA_REG | OFFSET | 1091 * +-----------+--------+-------------+-----------+-----------+----------+ 1092 * 1093 * - OFFSET (16 bits): Offset used to compute address for Load/Store instruction. 1094 * - ARENA_REG (5 bits): Register that is used to calculate the address for load/store when 1095 * accessing the arena region. 1096 * - ARENA_ACCESS (1 bit): This bit is set when the faulting instruction accessed the arena region. 1097 * - ARENA_WRITE (1 bit): This bit is set when the faulting instruction wrote to the arena region. 1098 * It is independent of FIXUP_REG, since a read-modify-write both writes to 1099 * memory and reads the old value into a register. 1100 * - FIXUP_REG (5 bits): Destination register for the load instruction (cleared on fault) or set to 1101 * DONT_CLEAR if the instruction does not read into a register. 1102 */ 1103 1104 #define BPF_FIXUP_OFFSET_MASK GENMASK(15, 0) 1105 #define BPF_FIXUP_ARENA_REG_MASK GENMASK(20, 16) 1106 #define BPF_ARENA_ACCESS BIT(21) 1107 #define BPF_ARENA_WRITE BIT(22) 1108 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 1109 #define DONT_CLEAR 5 /* Unused ARM64 register from BPF's POV */ 1110 1111 bool ex_handler_bpf(const struct exception_table_entry *ex, 1112 struct pt_regs *regs) 1113 { 1114 int dst_reg = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 1115 s16 off = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 1116 int arena_reg = FIELD_GET(BPF_FIXUP_ARENA_REG_MASK, ex->fixup); 1117 bool is_arena = !!(ex->fixup & BPF_ARENA_ACCESS); 1118 bool is_write = !!(ex->fixup & BPF_ARENA_WRITE); 1119 unsigned long addr; 1120 1121 if (is_arena) { 1122 addr = regs->regs[arena_reg] + off; 1123 bpf_prog_report_arena_violation(is_write, addr, regs->pc); 1124 } 1125 1126 if (dst_reg != DONT_CLEAR) 1127 regs->regs[dst_reg] = 0; 1128 /* Skip the faulting instruction */ 1129 regs->pc += AARCH64_INSN_SIZE; 1130 1131 return true; 1132 } 1133 1134 /* For accesses to BTF pointers, add an entry to the exception table */ 1135 static int add_exception_handler(const struct bpf_insn *insn, 1136 struct jit_ctx *ctx, 1137 int dst_reg) 1138 { 1139 off_t ins_offset; 1140 s16 off = insn->off; 1141 bool is_arena, is_write; 1142 int arena_reg; 1143 unsigned long pc; 1144 struct exception_table_entry *ex; 1145 1146 if (!ctx->image) 1147 /* First pass */ 1148 return 0; 1149 1150 if (BPF_MODE(insn->code) != BPF_PROBE_MEM && 1151 BPF_MODE(insn->code) != BPF_PROBE_MEMSX && 1152 BPF_MODE(insn->code) != BPF_PROBE_MEM32 && 1153 BPF_MODE(insn->code) != BPF_PROBE_MEM32SX && 1154 BPF_MODE(insn->code) != BPF_PROBE_ATOMIC) 1155 return 0; 1156 1157 is_arena = (BPF_MODE(insn->code) == BPF_PROBE_MEM32) || 1158 (BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) || 1159 (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC); 1160 1161 if (!ctx->prog->aux->extable || 1162 WARN_ON_ONCE(ctx->exentry_idx >= ctx->prog->aux->num_exentries)) 1163 return -EINVAL; 1164 1165 ex = &ctx->prog->aux->extable[ctx->exentry_idx]; 1166 pc = (unsigned long)&ctx->ro_image[ctx->idx - 1]; 1167 1168 /* 1169 * This is the relative offset of the instruction that may fault from 1170 * the exception table itself. This will be written to the exception 1171 * table and if this instruction faults, the destination register will 1172 * be set to '0' and the execution will jump to the next instruction. 1173 */ 1174 ins_offset = pc - (long)&ex->insn; 1175 if (WARN_ON_ONCE(ins_offset >= 0 || ins_offset < INT_MIN)) 1176 return -ERANGE; 1177 1178 /* 1179 * The offsets above have been calculated using the RO buffer but we 1180 * need to use the R/W buffer for writes. 1181 * switch ex to rw buffer for writing. 1182 */ 1183 ex = (void *)ctx->image + ((void *)ex - (void *)ctx->ro_image); 1184 1185 ex->insn = ins_offset; 1186 1187 /* 1188 * A load-acquire is of BPF_STX class, but reads from src_reg into 1189 * dst_reg like a BPF_LDX does, hence it must not be treated as a store 1190 * here. A read-modify-write carrying BPF_FETCH is reported as a write 1191 * even though it does have a register to clear, see the callers. 1192 */ 1193 is_write = BPF_CLASS(insn->code) != BPF_LDX && 1194 !bpf_atomic_is_load_acq(insn); 1195 1196 ex->fixup = FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 1197 1198 if (is_arena) { 1199 ex->fixup |= BPF_ARENA_ACCESS; 1200 if (is_write) 1201 ex->fixup |= BPF_ARENA_WRITE; 1202 /* 1203 * insn->src_reg/dst_reg holds the address in the arena region with upper 32-bits 1204 * being zero because of a preceding addr_space_cast(r<n>, 0x0, 0x1) instruction. 1205 * This address is adjusted with the addition of arena_vm_start (see the 1206 * implementation of BPF_PROBE_MEM32 and BPF_PROBE_ATOMIC) before being used for the 1207 * memory access. Pass the reg holding the unmodified 32-bit address to 1208 * ex_handler_bpf. 1209 */ 1210 if (BPF_CLASS(insn->code) == BPF_LDX || bpf_atomic_is_load_acq(insn)) 1211 arena_reg = bpf2a64[insn->src_reg]; 1212 else 1213 arena_reg = bpf2a64[insn->dst_reg]; 1214 1215 ex->fixup |= FIELD_PREP(BPF_FIXUP_OFFSET_MASK, off) | 1216 FIELD_PREP(BPF_FIXUP_ARENA_REG_MASK, arena_reg); 1217 } 1218 1219 ex->type = EX_TYPE_BPF; 1220 1221 ctx->exentry_idx++; 1222 return 0; 1223 } 1224 1225 static const u8 stack_arg_reg[] = { A64_R(5), A64_R(6), A64_R(7) }; 1226 1227 #define NR_STACK_ARG_REGS ARRAY_SIZE(stack_arg_reg) 1228 1229 static void emit_stack_arg_load(u8 dst, s16 bpf_off, struct jit_ctx *ctx) 1230 { 1231 int idx = bpf_off / sizeof(u64) - 1; 1232 1233 if (idx < NR_STACK_ARG_REGS) 1234 emit(A64_MOV(1, dst, stack_arg_reg[idx]), ctx); 1235 else 1236 emit(A64_LDR64I(dst, A64_FP, (idx - NR_STACK_ARG_REGS) * sizeof(u64) + 16), ctx); 1237 } 1238 1239 static void emit_stack_arg_store(u8 src_a64, s16 bpf_off, struct jit_ctx *ctx) 1240 { 1241 int idx = -bpf_off / sizeof(u64) - 1; 1242 1243 if (idx < NR_STACK_ARG_REGS) 1244 emit(A64_MOV(1, stack_arg_reg[idx], src_a64), ctx); 1245 else 1246 emit(A64_STR64I(src_a64, A64_SP, (idx - NR_STACK_ARG_REGS) * sizeof(u64)), ctx); 1247 } 1248 1249 static void emit_stack_arg_store_imm(s32 imm, s16 bpf_off, const u8 tmp, struct jit_ctx *ctx) 1250 { 1251 int idx = -bpf_off / sizeof(u64) - 1; 1252 1253 if (idx < NR_STACK_ARG_REGS) { 1254 emit_a64_mov_i(1, stack_arg_reg[idx], imm, ctx); 1255 } else { 1256 emit_a64_mov_i(1, tmp, imm, ctx); 1257 emit(A64_STR64I(tmp, A64_SP, (idx - NR_STACK_ARG_REGS) * sizeof(u64)), ctx); 1258 } 1259 } 1260 1261 /* 1262 * Rebase the __arena args of a kfunc call to arena kernel addresses, 1263 * xN = kern_vm_start + (u32)xN, with the arena base register holding 1264 * kern_vm_start. A nullable arg preserves NULL by skipping the add, tested 1265 * on the truncated value as arena NULL is offset 0. 1266 */ 1267 static int emit_kfunc_arena_args(struct jit_ctx *ctx, const struct bpf_insn *insn) 1268 { 1269 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 1270 const struct btf_func_model *fm; 1271 int i; 1272 1273 fm = bpf_jit_find_kfunc_model(ctx->prog, insn); 1274 if (!fm) 1275 return -EINVAL; 1276 1277 for (i = 0; i < min_t(int, fm->nr_args, MAX_BPF_FUNC_REG_ARGS); i++) { 1278 const u8 reg = bpf2a64[BPF_REG_1 + i]; 1279 u8 flags = fm->arg_flags[i]; 1280 1281 if (!(flags & BTF_FMODEL_ARENA_ARG)) 1282 continue; 1283 if (WARN_ON_ONCE(!ctx->arena_vm_start)) 1284 return -EINVAL; 1285 1286 if (flags & BTF_FMODEL_NULLABLE_ARG) { 1287 /* 32-bit mov clears the upper 32 bits */ 1288 emit(A64_MOV(0, reg, reg), ctx); 1289 /* skip the add so that NULL stays NULL */ 1290 emit(A64_CBZ(0, reg, 2), ctx); 1291 } 1292 emit(A64_ADD_UXTW(reg, arena_vm_base, reg), ctx); 1293 } 1294 1295 return 0; 1296 } 1297 1298 /* JITs an eBPF instruction. 1299 * Returns: 1300 * 0 - successfully JITed an 8-byte eBPF instruction. 1301 * >0 - successfully JITed a 16-byte eBPF instruction. 1302 * <0 - failed to JIT. 1303 */ 1304 static int build_insn(const struct bpf_verifier_env *env, const struct bpf_insn *insn, 1305 struct jit_ctx *ctx, bool extra_pass) 1306 { 1307 const u8 code = insn->code; 1308 u8 dst = bpf2a64[insn->dst_reg]; 1309 u8 src = bpf2a64[insn->src_reg]; 1310 const u8 tmp = bpf2a64[TMP_REG_1]; 1311 const u8 tmp2 = bpf2a64[TMP_REG_2]; 1312 const u8 tmp3 = bpf2a64[TMP_REG_3]; 1313 const u8 fp = bpf2a64[BPF_REG_FP]; 1314 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 1315 const u8 priv_sp = bpf2a64[PRIVATE_SP]; 1316 const s16 off = insn->off; 1317 const s32 imm = insn->imm; 1318 const int i = insn - ctx->prog->insnsi; 1319 const bool is64 = BPF_CLASS(code) == BPF_ALU64 || 1320 BPF_CLASS(code) == BPF_JMP; 1321 u8 jmp_cond; 1322 s32 jmp_offset; 1323 u32 a64_insn; 1324 u8 src_adj; 1325 u8 dst_adj; 1326 int off_adj; 1327 int ret; 1328 bool sign_extend; 1329 1330 if (bpf_insn_is_indirect_target(env, ctx->prog, i)) 1331 emit_bti(A64_BTI_J, ctx); 1332 1333 switch (code) { 1334 /* dst = src */ 1335 case BPF_ALU | BPF_MOV | BPF_X: 1336 case BPF_ALU64 | BPF_MOV | BPF_X: 1337 if (insn_is_cast_user(insn)) { 1338 u32 upper = ctx->user_vm_start >> 32; 1339 u16 upper_low = upper & 0xffff; 1340 u16 upper_high = upper >> 16; 1341 int nr_movk = !!upper_low + !!upper_high; 1342 1343 /* 1344 * Build the user address: the low 32 bits are the arena 1345 * offset, the upper 32 bits come from user_vm_start. A 1346 * zero offset must stay NULL, so branch over the MOVKs 1347 * when it is zero. 1348 */ 1349 emit(A64_MOV(0, dst, src), ctx); /* 32-bit mov clears the upper 32 bits */ 1350 if (nr_movk) { 1351 emit(A64_CBZ(0, dst, nr_movk + 1), ctx); 1352 if (upper_low) 1353 emit(A64_MOVK(1, dst, upper_low, 32), ctx); 1354 if (upper_high) 1355 emit(A64_MOVK(1, dst, upper_high, 48), ctx); 1356 } 1357 break; 1358 } else if (insn_is_mov_percpu_addr(insn)) { 1359 if (dst != src) 1360 emit(A64_MOV(1, dst, src), ctx); 1361 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) 1362 emit(A64_MRS_TPIDR_EL2(tmp), ctx); 1363 else 1364 emit(A64_MRS_TPIDR_EL1(tmp), ctx); 1365 emit(A64_ADD(1, dst, dst, tmp), ctx); 1366 break; 1367 } 1368 switch (insn->off) { 1369 case 0: 1370 emit(A64_MOV(is64, dst, src), ctx); 1371 break; 1372 case 8: 1373 emit(A64_SXTB(is64, dst, src), ctx); 1374 break; 1375 case 16: 1376 emit(A64_SXTH(is64, dst, src), ctx); 1377 break; 1378 case 32: 1379 emit(A64_SXTW(is64, dst, src), ctx); 1380 break; 1381 } 1382 break; 1383 /* dst = dst OP src */ 1384 case BPF_ALU | BPF_ADD | BPF_X: 1385 case BPF_ALU64 | BPF_ADD | BPF_X: 1386 emit(A64_ADD(is64, dst, dst, src), ctx); 1387 break; 1388 case BPF_ALU | BPF_SUB | BPF_X: 1389 case BPF_ALU64 | BPF_SUB | BPF_X: 1390 emit(A64_SUB(is64, dst, dst, src), ctx); 1391 break; 1392 case BPF_ALU | BPF_AND | BPF_X: 1393 case BPF_ALU64 | BPF_AND | BPF_X: 1394 emit(A64_AND(is64, dst, dst, src), ctx); 1395 break; 1396 case BPF_ALU | BPF_OR | BPF_X: 1397 case BPF_ALU64 | BPF_OR | BPF_X: 1398 emit(A64_ORR(is64, dst, dst, src), ctx); 1399 break; 1400 case BPF_ALU | BPF_XOR | BPF_X: 1401 case BPF_ALU64 | BPF_XOR | BPF_X: 1402 emit(A64_EOR(is64, dst, dst, src), ctx); 1403 break; 1404 case BPF_ALU | BPF_MUL | BPF_X: 1405 case BPF_ALU64 | BPF_MUL | BPF_X: 1406 emit(A64_MUL(is64, dst, dst, src), ctx); 1407 break; 1408 case BPF_ALU | BPF_DIV | BPF_X: 1409 case BPF_ALU64 | BPF_DIV | BPF_X: 1410 if (!off) 1411 emit(A64_UDIV(is64, dst, dst, src), ctx); 1412 else 1413 emit(A64_SDIV(is64, dst, dst, src), ctx); 1414 break; 1415 case BPF_ALU | BPF_MOD | BPF_X: 1416 case BPF_ALU64 | BPF_MOD | BPF_X: 1417 if (!off) 1418 emit(A64_UDIV(is64, tmp, dst, src), ctx); 1419 else 1420 emit(A64_SDIV(is64, tmp, dst, src), ctx); 1421 emit(A64_MSUB(is64, dst, dst, tmp, src), ctx); 1422 break; 1423 case BPF_ALU | BPF_LSH | BPF_X: 1424 case BPF_ALU64 | BPF_LSH | BPF_X: 1425 emit(A64_LSLV(is64, dst, dst, src), ctx); 1426 break; 1427 case BPF_ALU | BPF_RSH | BPF_X: 1428 case BPF_ALU64 | BPF_RSH | BPF_X: 1429 emit(A64_LSRV(is64, dst, dst, src), ctx); 1430 break; 1431 case BPF_ALU | BPF_ARSH | BPF_X: 1432 case BPF_ALU64 | BPF_ARSH | BPF_X: 1433 emit(A64_ASRV(is64, dst, dst, src), ctx); 1434 break; 1435 /* dst = -dst */ 1436 case BPF_ALU | BPF_NEG: 1437 case BPF_ALU64 | BPF_NEG: 1438 emit(A64_NEG(is64, dst, dst), ctx); 1439 break; 1440 /* dst = BSWAP##imm(dst) */ 1441 case BPF_ALU | BPF_END | BPF_FROM_LE: 1442 case BPF_ALU | BPF_END | BPF_FROM_BE: 1443 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1444 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE) 1445 goto emit_bswap_uxt; 1446 switch (imm) { 1447 case 16: 1448 emit(A64_REV16(is64, dst, dst), ctx); 1449 /* zero-extend 16 bits into 64 bits */ 1450 emit(A64_UXTH(is64, dst, dst), ctx); 1451 break; 1452 case 32: 1453 emit(A64_REV32(0, dst, dst), ctx); 1454 /* upper 32 bits already cleared */ 1455 break; 1456 case 64: 1457 emit(A64_REV64(dst, dst), ctx); 1458 break; 1459 } 1460 break; 1461 emit_bswap_uxt: 1462 switch (imm) { 1463 case 16: 1464 /* zero-extend 16 bits into 64 bits */ 1465 emit(A64_UXTH(is64, dst, dst), ctx); 1466 break; 1467 case 32: 1468 /* zero-extend 32 bits into 64 bits */ 1469 emit(A64_UXTW(is64, dst, dst), ctx); 1470 break; 1471 case 64: 1472 /* nop */ 1473 break; 1474 } 1475 break; 1476 /* dst = imm */ 1477 case BPF_ALU | BPF_MOV | BPF_K: 1478 case BPF_ALU64 | BPF_MOV | BPF_K: 1479 emit_a64_mov_i(is64, dst, imm, ctx); 1480 break; 1481 /* dst = dst OP imm */ 1482 case BPF_ALU | BPF_ADD | BPF_K: 1483 case BPF_ALU64 | BPF_ADD | BPF_K: 1484 emit_a64_add_i(is64, dst, dst, tmp, imm, ctx); 1485 break; 1486 case BPF_ALU | BPF_SUB | BPF_K: 1487 case BPF_ALU64 | BPF_SUB | BPF_K: 1488 if (is_addsub_imm(imm)) { 1489 emit(A64_SUB_I(is64, dst, dst, imm), ctx); 1490 } else if (is_addsub_imm(-(u32)imm)) { 1491 emit(A64_ADD_I(is64, dst, dst, -imm), ctx); 1492 } else { 1493 emit_a64_mov_i(is64, tmp, imm, ctx); 1494 emit(A64_SUB(is64, dst, dst, tmp), ctx); 1495 } 1496 break; 1497 case BPF_ALU | BPF_AND | BPF_K: 1498 case BPF_ALU64 | BPF_AND | BPF_K: 1499 a64_insn = A64_AND_I(is64, dst, dst, imm); 1500 if (a64_insn != AARCH64_BREAK_FAULT) { 1501 emit(a64_insn, ctx); 1502 } else { 1503 emit_a64_mov_i(is64, tmp, imm, ctx); 1504 emit(A64_AND(is64, dst, dst, tmp), ctx); 1505 } 1506 break; 1507 case BPF_ALU | BPF_OR | BPF_K: 1508 case BPF_ALU64 | BPF_OR | BPF_K: 1509 a64_insn = A64_ORR_I(is64, dst, dst, imm); 1510 if (a64_insn != AARCH64_BREAK_FAULT) { 1511 emit(a64_insn, ctx); 1512 } else { 1513 emit_a64_mov_i(is64, tmp, imm, ctx); 1514 emit(A64_ORR(is64, dst, dst, tmp), ctx); 1515 } 1516 break; 1517 case BPF_ALU | BPF_XOR | BPF_K: 1518 case BPF_ALU64 | BPF_XOR | BPF_K: 1519 a64_insn = A64_EOR_I(is64, dst, dst, imm); 1520 if (a64_insn != AARCH64_BREAK_FAULT) { 1521 emit(a64_insn, ctx); 1522 } else { 1523 emit_a64_mov_i(is64, tmp, imm, ctx); 1524 emit(A64_EOR(is64, dst, dst, tmp), ctx); 1525 } 1526 break; 1527 case BPF_ALU | BPF_MUL | BPF_K: 1528 case BPF_ALU64 | BPF_MUL | BPF_K: 1529 emit_a64_mov_i(is64, tmp, imm, ctx); 1530 emit(A64_MUL(is64, dst, dst, tmp), ctx); 1531 break; 1532 case BPF_ALU | BPF_DIV | BPF_K: 1533 case BPF_ALU64 | BPF_DIV | BPF_K: 1534 emit_a64_mov_i(is64, tmp, imm, ctx); 1535 if (!off) 1536 emit(A64_UDIV(is64, dst, dst, tmp), ctx); 1537 else 1538 emit(A64_SDIV(is64, dst, dst, tmp), ctx); 1539 break; 1540 case BPF_ALU | BPF_MOD | BPF_K: 1541 case BPF_ALU64 | BPF_MOD | BPF_K: 1542 emit_a64_mov_i(is64, tmp2, imm, ctx); 1543 if (!off) 1544 emit(A64_UDIV(is64, tmp, dst, tmp2), ctx); 1545 else 1546 emit(A64_SDIV(is64, tmp, dst, tmp2), ctx); 1547 emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx); 1548 break; 1549 case BPF_ALU | BPF_LSH | BPF_K: 1550 case BPF_ALU64 | BPF_LSH | BPF_K: 1551 emit(A64_LSL(is64, dst, dst, imm), ctx); 1552 break; 1553 case BPF_ALU | BPF_RSH | BPF_K: 1554 case BPF_ALU64 | BPF_RSH | BPF_K: 1555 emit(A64_LSR(is64, dst, dst, imm), ctx); 1556 break; 1557 case BPF_ALU | BPF_ARSH | BPF_K: 1558 case BPF_ALU64 | BPF_ARSH | BPF_K: 1559 emit(A64_ASR(is64, dst, dst, imm), ctx); 1560 break; 1561 1562 /* JUMP reg */ 1563 case BPF_JMP | BPF_JA | BPF_X: 1564 emit(A64_BR(dst), ctx); 1565 break; 1566 /* JUMP off */ 1567 case BPF_JMP | BPF_JA: 1568 case BPF_JMP32 | BPF_JA: 1569 if (BPF_CLASS(code) == BPF_JMP) 1570 jmp_offset = bpf2a64_offset(i, off, ctx); 1571 else 1572 jmp_offset = bpf2a64_offset(i, imm, ctx); 1573 check_imm26(jmp_offset); 1574 emit(A64_B(jmp_offset), ctx); 1575 break; 1576 /* IF (dst COND src) JUMP off */ 1577 case BPF_JMP | BPF_JEQ | BPF_X: 1578 case BPF_JMP | BPF_JGT | BPF_X: 1579 case BPF_JMP | BPF_JLT | BPF_X: 1580 case BPF_JMP | BPF_JGE | BPF_X: 1581 case BPF_JMP | BPF_JLE | BPF_X: 1582 case BPF_JMP | BPF_JNE | BPF_X: 1583 case BPF_JMP | BPF_JSGT | BPF_X: 1584 case BPF_JMP | BPF_JSLT | BPF_X: 1585 case BPF_JMP | BPF_JSGE | BPF_X: 1586 case BPF_JMP | BPF_JSLE | BPF_X: 1587 case BPF_JMP32 | BPF_JEQ | BPF_X: 1588 case BPF_JMP32 | BPF_JGT | BPF_X: 1589 case BPF_JMP32 | BPF_JLT | BPF_X: 1590 case BPF_JMP32 | BPF_JGE | BPF_X: 1591 case BPF_JMP32 | BPF_JLE | BPF_X: 1592 case BPF_JMP32 | BPF_JNE | BPF_X: 1593 case BPF_JMP32 | BPF_JSGT | BPF_X: 1594 case BPF_JMP32 | BPF_JSLT | BPF_X: 1595 case BPF_JMP32 | BPF_JSGE | BPF_X: 1596 case BPF_JMP32 | BPF_JSLE | BPF_X: 1597 emit(A64_CMP(is64, dst, src), ctx); 1598 emit_cond_jmp: 1599 jmp_offset = bpf2a64_offset(i, off, ctx); 1600 check_imm19(jmp_offset); 1601 switch (BPF_OP(code)) { 1602 case BPF_JEQ: 1603 jmp_cond = A64_COND_EQ; 1604 break; 1605 case BPF_JGT: 1606 jmp_cond = A64_COND_HI; 1607 break; 1608 case BPF_JLT: 1609 jmp_cond = A64_COND_CC; 1610 break; 1611 case BPF_JGE: 1612 jmp_cond = A64_COND_CS; 1613 break; 1614 case BPF_JLE: 1615 jmp_cond = A64_COND_LS; 1616 break; 1617 case BPF_JSET: 1618 case BPF_JNE: 1619 jmp_cond = A64_COND_NE; 1620 break; 1621 case BPF_JSGT: 1622 jmp_cond = A64_COND_GT; 1623 break; 1624 case BPF_JSLT: 1625 jmp_cond = A64_COND_LT; 1626 break; 1627 case BPF_JSGE: 1628 jmp_cond = A64_COND_GE; 1629 break; 1630 case BPF_JSLE: 1631 jmp_cond = A64_COND_LE; 1632 break; 1633 default: 1634 return -EFAULT; 1635 } 1636 emit(A64_B_(jmp_cond, jmp_offset), ctx); 1637 break; 1638 case BPF_JMP | BPF_JSET | BPF_X: 1639 case BPF_JMP32 | BPF_JSET | BPF_X: 1640 emit(A64_TST(is64, dst, src), ctx); 1641 goto emit_cond_jmp; 1642 /* IF (dst COND imm) JUMP off */ 1643 case BPF_JMP | BPF_JEQ | BPF_K: 1644 case BPF_JMP | BPF_JGT | BPF_K: 1645 case BPF_JMP | BPF_JLT | BPF_K: 1646 case BPF_JMP | BPF_JGE | BPF_K: 1647 case BPF_JMP | BPF_JLE | BPF_K: 1648 case BPF_JMP | BPF_JNE | BPF_K: 1649 case BPF_JMP | BPF_JSGT | BPF_K: 1650 case BPF_JMP | BPF_JSLT | BPF_K: 1651 case BPF_JMP | BPF_JSGE | BPF_K: 1652 case BPF_JMP | BPF_JSLE | BPF_K: 1653 case BPF_JMP32 | BPF_JEQ | BPF_K: 1654 case BPF_JMP32 | BPF_JGT | BPF_K: 1655 case BPF_JMP32 | BPF_JLT | BPF_K: 1656 case BPF_JMP32 | BPF_JGE | BPF_K: 1657 case BPF_JMP32 | BPF_JLE | BPF_K: 1658 case BPF_JMP32 | BPF_JNE | BPF_K: 1659 case BPF_JMP32 | BPF_JSGT | BPF_K: 1660 case BPF_JMP32 | BPF_JSLT | BPF_K: 1661 case BPF_JMP32 | BPF_JSGE | BPF_K: 1662 case BPF_JMP32 | BPF_JSLE | BPF_K: 1663 if (is_addsub_imm(imm)) { 1664 emit(A64_CMP_I(is64, dst, imm), ctx); 1665 } else if (is_addsub_imm(-(u32)imm)) { 1666 emit(A64_CMN_I(is64, dst, -imm), ctx); 1667 } else { 1668 emit_a64_mov_i(is64, tmp, imm, ctx); 1669 emit(A64_CMP(is64, dst, tmp), ctx); 1670 } 1671 goto emit_cond_jmp; 1672 case BPF_JMP | BPF_JSET | BPF_K: 1673 case BPF_JMP32 | BPF_JSET | BPF_K: 1674 a64_insn = A64_TST_I(is64, dst, imm); 1675 if (a64_insn != AARCH64_BREAK_FAULT) { 1676 emit(a64_insn, ctx); 1677 } else { 1678 emit_a64_mov_i(is64, tmp, imm, ctx); 1679 emit(A64_TST(is64, dst, tmp), ctx); 1680 } 1681 goto emit_cond_jmp; 1682 /* function call */ 1683 case BPF_JMP | BPF_CALL: 1684 { 1685 const u8 r0 = bpf2a64[BPF_REG_0]; 1686 bool func_addr_fixed; 1687 u64 func_addr; 1688 u32 cpu_offset; 1689 1690 /* Implement helper call to bpf_get_smp_processor_id() inline */ 1691 if (insn->src_reg == 0 && insn->imm == BPF_FUNC_get_smp_processor_id) { 1692 cpu_offset = offsetof(struct thread_info, cpu); 1693 1694 emit(A64_MRS_SP_EL0(tmp), ctx); 1695 if (is_lsi_offset(cpu_offset, 2)) { 1696 emit(A64_LDR32I(r0, tmp, cpu_offset), ctx); 1697 } else { 1698 emit_a64_mov_i(1, tmp2, cpu_offset, ctx); 1699 emit(A64_LDR32(r0, tmp, tmp2), ctx); 1700 } 1701 break; 1702 } 1703 1704 /* Implement helper call to bpf_get_current_task/_btf() inline */ 1705 if (insn->src_reg == 0 && (insn->imm == BPF_FUNC_get_current_task || 1706 insn->imm == BPF_FUNC_get_current_task_btf)) { 1707 emit(A64_MRS_SP_EL0(r0), ctx); 1708 break; 1709 } 1710 1711 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1712 &func_addr, &func_addr_fixed); 1713 if (ret < 0) 1714 return ret; 1715 if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) { 1716 ret = emit_kfunc_arena_args(ctx, insn); 1717 if (ret < 0) 1718 return ret; 1719 } 1720 emit_call(func_addr, ctx); 1721 /* 1722 * Call to arch_bpf_timed_may_goto() is emitted by the 1723 * verifier and called with custom calling convention with 1724 * first argument and return value in BPF_REG_AX (x9). 1725 */ 1726 if (func_addr != (u64)arch_bpf_timed_may_goto) 1727 emit(A64_MOV(1, r0, A64_R(0)), ctx); 1728 break; 1729 } 1730 /* tail call */ 1731 case BPF_JMP | BPF_TAIL_CALL: 1732 if (emit_bpf_tail_call(ctx)) 1733 return -EFAULT; 1734 break; 1735 /* function return */ 1736 case BPF_JMP | BPF_EXIT: 1737 /* Optimization: when last instruction is EXIT, 1738 simply fallthrough to epilogue. */ 1739 if (i == ctx->prog->len - 1) 1740 break; 1741 jmp_offset = epilogue_offset(ctx); 1742 check_imm26(jmp_offset); 1743 emit(A64_B(jmp_offset), ctx); 1744 break; 1745 1746 /* dst = imm64 */ 1747 case BPF_LD | BPF_IMM | BPF_DW: 1748 { 1749 const struct bpf_insn insn1 = insn[1]; 1750 u64 imm64; 1751 1752 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1753 if (bpf_pseudo_func(insn)) 1754 emit_addr_mov_i64(dst, imm64, ctx); 1755 else 1756 emit_a64_mov_i64(dst, imm64, ctx); 1757 1758 return 1; 1759 } 1760 1761 /* LDX: dst = (u64)*(unsigned size *)(src + off) */ 1762 case BPF_LDX | BPF_MEM | BPF_W: 1763 case BPF_LDX | BPF_MEM | BPF_H: 1764 case BPF_LDX | BPF_MEM | BPF_B: 1765 case BPF_LDX | BPF_MEM | BPF_DW: 1766 if (insn->src_reg == BPF_REG_PARAMS) { 1767 emit_stack_arg_load(dst, off, ctx); 1768 break; 1769 } 1770 fallthrough; 1771 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1772 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1773 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1774 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1775 /* LDXS: dst_reg = (s64)*(signed size *)(src_reg + off) */ 1776 case BPF_LDX | BPF_MEMSX | BPF_B: 1777 case BPF_LDX | BPF_MEMSX | BPF_H: 1778 case BPF_LDX | BPF_MEMSX | BPF_W: 1779 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1780 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1781 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1782 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1783 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1784 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1785 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1786 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B: 1787 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H: 1788 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W: 1789 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32 || 1790 BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) { 1791 emit(A64_ADD(1, tmp2, src, arena_vm_base), ctx); 1792 src = tmp2; 1793 } 1794 if (src == fp) { 1795 src_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1796 off_adj = off + ctx->stack_size; 1797 if (!ctx->priv_sp_used) 1798 off_adj += ctx->stack_arg_size; 1799 } else { 1800 src_adj = src; 1801 off_adj = off; 1802 } 1803 sign_extend = (BPF_MODE(insn->code) == BPF_MEMSX || 1804 BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 1805 BPF_MODE(insn->code) == BPF_PROBE_MEM32SX); 1806 switch (BPF_SIZE(code)) { 1807 case BPF_W: 1808 if (is_lsi_offset(off_adj, 2)) { 1809 if (sign_extend) 1810 emit(A64_LDRSWI(dst, src_adj, off_adj), ctx); 1811 else 1812 emit(A64_LDR32I(dst, src_adj, off_adj), ctx); 1813 } else { 1814 emit_a64_mov_i(1, tmp, off, ctx); 1815 if (sign_extend) 1816 emit(A64_LDRSW(dst, src, tmp), ctx); 1817 else 1818 emit(A64_LDR32(dst, src, tmp), ctx); 1819 } 1820 break; 1821 case BPF_H: 1822 if (is_lsi_offset(off_adj, 1)) { 1823 if (sign_extend) 1824 emit(A64_LDRSHI(dst, src_adj, off_adj), ctx); 1825 else 1826 emit(A64_LDRHI(dst, src_adj, off_adj), ctx); 1827 } else { 1828 emit_a64_mov_i(1, tmp, off, ctx); 1829 if (sign_extend) 1830 emit(A64_LDRSH(dst, src, tmp), ctx); 1831 else 1832 emit(A64_LDRH(dst, src, tmp), ctx); 1833 } 1834 break; 1835 case BPF_B: 1836 if (is_lsi_offset(off_adj, 0)) { 1837 if (sign_extend) 1838 emit(A64_LDRSBI(dst, src_adj, off_adj), ctx); 1839 else 1840 emit(A64_LDRBI(dst, src_adj, off_adj), ctx); 1841 } else { 1842 emit_a64_mov_i(1, tmp, off, ctx); 1843 if (sign_extend) 1844 emit(A64_LDRSB(dst, src, tmp), ctx); 1845 else 1846 emit(A64_LDRB(dst, src, tmp), ctx); 1847 } 1848 break; 1849 case BPF_DW: 1850 if (is_lsi_offset(off_adj, 3)) { 1851 emit(A64_LDR64I(dst, src_adj, off_adj), ctx); 1852 } else { 1853 emit_a64_mov_i(1, tmp, off, ctx); 1854 emit(A64_LDR64(dst, src, tmp), ctx); 1855 } 1856 break; 1857 } 1858 1859 ret = add_exception_handler(insn, ctx, dst); 1860 if (ret) 1861 return ret; 1862 break; 1863 1864 /* speculation barrier against v1 and v4 */ 1865 case BPF_ST | BPF_NOSPEC: 1866 if (alternative_has_cap_likely(ARM64_HAS_SB)) { 1867 emit(A64_SB, ctx); 1868 } else { 1869 emit(A64_DSB_NSH, ctx); 1870 emit(A64_ISB, ctx); 1871 } 1872 break; 1873 1874 /* ST: *(size *)(dst + off) = imm */ 1875 case BPF_ST | BPF_MEM | BPF_W: 1876 case BPF_ST | BPF_MEM | BPF_H: 1877 case BPF_ST | BPF_MEM | BPF_B: 1878 case BPF_ST | BPF_MEM | BPF_DW: 1879 if (insn->dst_reg == BPF_REG_PARAMS) { 1880 emit_stack_arg_store_imm(imm, off, tmp, ctx); 1881 break; 1882 } 1883 fallthrough; 1884 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1885 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1886 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1887 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1888 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1889 emit(A64_ADD(1, tmp3, dst, arena_vm_base), ctx); 1890 dst = tmp3; 1891 } 1892 if (dst == fp) { 1893 dst_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1894 off_adj = off + ctx->stack_size; 1895 if (!ctx->priv_sp_used) 1896 off_adj += ctx->stack_arg_size; 1897 } else { 1898 dst_adj = dst; 1899 off_adj = off; 1900 } 1901 /* Load imm to a register then store it */ 1902 emit_a64_mov_i(1, tmp, imm, ctx); 1903 switch (BPF_SIZE(code)) { 1904 case BPF_W: 1905 if (is_lsi_offset(off_adj, 2)) { 1906 emit(A64_STR32I(tmp, dst_adj, off_adj), ctx); 1907 } else { 1908 emit_a64_mov_i(1, tmp2, off, ctx); 1909 emit(A64_STR32(tmp, dst, tmp2), ctx); 1910 } 1911 break; 1912 case BPF_H: 1913 if (is_lsi_offset(off_adj, 1)) { 1914 emit(A64_STRHI(tmp, dst_adj, off_adj), ctx); 1915 } else { 1916 emit_a64_mov_i(1, tmp2, off, ctx); 1917 emit(A64_STRH(tmp, dst, tmp2), ctx); 1918 } 1919 break; 1920 case BPF_B: 1921 if (is_lsi_offset(off_adj, 0)) { 1922 emit(A64_STRBI(tmp, dst_adj, off_adj), ctx); 1923 } else { 1924 emit_a64_mov_i(1, tmp2, off, ctx); 1925 emit(A64_STRB(tmp, dst, tmp2), ctx); 1926 } 1927 break; 1928 case BPF_DW: 1929 if (is_lsi_offset(off_adj, 3)) { 1930 emit(A64_STR64I(tmp, dst_adj, off_adj), ctx); 1931 } else { 1932 emit_a64_mov_i(1, tmp2, off, ctx); 1933 emit(A64_STR64(tmp, dst, tmp2), ctx); 1934 } 1935 break; 1936 } 1937 1938 ret = add_exception_handler(insn, ctx, DONT_CLEAR); 1939 if (ret) 1940 return ret; 1941 break; 1942 1943 /* STX: *(size *)(dst + off) = src */ 1944 case BPF_STX | BPF_MEM | BPF_W: 1945 case BPF_STX | BPF_MEM | BPF_H: 1946 case BPF_STX | BPF_MEM | BPF_B: 1947 case BPF_STX | BPF_MEM | BPF_DW: 1948 if (insn->dst_reg == BPF_REG_PARAMS) { 1949 emit_stack_arg_store(src, off, ctx); 1950 break; 1951 } 1952 fallthrough; 1953 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1954 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1955 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1956 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1957 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1958 emit(A64_ADD(1, tmp2, dst, arena_vm_base), ctx); 1959 dst = tmp2; 1960 } 1961 if (dst == fp) { 1962 dst_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1963 off_adj = off + ctx->stack_size; 1964 if (!ctx->priv_sp_used) 1965 off_adj += ctx->stack_arg_size; 1966 } else { 1967 dst_adj = dst; 1968 off_adj = off; 1969 } 1970 switch (BPF_SIZE(code)) { 1971 case BPF_W: 1972 if (is_lsi_offset(off_adj, 2)) { 1973 emit(A64_STR32I(src, dst_adj, off_adj), ctx); 1974 } else { 1975 emit_a64_mov_i(1, tmp, off, ctx); 1976 emit(A64_STR32(src, dst, tmp), ctx); 1977 } 1978 break; 1979 case BPF_H: 1980 if (is_lsi_offset(off_adj, 1)) { 1981 emit(A64_STRHI(src, dst_adj, off_adj), ctx); 1982 } else { 1983 emit_a64_mov_i(1, tmp, off, ctx); 1984 emit(A64_STRH(src, dst, tmp), ctx); 1985 } 1986 break; 1987 case BPF_B: 1988 if (is_lsi_offset(off_adj, 0)) { 1989 emit(A64_STRBI(src, dst_adj, off_adj), ctx); 1990 } else { 1991 emit_a64_mov_i(1, tmp, off, ctx); 1992 emit(A64_STRB(src, dst, tmp), ctx); 1993 } 1994 break; 1995 case BPF_DW: 1996 if (is_lsi_offset(off_adj, 3)) { 1997 emit(A64_STR64I(src, dst_adj, off_adj), ctx); 1998 } else { 1999 emit_a64_mov_i(1, tmp, off, ctx); 2000 emit(A64_STR64(src, dst, tmp), ctx); 2001 } 2002 break; 2003 } 2004 2005 ret = add_exception_handler(insn, ctx, DONT_CLEAR); 2006 if (ret) 2007 return ret; 2008 break; 2009 2010 case BPF_STX | BPF_ATOMIC | BPF_B: 2011 case BPF_STX | BPF_ATOMIC | BPF_H: 2012 case BPF_STX | BPF_ATOMIC | BPF_W: 2013 case BPF_STX | BPF_ATOMIC | BPF_DW: 2014 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 2015 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 2016 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2017 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2018 if (bpf_atomic_is_load_store(insn)) 2019 ret = emit_atomic_ld_st(insn, ctx); 2020 else if (cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) 2021 ret = emit_lse_atomic(insn, ctx); 2022 else 2023 ret = emit_ll_sc_atomic(insn, ctx); 2024 if (ret) 2025 return ret; 2026 2027 if (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC) { 2028 /* 2029 * A load-acquire reads into dst_reg, and a read-modify-write 2030 * carrying BPF_FETCH reads the old value into src_reg, or into 2031 * r0 for a BPF_CMPXCHG. Clear that register on fault, the 2032 * remaining atomics have no destination register. 2033 */ 2034 int load_reg = bpf_atomic_load_reg(insn); 2035 2036 ret = add_exception_handler(insn, ctx, load_reg < 0 ? 2037 DONT_CLEAR : bpf2a64[load_reg]); 2038 if (ret) 2039 return ret; 2040 } 2041 break; 2042 2043 default: 2044 pr_err_once("unknown opcode %02x\n", code); 2045 return -EINVAL; 2046 } 2047 2048 return 0; 2049 } 2050 2051 static int build_body(struct bpf_verifier_env *env, struct jit_ctx *ctx, bool extra_pass) 2052 { 2053 const struct bpf_prog *prog = ctx->prog; 2054 int i; 2055 2056 /* 2057 * - offset[0] offset of the end of prologue, 2058 * start of the 1st instruction. 2059 * - offset[1] - offset of the end of 1st instruction, 2060 * start of the 2nd instruction 2061 * [....] 2062 * - offset[3] - offset of the end of 3rd instruction, 2063 * start of 4th instruction 2064 */ 2065 for (i = 0; i < prog->len; i++) { 2066 const struct bpf_insn *insn = &prog->insnsi[i]; 2067 int ret; 2068 2069 ctx->offset[i] = ctx->idx; 2070 ret = build_insn(env, insn, ctx, extra_pass); 2071 if (ret > 0) { 2072 i++; 2073 ctx->offset[i] = ctx->idx; 2074 continue; 2075 } 2076 if (ret) 2077 return ret; 2078 } 2079 /* 2080 * offset is allocated with prog->len + 1 so fill in 2081 * the last element with the offset after the last 2082 * instruction (end of program) 2083 */ 2084 ctx->offset[i] = ctx->idx; 2085 2086 return 0; 2087 } 2088 2089 static int validate_code(struct jit_ctx *ctx) 2090 { 2091 int i; 2092 2093 for (i = 0; i < ctx->idx; i++) { 2094 u32 a64_insn = le32_to_cpu(ctx->image[i]); 2095 2096 if (a64_insn == AARCH64_BREAK_FAULT) 2097 return -1; 2098 } 2099 return 0; 2100 } 2101 2102 static int validate_ctx(struct jit_ctx *ctx) 2103 { 2104 if (validate_code(ctx)) 2105 return -1; 2106 2107 if (WARN_ON_ONCE(ctx->exentry_idx != ctx->prog->aux->num_exentries)) 2108 return -1; 2109 2110 return 0; 2111 } 2112 2113 static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 2114 { 2115 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 2116 u64 *stack_ptr; 2117 2118 for_each_possible_cpu(cpu) { 2119 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 2120 stack_ptr[0] = PRIV_STACK_GUARD_VAL; 2121 stack_ptr[1] = PRIV_STACK_GUARD_VAL; 2122 stack_ptr[underflow_idx] = PRIV_STACK_GUARD_VAL; 2123 stack_ptr[underflow_idx + 1] = PRIV_STACK_GUARD_VAL; 2124 } 2125 } 2126 2127 static void priv_stack_check_guard(void __percpu *priv_stack_ptr, int alloc_size, 2128 struct bpf_prog *prog) 2129 { 2130 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 2131 u64 *stack_ptr; 2132 2133 for_each_possible_cpu(cpu) { 2134 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 2135 if (stack_ptr[0] != PRIV_STACK_GUARD_VAL || 2136 stack_ptr[1] != PRIV_STACK_GUARD_VAL || 2137 stack_ptr[underflow_idx] != PRIV_STACK_GUARD_VAL || 2138 stack_ptr[underflow_idx + 1] != PRIV_STACK_GUARD_VAL) { 2139 pr_err("BPF private stack overflow/underflow detected for prog %sx\n", 2140 bpf_jit_get_prog_name(prog)); 2141 break; 2142 } 2143 } 2144 } 2145 2146 struct arm64_jit_data { 2147 struct bpf_binary_header *header; 2148 u8 *ro_image; 2149 struct bpf_binary_header *ro_header; 2150 struct jit_ctx ctx; 2151 }; 2152 2153 struct bpf_prog *bpf_int_jit_compile(struct bpf_verifier_env *env, struct bpf_prog *prog) 2154 { 2155 int image_size, prog_size, extable_size, extable_align, extable_offset; 2156 struct bpf_binary_header *header; 2157 struct bpf_binary_header *ro_header = NULL; 2158 struct arm64_jit_data *jit_data; 2159 void __percpu *priv_stack_ptr = NULL; 2160 bool was_classic = bpf_prog_was_classic(prog); 2161 int priv_stack_alloc_sz; 2162 bool extra_pass = false; 2163 struct jit_ctx ctx; 2164 u8 *image_ptr; 2165 u8 *ro_image_ptr; 2166 int body_idx; 2167 int exentry_idx; 2168 int out_cnt; 2169 2170 if (!prog->jit_requested) 2171 return prog; 2172 2173 jit_data = prog->aux->jit_data; 2174 if (!jit_data) { 2175 jit_data = kzalloc_obj(*jit_data); 2176 if (!jit_data) 2177 return prog; 2178 prog->aux->jit_data = jit_data; 2179 } 2180 priv_stack_ptr = prog->aux->priv_stack_ptr; 2181 if (!priv_stack_ptr && prog->aux->jits_use_priv_stack) { 2182 /* Allocate actual private stack size with verifier-calculated 2183 * stack size plus two memory guards to protect overflow and 2184 * underflow. 2185 */ 2186 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 16) + 2187 2 * PRIV_STACK_GUARD_SZ; 2188 priv_stack_ptr = __alloc_percpu_gfp(priv_stack_alloc_sz, 16, GFP_KERNEL); 2189 if (!priv_stack_ptr) 2190 goto out_priv_stack; 2191 2192 priv_stack_init_guard(priv_stack_ptr, priv_stack_alloc_sz); 2193 prog->aux->priv_stack_ptr = priv_stack_ptr; 2194 } 2195 if (jit_data->ctx.offset) { 2196 ctx = jit_data->ctx; 2197 ro_image_ptr = jit_data->ro_image; 2198 ro_header = jit_data->ro_header; 2199 header = jit_data->header; 2200 image_ptr = (void *)header + ((void *)ro_image_ptr 2201 - (void *)ro_header); 2202 extra_pass = true; 2203 prog_size = sizeof(u32) * ctx.idx; 2204 goto skip_init_ctx; 2205 } 2206 memset(&ctx, 0, sizeof(ctx)); 2207 ctx.prog = prog; 2208 2209 ctx.offset = kvzalloc_objs(int, prog->len + 1); 2210 if (ctx.offset == NULL) 2211 goto out_off; 2212 2213 ctx.user_vm_start = bpf_arena_get_user_vm_start(prog->aux->arena); 2214 ctx.arena_vm_start = bpf_arena_get_kern_vm_start(prog->aux->arena); 2215 2216 out_cnt = bpf_out_stack_arg_cnt(env, prog); 2217 if (out_cnt) { 2218 int nr_on_stack = out_cnt - NR_STACK_ARG_REGS; 2219 2220 if (nr_on_stack > 0) 2221 ctx.stack_arg_size = round_up(nr_on_stack * sizeof(u64), 16); 2222 } 2223 2224 if (priv_stack_ptr) 2225 ctx.priv_sp_used = true; 2226 2227 /* Pass 1: Estimate the maximum image size. 2228 * 2229 * BPF line info needs ctx->offset[i] to be the offset of 2230 * instruction[i] in jited image, so build prologue first. 2231 */ 2232 if (build_prologue(&ctx, was_classic)) 2233 goto out_off; 2234 2235 if (build_body(env, &ctx, extra_pass)) 2236 goto out_off; 2237 2238 ctx.epilogue_offset = ctx.idx; 2239 build_epilogue(&ctx, was_classic); 2240 build_plt(&ctx); 2241 2242 extable_align = __alignof__(struct exception_table_entry); 2243 extable_size = prog->aux->num_exentries * 2244 sizeof(struct exception_table_entry); 2245 2246 /* Now we know the maximum image size. */ 2247 prog_size = sizeof(u32) * ctx.idx; 2248 /* also allocate space for plt target */ 2249 extable_offset = round_up(prog_size + PLT_TARGET_SIZE, extable_align); 2250 image_size = extable_offset + extable_size; 2251 ro_header = bpf_jit_binary_pack_alloc(image_size, &ro_image_ptr, 2252 sizeof(u64), &header, &image_ptr, 2253 jit_fill_hole, was_classic); 2254 if (!ro_header) 2255 goto out_off; 2256 2257 /* Pass 2: Determine jited position and result for each instruction */ 2258 2259 /* 2260 * Use the image(RW) for writing the JITed instructions. But also save 2261 * the ro_image(RX) for calculating the offsets in the image. The RW 2262 * image will be later copied to the RX image from where the program 2263 * will run. The bpf_jit_binary_pack_finalize() will do this copy in the 2264 * final step. 2265 */ 2266 ctx.image = (__le32 *)image_ptr; 2267 ctx.ro_image = (__le32 *)ro_image_ptr; 2268 if (extable_size) 2269 prog->aux->extable = (void *)ro_image_ptr + extable_offset; 2270 skip_init_ctx: 2271 ctx.idx = 0; 2272 ctx.exentry_idx = 0; 2273 ctx.write = true; 2274 2275 build_prologue(&ctx, was_classic); 2276 2277 /* Record exentry_idx and body_idx before first build_body */ 2278 exentry_idx = ctx.exentry_idx; 2279 body_idx = ctx.idx; 2280 /* Dont write body instructions to memory for now */ 2281 ctx.write = false; 2282 2283 if (build_body(env, &ctx, extra_pass)) 2284 goto out_free_hdr; 2285 2286 ctx.epilogue_offset = ctx.idx; 2287 ctx.exentry_idx = exentry_idx; 2288 ctx.idx = body_idx; 2289 ctx.write = true; 2290 2291 /* Pass 3: Adjust jump offset and write final image */ 2292 if (build_body(env, &ctx, extra_pass) || 2293 WARN_ON_ONCE(ctx.idx != ctx.epilogue_offset)) 2294 goto out_free_hdr; 2295 2296 build_epilogue(&ctx, was_classic); 2297 build_plt(&ctx); 2298 2299 /* Extra pass to validate JITed code. */ 2300 if (validate_ctx(&ctx)) 2301 goto out_free_hdr; 2302 2303 /* update the real prog size */ 2304 prog_size = sizeof(u32) * ctx.idx; 2305 2306 /* And we're done. */ 2307 if (bpf_jit_enable > 1) 2308 bpf_jit_dump(prog->len, prog_size, 2, ctx.image); 2309 2310 if (!prog->is_func || extra_pass) { 2311 /* The jited image may shrink since the jited result for 2312 * BPF_CALL to subprog may be changed from indirect call 2313 * to direct call. 2314 */ 2315 if (extra_pass && ctx.idx > jit_data->ctx.idx) { 2316 pr_err_once("multi-func JIT bug %d > %d\n", 2317 ctx.idx, jit_data->ctx.idx); 2318 goto out_free_hdr; 2319 } 2320 if (WARN_ON(bpf_jit_binary_pack_finalize(ro_header, header))) { 2321 /* ro_header and header has been freed */ 2322 ro_header = NULL; 2323 header = NULL; 2324 goto out_free_hdr; 2325 } 2326 } else { 2327 jit_data->ctx = ctx; 2328 jit_data->ro_image = ro_image_ptr; 2329 jit_data->header = header; 2330 jit_data->ro_header = ro_header; 2331 } 2332 2333 prog->bpf_func = (void *)ctx.ro_image + cfi_get_offset(); 2334 prog->jited = 1; 2335 prog->jited_len = prog_size - cfi_get_offset(); 2336 2337 if (!prog->is_func || extra_pass) { 2338 int i; 2339 2340 /* offset[prog->len] is the size of program */ 2341 for (i = 0; i <= prog->len; i++) 2342 ctx.offset[i] *= AARCH64_INSN_SIZE; 2343 bpf_prog_fill_jited_linfo(prog, ctx.offset + 1); 2344 /* 2345 * The bpf_prog_update_insn_ptrs function expects offsets to 2346 * point to the first byte of the jitted instruction (unlike 2347 * the bpf_prog_fill_jited_linfo above, which, for historical 2348 * reasons, expects to point to the next instruction) 2349 */ 2350 bpf_prog_update_insn_ptrs(prog, ctx.offset, ctx.ro_image); 2351 out_off: 2352 if (!ro_header && priv_stack_ptr) { 2353 free_percpu(priv_stack_ptr); 2354 prog->aux->priv_stack_ptr = NULL; 2355 } 2356 kvfree(ctx.offset); 2357 out_priv_stack: 2358 kfree(jit_data); 2359 prog->aux->jit_data = NULL; 2360 } 2361 2362 return prog; 2363 2364 out_free_hdr: 2365 if (extra_pass) { 2366 prog->bpf_func = NULL; 2367 prog->jited = 0; 2368 prog->jited_len = 0; 2369 } 2370 if (header) { 2371 bpf_arch_text_copy(&ro_header->size, &header->size, 2372 sizeof(header->size)); 2373 bpf_jit_binary_pack_free(ro_header, header); 2374 } 2375 goto out_off; 2376 } 2377 2378 bool bpf_jit_supports_private_stack(void) 2379 { 2380 return true; 2381 } 2382 2383 bool bpf_jit_supports_kfunc_call(void) 2384 { 2385 return true; 2386 } 2387 2388 bool bpf_jit_supports_stack_args(void) 2389 { 2390 return true; 2391 } 2392 2393 bool bpf_jit_supports_arena_args(void) 2394 { 2395 return true; 2396 } 2397 2398 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 2399 { 2400 if (!aarch64_insn_copy(dst, src, len)) 2401 return ERR_PTR(-EINVAL); 2402 return dst; 2403 } 2404 2405 u64 bpf_jit_alloc_exec_limit(void) 2406 { 2407 return VMALLOC_END - VMALLOC_START; 2408 } 2409 2410 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 2411 bool bpf_jit_supports_subprog_tailcalls(void) 2412 { 2413 return true; 2414 } 2415 2416 static void invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_image *im, 2417 struct bpf_tramp_node *node, int bargs_off, 2418 int retval_off, int run_ctx_off, bool save_ret) 2419 { 2420 void *skip; 2421 __le32 *branch; 2422 u64 enter_prog; 2423 u64 exit_prog; 2424 struct bpf_prog *p = node->link->prog; 2425 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2426 2427 enter_prog = (u64)bpf_trampoline_enter(p); 2428 exit_prog = (u64)bpf_trampoline_exit(p); 2429 2430 /* nop, patched to skip this prog when it is detached */ 2431 skip = ctx->ro_image + ctx->idx; 2432 emit(A64_NOP, ctx); 2433 2434 if (node->cookie == 0) { 2435 /* if cookie is zero, one instruction is enough to store it */ 2436 emit(A64_STR64I(A64_ZR, A64_SP, run_ctx_off + cookie_off), ctx); 2437 } else { 2438 emit_a64_mov_i64(A64_R(10), node->cookie, ctx); 2439 emit(A64_STR64I(A64_R(10), A64_SP, run_ctx_off + cookie_off), 2440 ctx); 2441 } 2442 2443 /* save p to callee saved register x19 to avoid loading p with mov_i64 2444 * each time. 2445 */ 2446 emit_addr_mov_i64(A64_R(19), (const u64)p, ctx); 2447 2448 /* arg1: prog */ 2449 emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); 2450 /* arg2: &run_ctx */ 2451 emit(A64_ADD_I(1, A64_R(1), A64_SP, run_ctx_off), ctx); 2452 2453 emit_call(enter_prog, ctx); 2454 2455 /* save return value to callee saved register x20 */ 2456 emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx); 2457 2458 /* if (__bpf_prog_enter(prog) == 0) 2459 * goto skip_exec_of_prog; 2460 */ 2461 branch = ctx->image + ctx->idx; 2462 emit(A64_NOP, ctx); 2463 2464 emit(A64_ADD_I(1, A64_R(0), A64_SP, bargs_off), ctx); 2465 if (!p->jited) 2466 emit_addr_mov_i64(A64_R(1), (const u64)p->insnsi, ctx); 2467 2468 emit_call((const u64)p->bpf_func, ctx); 2469 2470 if (save_ret) 2471 emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); 2472 2473 if (ctx->image) { 2474 int offset = &ctx->image[ctx->idx] - branch; 2475 *branch = cpu_to_le32(A64_CBZ(1, A64_R(0), offset)); 2476 } 2477 2478 /* arg1: prog */ 2479 emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); 2480 /* arg2: start time */ 2481 emit(A64_MOV(1, A64_R(1), A64_R(20)), ctx); 2482 /* arg3: &run_ctx */ 2483 emit(A64_ADD_I(1, A64_R(2), A64_SP, run_ctx_off), ctx); 2484 2485 emit_call(exit_prog, ctx); 2486 2487 bpf_tramp_image_add_skip(im, p, skip, ctx->ro_image + ctx->idx); 2488 } 2489 2490 static void invoke_bpf_mod_ret(struct jit_ctx *ctx, struct bpf_tramp_image *im, 2491 struct bpf_tramp_nodes *tn, int bargs_off, 2492 int retval_off, int run_ctx_off, __le32 **branches) 2493 { 2494 int i; 2495 2496 /* The first fmod_ret program will receive a garbage return value. 2497 * Set this to 0 to avoid confusing the program. 2498 */ 2499 emit(A64_STR64I(A64_ZR, A64_SP, retval_off), ctx); 2500 for (i = 0; i < tn->nr_nodes; i++) { 2501 invoke_bpf_prog(ctx, im, tn->nodes[i], bargs_off, retval_off, 2502 run_ctx_off, true); 2503 /* if (*(u64 *)(sp + retval_off) != 0) 2504 * goto do_fexit; 2505 */ 2506 emit(A64_LDR64I(A64_R(10), A64_SP, retval_off), ctx); 2507 /* Save the location of branch, and generate a nop. 2508 * This nop will be replaced with a cbnz later. 2509 */ 2510 branches[i] = ctx->image + ctx->idx; 2511 emit(A64_NOP, ctx); 2512 } 2513 } 2514 2515 struct arg_aux { 2516 /* how many args are passed through registers, the rest of the args are 2517 * passed through stack 2518 */ 2519 int args_in_regs; 2520 /* how many registers are used to pass arguments */ 2521 int regs_for_args; 2522 /* how much stack is used for additional args passed to bpf program 2523 * that did not fit in original function registers 2524 */ 2525 int bstack_for_args; 2526 /* home much stack is used for additional args passed to the 2527 * original function when called from trampoline (this one needs 2528 * arguments to be properly aligned) 2529 */ 2530 int ostack_for_args; 2531 }; 2532 2533 static int calc_arg_aux(const struct btf_func_model *m, 2534 struct arg_aux *a) 2535 { 2536 int stack_slots, nregs, slots, i; 2537 2538 /* verifier ensures m->nr_args <= MAX_BPF_FUNC_ARGS */ 2539 for (i = 0, nregs = 0; i < m->nr_args; i++) { 2540 slots = (m->arg_size[i] + 7) / 8; 2541 if (nregs + slots <= 8) /* passed through register ? */ 2542 nregs += slots; 2543 else 2544 break; 2545 } 2546 2547 a->args_in_regs = i; 2548 a->regs_for_args = nregs; 2549 a->ostack_for_args = 0; 2550 a->bstack_for_args = 0; 2551 2552 /* the rest arguments are passed through stack */ 2553 for (; i < m->nr_args; i++) { 2554 stack_slots = (m->arg_size[i] + 7) / 8; 2555 a->bstack_for_args += stack_slots * 8; 2556 a->ostack_for_args = a->ostack_for_args + stack_slots * 8; 2557 } 2558 2559 return 0; 2560 } 2561 2562 static void clear_garbage(struct jit_ctx *ctx, int reg, int effective_bytes) 2563 { 2564 if (effective_bytes) { 2565 int garbage_bits = 64 - 8 * effective_bytes; 2566 /* garbage bits are at the left end */ 2567 emit(A64_LSL(1, reg, reg, garbage_bits), ctx); 2568 emit(A64_LSR(1, reg, reg, garbage_bits), ctx); 2569 } 2570 } 2571 2572 /* 2573 * Convert an arena kernel address into the arena pointer form on its way into 2574 * the BPF ctx, dst = (u32)(src - kern_vm_start), with @base_lo holding the low 2575 * 32 bits of kern_vm_start. A nullable arg preserves NULL, tested on the full 2576 * 64-bit kernel pointer. The 32-bit subtraction both truncates and clears the 2577 * upper half, so the stored value satisfies the JIT invariant for arena 2578 * pointer registers. 2579 */ 2580 static void emit_arena_arg_conv(struct jit_ctx *ctx, u8 dst, u8 src, bool nullable, u8 base_lo) 2581 { 2582 if (nullable) { 2583 if (dst != src) 2584 emit(A64_MOV(1, dst, src), ctx); 2585 /* skip the subtraction so that NULL stays NULL */ 2586 emit(A64_CBZ(1, dst, 2), ctx); 2587 src = dst; 2588 } 2589 emit(A64_SUB(0, dst, src, base_lo), ctx); 2590 } 2591 2592 static void save_args(struct jit_ctx *ctx, int bargs_off, int oargs_off, 2593 const struct btf_func_model *m, const struct arg_aux *a, 2594 bool for_call_origin, bool is_struct_ops, u64 arena_base) 2595 { 2596 u8 tmp = bpf2a64[TMP_REG_1]; 2597 u8 base_lo = bpf2a64[TMP_REG_2]; 2598 int i, reg, doff, soff, slots; 2599 2600 /* only the low 32 bits of the base take part in the subtraction */ 2601 if (arena_base) 2602 emit_a64_mov_i(0, base_lo, (s32)(u32)arena_base, ctx); 2603 2604 /* store arguments to the stack for the bpf program, or restore 2605 * arguments from stack for the original function 2606 */ 2607 for (i = 0, reg = 0; i < a->args_in_regs; i++) { 2608 bool arena_arg = arena_base && (m->arg_flags[i] & BTF_FMODEL_ARENA_ARG); 2609 bool nullable = m->arg_flags[i] & BTF_FMODEL_NULLABLE_ARG; 2610 2611 slots = (m->arg_size[i] + 7) / 8; 2612 while (slots-- > 0) { 2613 if (for_call_origin) { 2614 emit(A64_LDR64I(reg, A64_SP, bargs_off), ctx); 2615 } else if (arena_arg) { 2616 emit_arena_arg_conv(ctx, tmp, reg, nullable, base_lo); 2617 emit(A64_STR64I(tmp, A64_SP, bargs_off), ctx); 2618 } else { 2619 emit(A64_STR64I(reg, A64_SP, bargs_off), ctx); 2620 } 2621 reg++; 2622 bargs_off += 8; 2623 } 2624 } 2625 2626 /* 2627 * On-stack arguments start above the frame(s) pushed by the trampoline 2628 * prologue. Entered through the fentry call from a traced function, the 2629 * prologue saves both the parent (FP/x9) and the traced function 2630 * (FP/LR) frames, so the arguments start at FP + 32. A struct_ops 2631 * callback is called indirectly and only the FP/LR frame is saved, so 2632 * they start at FP + 16. 2633 */ 2634 soff = is_struct_ops ? 16 : 32; 2635 doff = (for_call_origin ? oargs_off : bargs_off); 2636 2637 /* save on stack arguments */ 2638 for (i = a->args_in_regs; i < m->nr_args; i++) { 2639 bool arena_arg = arena_base && (m->arg_flags[i] & BTF_FMODEL_ARENA_ARG); 2640 bool nullable = m->arg_flags[i] & BTF_FMODEL_NULLABLE_ARG; 2641 2642 slots = (m->arg_size[i] + 7) / 8; 2643 /* verifier ensures arg_size <= 16, so slots equals 1 or 2 */ 2644 while (slots-- > 0) { 2645 emit(A64_LDR64I(tmp, A64_FP, soff), ctx); 2646 /* if there is unused space in the last slot, clear 2647 * the garbage contained in the space. 2648 */ 2649 if (slots == 0 && !for_call_origin) 2650 clear_garbage(ctx, tmp, m->arg_size[i] % 8); 2651 /* 2652 * No guard on for_call_origin here: only the indirect 2653 * trampoline is given a base, and it never calls the 2654 * original function, so arguments are never converted 2655 * on their way back out to it. See the WARN_ON_ONCE() 2656 * in prepare_trampoline(). 2657 */ 2658 if (arena_arg) 2659 emit_arena_arg_conv(ctx, tmp, tmp, nullable, base_lo); 2660 emit(A64_STR64I(tmp, A64_SP, doff), ctx); 2661 soff += 8; 2662 doff += 8; 2663 } 2664 } 2665 } 2666 2667 static void restore_args(struct jit_ctx *ctx, int bargs_off, int nregs) 2668 { 2669 int reg; 2670 2671 for (reg = 0; reg < nregs; reg++) { 2672 emit(A64_LDR64I(reg, A64_SP, bargs_off), ctx); 2673 bargs_off += 8; 2674 } 2675 } 2676 2677 static void store_func_meta(struct jit_ctx *ctx, u64 func_meta, int func_meta_off) 2678 { 2679 emit_a64_mov_i64(A64_R(10), func_meta, ctx); 2680 emit(A64_STR64I(A64_R(10), A64_SP, func_meta_off), ctx); 2681 } 2682 2683 /* Based on the x86's implementation of arch_prepare_bpf_trampoline(). 2684 * 2685 * bpf prog and function entry before bpf trampoline hooked: 2686 * mov x9, lr 2687 * nop 2688 * 2689 * bpf prog and function entry after bpf trampoline hooked: 2690 * mov x9, lr 2691 * bl <bpf_trampoline or plt> 2692 * 2693 */ 2694 static int prepare_trampoline(struct jit_ctx *ctx, struct bpf_tramp_image *im, 2695 struct bpf_tramp_nodes *tnodes, void *func_addr, 2696 const struct btf_func_model *m, 2697 const struct arg_aux *a, 2698 u32 flags) 2699 { 2700 int i; 2701 int stack_size; 2702 int retaddr_off; 2703 int regs_off; 2704 int retval_off; 2705 int bargs_off; 2706 int func_meta_off; 2707 int ip_off; 2708 int run_ctx_off; 2709 int oargs_off; 2710 int nfuncargs; 2711 struct bpf_tramp_nodes *fentry = &tnodes[BPF_TRAMP_FENTRY]; 2712 struct bpf_tramp_nodes *fexit = &tnodes[BPF_TRAMP_FEXIT]; 2713 struct bpf_tramp_nodes *fmod_ret = &tnodes[BPF_TRAMP_MODIFY_RETURN]; 2714 bool save_ret; 2715 __le32 **branches = NULL; 2716 bool is_struct_ops = is_struct_ops_tramp(fentry); 2717 int cookie_off, cookie_cnt, cookie_bargs_off; 2718 int fsession_cnt = bpf_fsession_cnt(tnodes); 2719 u64 arena_base; 2720 u64 func_meta; 2721 2722 /* 2723 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is explicitly 2724 * incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG because 2725 * @func_addr. Arena conversion relies on this: bpf_tramp_arena_base() 2726 * only returns a base for the indirect trampoline, which therefore 2727 * never calls the original function with converted arguments. 2728 */ 2729 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 2730 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 2731 2732 arena_base = bpf_tramp_arena_base(m, tnodes, flags); 2733 2734 /* trampoline stack layout: 2735 * [ parent ip ] 2736 * [ FP ] 2737 * SP + retaddr_off [ self ip ] 2738 * [ FP ] 2739 * 2740 * [ padding ] align SP to multiples of 16 2741 * 2742 * [ x20 ] callee saved reg x20 2743 * SP + regs_off [ x19 ] callee saved reg x19 2744 * 2745 * SP + retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 2746 * BPF_TRAMP_F_RET_FENTRY_RET 2747 * [ arg reg N ] 2748 * [ ... ] 2749 * SP + bargs_off [ arg reg 1 ] for bpf 2750 * 2751 * SP + func_meta_off [ regs count, etc ] 2752 * 2753 * SP + ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 2754 * 2755 * [ stack cookie N ] 2756 * [ ... ] 2757 * SP + cookie_off [ stack cookie 1 ] 2758 * 2759 * SP + run_ctx_off [ bpf_tramp_run_ctx ] 2760 * 2761 * [ stack arg N ] 2762 * [ ... ] 2763 * SP + oargs_off [ stack arg 1 ] for original func 2764 */ 2765 2766 stack_size = 0; 2767 oargs_off = stack_size; 2768 if (flags & BPF_TRAMP_F_CALL_ORIG) 2769 stack_size += a->ostack_for_args; 2770 2771 run_ctx_off = stack_size; 2772 /* room for bpf_tramp_run_ctx */ 2773 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 2774 2775 cookie_off = stack_size; 2776 /* room for session cookies */ 2777 cookie_cnt = bpf_fsession_cookie_cnt(tnodes); 2778 stack_size += cookie_cnt * 8; 2779 2780 ip_off = stack_size; 2781 /* room for IP address argument */ 2782 if (flags & BPF_TRAMP_F_IP_ARG) 2783 stack_size += 8; 2784 2785 func_meta_off = stack_size; 2786 /* room for function metadata, such as regs count */ 2787 stack_size += 8; 2788 2789 bargs_off = stack_size; 2790 /* room for args */ 2791 nfuncargs = a->regs_for_args + a->bstack_for_args / 8; 2792 stack_size += 8 * nfuncargs; 2793 2794 /* room for return value */ 2795 retval_off = stack_size; 2796 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 2797 if (save_ret) 2798 stack_size += 8; 2799 2800 /* room for callee saved registers, currently x19 and x20 are used */ 2801 regs_off = stack_size; 2802 stack_size += 16; 2803 2804 /* round up to multiples of 16 to avoid SPAlignmentFault */ 2805 stack_size = round_up(stack_size, 16); 2806 2807 /* return address locates above FP */ 2808 retaddr_off = stack_size + 8; 2809 2810 if (flags & BPF_TRAMP_F_INDIRECT) { 2811 /* 2812 * Indirect call for bpf_struct_ops 2813 */ 2814 emit_kcfi(cfi_get_func_hash(func_addr), ctx); 2815 } 2816 /* bpf trampoline may be invoked by 3 instruction types: 2817 * 1. bl, attached to bpf prog or kernel function via short jump 2818 * 2. br, attached to bpf prog or kernel function via long jump 2819 * 3. blr, working as a function pointer, used by struct_ops. 2820 * So BTI_JC should used here to support both br and blr. 2821 */ 2822 emit_bti(A64_BTI_JC, ctx); 2823 2824 /* x9 is not set for struct_ops */ 2825 if (!is_struct_ops) { 2826 /* frame for parent function */ 2827 emit(A64_PUSH(A64_FP, A64_R(9), A64_SP), ctx); 2828 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 2829 } 2830 2831 /* frame for patched function for tracing, or caller for struct_ops */ 2832 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); 2833 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 2834 2835 /* allocate stack space */ 2836 emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); 2837 2838 if (flags & BPF_TRAMP_F_IP_ARG) { 2839 /* save ip address of the traced function */ 2840 emit_addr_mov_i64(A64_R(10), (const u64)func_addr, ctx); 2841 emit(A64_STR64I(A64_R(10), A64_SP, ip_off), ctx); 2842 } 2843 2844 /* save function metadata */ 2845 func_meta = nfuncargs; 2846 store_func_meta(ctx, func_meta, func_meta_off); 2847 2848 /* save args for bpf */ 2849 save_args(ctx, bargs_off, oargs_off, m, a, false, is_struct_ops, arena_base); 2850 2851 /* save callee saved registers */ 2852 emit(A64_STR64I(A64_R(19), A64_SP, regs_off), ctx); 2853 emit(A64_STR64I(A64_R(20), A64_SP, regs_off + 8), ctx); 2854 2855 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2856 /* for the first pass, assume the worst case */ 2857 if (!ctx->image) 2858 ctx->idx += 4; 2859 else 2860 emit_a64_mov_i64(A64_R(0), (const u64)im, ctx); 2861 emit_call((const u64)__bpf_tramp_enter, ctx); 2862 } 2863 2864 if (fsession_cnt) { 2865 /* clear all the session cookies' value */ 2866 emit(A64_MOVZ(1, A64_R(10), 0, 0), ctx); 2867 for (int i = 0; i < cookie_cnt; i++) 2868 emit(A64_STR64I(A64_R(10), A64_SP, cookie_off + 8 * i), ctx); 2869 /* clear the return value to make sure fentry always gets 0 */ 2870 emit(A64_STR64I(A64_R(10), A64_SP, retval_off), ctx); 2871 } 2872 2873 cookie_bargs_off = (bargs_off - cookie_off) / 8; 2874 for (i = 0; i < fentry->nr_nodes; i++) { 2875 if (bpf_prog_calls_session_cookie(fentry->nodes[i])) { 2876 u64 meta = func_meta | (cookie_bargs_off << BPF_TRAMP_COOKIE_INDEX_SHIFT); 2877 2878 store_func_meta(ctx, meta, func_meta_off); 2879 cookie_bargs_off--; 2880 } 2881 invoke_bpf_prog(ctx, im, fentry->nodes[i], bargs_off, 2882 retval_off, run_ctx_off, 2883 flags & BPF_TRAMP_F_RET_FENTRY_RET); 2884 } 2885 2886 if (fmod_ret->nr_nodes) { 2887 branches = kcalloc(fmod_ret->nr_nodes, sizeof(__le32 *), 2888 GFP_KERNEL); 2889 if (!branches) 2890 return -ENOMEM; 2891 2892 invoke_bpf_mod_ret(ctx, im, fmod_ret, bargs_off, retval_off, 2893 run_ctx_off, branches); 2894 } 2895 2896 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2897 /* the original func takes kernel addresses, never converted ones */ 2898 save_args(ctx, bargs_off, oargs_off, m, a, true, is_struct_ops, 0); 2899 /* call original func */ 2900 emit(A64_LDR64I(A64_R(10), A64_SP, retaddr_off), ctx); 2901 emit(A64_ADR(A64_LR, AARCH64_INSN_SIZE * 2), ctx); 2902 emit(A64_RET(A64_R(10)), ctx); 2903 /* store return value */ 2904 emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); 2905 } 2906 2907 /* update the branches saved in invoke_bpf_mod_ret with cbnz */ 2908 for (i = 0; i < fmod_ret->nr_nodes && ctx->image != NULL; i++) { 2909 int offset = &ctx->image[ctx->idx] - branches[i]; 2910 *branches[i] = cpu_to_le32(A64_CBNZ(1, A64_R(10), offset)); 2911 } 2912 2913 /* set the "is_return" flag for fsession */ 2914 func_meta |= (1ULL << BPF_TRAMP_IS_RETURN_SHIFT); 2915 if (fsession_cnt) 2916 store_func_meta(ctx, func_meta, func_meta_off); 2917 2918 cookie_bargs_off = (bargs_off - cookie_off) / 8; 2919 for (i = 0; i < fexit->nr_nodes; i++) { 2920 if (bpf_prog_calls_session_cookie(fexit->nodes[i])) { 2921 u64 meta = func_meta | (cookie_bargs_off << BPF_TRAMP_COOKIE_INDEX_SHIFT); 2922 2923 store_func_meta(ctx, meta, func_meta_off); 2924 cookie_bargs_off--; 2925 } 2926 invoke_bpf_prog(ctx, im, fexit->nodes[i], bargs_off, retval_off, 2927 run_ctx_off, false); 2928 } 2929 2930 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2931 /* for the first pass, assume the worst case */ 2932 if (!ctx->image) 2933 ctx->idx += 4; 2934 else 2935 emit_a64_mov_i64(A64_R(0), (const u64)im, ctx); 2936 emit_call((const u64)__bpf_tramp_exit, ctx); 2937 } 2938 2939 if (flags & BPF_TRAMP_F_RESTORE_REGS) 2940 restore_args(ctx, bargs_off, a->regs_for_args); 2941 2942 /* restore callee saved register x19 and x20 */ 2943 emit(A64_LDR64I(A64_R(19), A64_SP, regs_off), ctx); 2944 emit(A64_LDR64I(A64_R(20), A64_SP, regs_off + 8), ctx); 2945 2946 if (save_ret) 2947 emit(A64_LDR64I(A64_R(0), A64_SP, retval_off), ctx); 2948 2949 /* reset SP */ 2950 emit(A64_MOV(1, A64_SP, A64_FP), ctx); 2951 2952 if (is_struct_ops) { 2953 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 2954 emit(A64_RET(A64_LR), ctx); 2955 } else { 2956 /* pop frames */ 2957 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 2958 emit(A64_POP(A64_FP, A64_R(9), A64_SP), ctx); 2959 2960 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 2961 /* skip patched function, return to parent */ 2962 emit(A64_MOV(1, A64_LR, A64_R(9)), ctx); 2963 emit(A64_RET(A64_R(9)), ctx); 2964 } else { 2965 /* return to patched function */ 2966 emit(A64_MOV(1, A64_R(10), A64_LR), ctx); 2967 emit(A64_MOV(1, A64_LR, A64_R(9)), ctx); 2968 emit(A64_RET(A64_R(10)), ctx); 2969 } 2970 } 2971 2972 kfree(branches); 2973 2974 return ctx->idx; 2975 } 2976 2977 bool bpf_jit_supports_fsession(void) 2978 { 2979 return true; 2980 } 2981 2982 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 2983 struct bpf_tramp_nodes *tnodes, void *func_addr) 2984 { 2985 struct jit_ctx ctx = { 2986 .image = NULL, 2987 .idx = 0, 2988 }; 2989 struct bpf_tramp_image im = {}; 2990 struct arg_aux aaux; 2991 int ret; 2992 2993 ret = calc_arg_aux(m, &aaux); 2994 if (ret < 0) 2995 return ret; 2996 2997 ret = prepare_trampoline(&ctx, &im, tnodes, func_addr, m, &aaux, flags); 2998 if (ret < 0) 2999 return ret; 3000 3001 return ret < 0 ? ret : ret * AARCH64_INSN_SIZE; 3002 } 3003 3004 void *arch_alloc_bpf_trampoline(unsigned int size) 3005 { 3006 return bpf_prog_pack_alloc(size, jit_fill_hole, false); 3007 } 3008 3009 void arch_free_bpf_trampoline(void *image, unsigned int size) 3010 { 3011 bpf_prog_pack_free(image, size); 3012 } 3013 3014 int arch_protect_bpf_trampoline(void *image, unsigned int size) 3015 { 3016 return 0; 3017 } 3018 3019 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image, 3020 void *ro_image_end, const struct btf_func_model *m, 3021 u32 flags, struct bpf_tramp_nodes *tnodes, 3022 void *func_addr) 3023 { 3024 u32 size = ro_image_end - ro_image; 3025 struct arg_aux aaux; 3026 void *image, *tmp; 3027 int ret; 3028 3029 /* image doesn't need to be in module memory range, so we can 3030 * use kvmalloc. 3031 */ 3032 image = kvmalloc(size, GFP_KERNEL); 3033 if (!image) 3034 return -ENOMEM; 3035 3036 struct jit_ctx ctx = { 3037 .image = image, 3038 .ro_image = ro_image, 3039 .idx = 0, 3040 .write = true, 3041 }; 3042 3043 3044 jit_fill_hole(image, (unsigned int)(ro_image_end - ro_image)); 3045 ret = calc_arg_aux(m, &aaux); 3046 if (ret) 3047 goto out; 3048 ret = prepare_trampoline(&ctx, im, tnodes, func_addr, m, &aaux, flags); 3049 3050 if (ret > 0 && validate_code(&ctx) < 0) { 3051 ret = -EINVAL; 3052 goto out; 3053 } 3054 3055 if (ret > 0) 3056 ret *= AARCH64_INSN_SIZE; 3057 3058 tmp = bpf_arch_text_copy(ro_image, image, size); 3059 if (IS_ERR(tmp)) { 3060 ret = PTR_ERR(tmp); 3061 goto out; 3062 } 3063 3064 out: 3065 kvfree(image); 3066 return ret; 3067 } 3068 3069 static bool is_long_jump(void *ip, void *target) 3070 { 3071 long offset; 3072 3073 /* NULL target means this is a NOP */ 3074 if (!target) 3075 return false; 3076 3077 offset = (long)target - (long)ip; 3078 return offset < -SZ_128M || offset >= SZ_128M; 3079 } 3080 3081 static int gen_branch_or_nop(enum aarch64_insn_branch_type type, void *ip, 3082 void *addr, void *plt, u32 *insn) 3083 { 3084 void *target; 3085 3086 if (!addr) { 3087 *insn = aarch64_insn_gen_nop(); 3088 return 0; 3089 } 3090 3091 if (is_long_jump(ip, addr)) 3092 target = plt; 3093 else 3094 target = addr; 3095 3096 *insn = aarch64_insn_gen_branch_imm((unsigned long)ip, 3097 (unsigned long)target, 3098 type); 3099 3100 return *insn != AARCH64_BREAK_FAULT ? 0 : -EFAULT; 3101 } 3102 3103 /* Replace the branch instruction from @ip to @old_addr in a bpf prog or a bpf 3104 * trampoline with the branch instruction from @ip to @new_addr. If @old_addr 3105 * or @new_addr is NULL, the old or new instruction is NOP. 3106 * 3107 * When @ip is the bpf prog entry, a bpf trampoline is being attached or 3108 * detached. Since bpf trampoline and bpf prog are allocated separately with 3109 * vmalloc, the address distance may exceed 128MB, the maximum branch range. 3110 * So long jump should be handled. 3111 * 3112 * When a bpf prog is constructed, a plt pointing to empty trampoline 3113 * dummy_tramp is placed at the end: 3114 * 3115 * bpf_prog: 3116 * mov x9, lr 3117 * nop // patchsite 3118 * ... 3119 * ret 3120 * 3121 * plt: 3122 * ldr x10, target 3123 * br x10 3124 * target: 3125 * .quad dummy_tramp // plt target 3126 * 3127 * This is also the state when no trampoline is attached. 3128 * 3129 * When a short-jump bpf trampoline is attached, the patchsite is patched 3130 * to a bl instruction to the trampoline directly: 3131 * 3132 * bpf_prog: 3133 * mov x9, lr 3134 * bl <short-jump bpf trampoline address> // patchsite 3135 * ... 3136 * ret 3137 * 3138 * plt: 3139 * ldr x10, target 3140 * br x10 3141 * target: 3142 * .quad dummy_tramp // plt target 3143 * 3144 * When a long-jump bpf trampoline is attached, the plt target is filled with 3145 * the trampoline address and the patchsite is patched to a bl instruction to 3146 * the plt: 3147 * 3148 * bpf_prog: 3149 * mov x9, lr 3150 * bl plt // patchsite 3151 * ... 3152 * ret 3153 * 3154 * plt: 3155 * ldr x10, target 3156 * br x10 3157 * target: 3158 * .quad <long-jump bpf trampoline address> // plt target 3159 * 3160 * The dummy_tramp is used to prevent another CPU from jumping to unknown 3161 * locations during the patching process, making the patching process easier. 3162 */ 3163 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type old_t, 3164 enum bpf_text_poke_type new_t, void *old_addr, 3165 void *new_addr) 3166 { 3167 int ret; 3168 u32 old_insn; 3169 u32 new_insn; 3170 u32 replaced; 3171 struct bpf_plt *plt = NULL; 3172 unsigned long size = 0UL; 3173 unsigned long offset = ~0UL; 3174 enum aarch64_insn_branch_type branch_type; 3175 char namebuf[KSYM_NAME_LEN]; 3176 void *image = NULL; 3177 u64 plt_target = 0ULL; 3178 bool poking_bpf_entry; 3179 3180 if (!bpf_address_lookup((unsigned long)ip, &size, &offset, namebuf)) 3181 /* Only poking bpf text is supported. Since kernel function 3182 * entry is set up by ftrace, we reply on ftrace to poke kernel 3183 * functions. 3184 */ 3185 return -ENOTSUPP; 3186 3187 image = ip - offset; 3188 /* zero offset means we're poking bpf prog entry */ 3189 poking_bpf_entry = (offset == 0UL); 3190 3191 /* bpf prog entry, find plt and the real patchsite */ 3192 if (poking_bpf_entry) { 3193 /* plt locates at the end of bpf prog */ 3194 plt = image + size - PLT_TARGET_OFFSET; 3195 3196 /* skip to the nop instruction in bpf prog entry: 3197 * bti c // if BTI enabled 3198 * mov x9, x30 3199 * nop 3200 */ 3201 ip = image + POKE_OFFSET * AARCH64_INSN_SIZE; 3202 } 3203 3204 /* long jump is only possible at bpf prog entry */ 3205 if (WARN_ON((is_long_jump(ip, new_addr) || is_long_jump(ip, old_addr)) && 3206 !poking_bpf_entry)) 3207 return -EINVAL; 3208 3209 branch_type = old_t == BPF_MOD_CALL ? AARCH64_INSN_BRANCH_LINK : 3210 AARCH64_INSN_BRANCH_NOLINK; 3211 if (gen_branch_or_nop(branch_type, ip, old_addr, plt, &old_insn) < 0) 3212 return -EFAULT; 3213 3214 branch_type = new_t == BPF_MOD_CALL ? AARCH64_INSN_BRANCH_LINK : 3215 AARCH64_INSN_BRANCH_NOLINK; 3216 if (gen_branch_or_nop(branch_type, ip, new_addr, plt, &new_insn) < 0) 3217 return -EFAULT; 3218 3219 if (is_long_jump(ip, new_addr)) 3220 plt_target = (u64)new_addr; 3221 else if (is_long_jump(ip, old_addr)) 3222 /* if the old target is a long jump and the new target is not, 3223 * restore the plt target to dummy_tramp, so there is always a 3224 * legal and harmless address stored in plt target, and we'll 3225 * never jump from plt to an unknown place. 3226 */ 3227 plt_target = (u64)&dummy_tramp; 3228 3229 if (plt_target) { 3230 /* non-zero plt_target indicates we're patching a bpf prog, 3231 * which is read only. 3232 */ 3233 if (set_memory_rw(PAGE_MASK & ((uintptr_t)&plt->target), 1)) 3234 return -EFAULT; 3235 WRITE_ONCE(plt->target, plt_target); 3236 set_memory_ro(PAGE_MASK & ((uintptr_t)&plt->target), 1); 3237 /* since plt target points to either the new trampoline 3238 * or dummy_tramp, even if another CPU reads the old plt 3239 * target value before fetching the bl instruction to plt, 3240 * it will be brought back by dummy_tramp, so no barrier is 3241 * required here. 3242 */ 3243 } 3244 3245 /* if the old target and the new target are both long jumps, no 3246 * patching is required 3247 */ 3248 if (old_insn == new_insn) 3249 return 0; 3250 3251 mutex_lock(&text_mutex); 3252 if (aarch64_insn_read(ip, &replaced)) { 3253 ret = -EFAULT; 3254 goto out; 3255 } 3256 3257 if (replaced != old_insn) { 3258 ret = -EFAULT; 3259 goto out; 3260 } 3261 3262 /* We call aarch64_insn_patch_text_nosync() to replace instruction 3263 * atomically, so no other CPUs will fetch a half-new and half-old 3264 * instruction. But there is chance that another CPU executes the 3265 * old instruction after the patching operation finishes (e.g., 3266 * pipeline not flushed, or icache not synchronized yet). 3267 * 3268 * 1. when a new trampoline is attached, it is not a problem for 3269 * different CPUs to jump to different trampolines temporarily. 3270 * 3271 * 2. when an old trampoline is freed, we should wait for all other 3272 * CPUs to exit the trampoline and make sure the trampoline is no 3273 * longer reachable, since bpf_tramp_image_put() function already 3274 * uses percpu_ref and task-based rcu to do the sync, no need to call 3275 * the sync version here, see bpf_tramp_image_put() for details. 3276 * 3277 * 3. when a detached prog is patched out of a trampoline, a CPU that 3278 * still executes the old nop calls the prog before it went through 3279 * a quiescent state, and the prog is freed after grace periods. 3280 */ 3281 ret = aarch64_insn_patch_text_nosync(ip, new_insn); 3282 out: 3283 mutex_unlock(&text_mutex); 3284 3285 return ret; 3286 } 3287 3288 bool bpf_jit_supports_ptr_xchg(void) 3289 { 3290 return true; 3291 } 3292 3293 bool bpf_jit_supports_exceptions(void) 3294 { 3295 /* We unwind through both kernel frames starting from within bpf_throw 3296 * call and BPF frames. Therefore we require FP unwinder to be enabled 3297 * to walk kernel frames and reach BPF frames in the stack trace. 3298 * ARM64 kernel is always compiled with CONFIG_FRAME_POINTER=y 3299 */ 3300 return true; 3301 } 3302 3303 bool bpf_jit_supports_arena(void) 3304 { 3305 return true; 3306 } 3307 3308 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 3309 { 3310 if (!in_arena) 3311 return true; 3312 switch (insn->code) { 3313 case BPF_STX | BPF_ATOMIC | BPF_W: 3314 case BPF_STX | BPF_ATOMIC | BPF_DW: 3315 if (!bpf_atomic_is_load_store(insn) && 3316 !cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) 3317 return false; 3318 } 3319 return true; 3320 } 3321 3322 bool bpf_jit_supports_percpu_insn(void) 3323 { 3324 return true; 3325 } 3326 3327 bool bpf_jit_bypass_spec_v4(void) 3328 { 3329 /* In case of arm64, we rely on the firmware mitigation of Speculative 3330 * Store Bypass as controlled via the ssbd kernel parameter. Whenever 3331 * the mitigation is enabled, it works for all of the kernel code with 3332 * no need to provide any additional instructions. Therefore, skip 3333 * inserting nospec insns against Spectre v4. 3334 */ 3335 return true; 3336 } 3337 3338 bool bpf_jit_supports_timed_may_goto(void) 3339 { 3340 return true; 3341 } 3342 3343 bool bpf_jit_inlines_helper_call(s32 imm) 3344 { 3345 switch (imm) { 3346 case BPF_FUNC_get_smp_processor_id: 3347 case BPF_FUNC_get_current_task: 3348 case BPF_FUNC_get_current_task_btf: 3349 return true; 3350 default: 3351 return false; 3352 } 3353 } 3354 3355 void bpf_jit_free(struct bpf_prog *prog) 3356 { 3357 if (prog->jited) { 3358 struct arm64_jit_data *jit_data = prog->aux->jit_data; 3359 struct bpf_binary_header *hdr; 3360 void __percpu *priv_stack_ptr; 3361 int priv_stack_alloc_sz; 3362 3363 /* 3364 * If we fail the final pass of JIT (from jit_subprogs), 3365 * the program may not be finalized yet. Call finalize here 3366 * before freeing it. 3367 */ 3368 if (jit_data) { 3369 bpf_jit_binary_pack_finalize(jit_data->ro_header, jit_data->header); 3370 kfree(jit_data); 3371 } 3372 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3373 hdr = bpf_jit_binary_pack_hdr(prog); 3374 bpf_jit_binary_pack_free(hdr, NULL); 3375 priv_stack_ptr = prog->aux->priv_stack_ptr; 3376 if (priv_stack_ptr) { 3377 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 16) + 3378 2 * PRIV_STACK_GUARD_SZ; 3379 priv_stack_check_guard(priv_stack_ptr, priv_stack_alloc_sz, prog); 3380 free_percpu(prog->aux->priv_stack_ptr); 3381 } 3382 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3383 } 3384 3385 bpf_prog_unlock_free(prog); 3386 } 3387