1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler for ARM64 4 * 5 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "bpf_jit: " fmt 9 10 #include <linux/arm-smccc.h> 11 #include <linux/bitfield.h> 12 #include <linux/bpf.h> 13 #include <linux/cfi.h> 14 #include <linux/filter.h> 15 #include <linux/memory.h> 16 #include <linux/printk.h> 17 #include <linux/slab.h> 18 19 #include <asm/asm-extable.h> 20 #include <asm/byteorder.h> 21 #include <asm/cpufeature.h> 22 #include <asm/debug-monitors.h> 23 #include <asm/insn.h> 24 #include <asm/text-patching.h> 25 #include <asm/set_memory.h> 26 27 #include "bpf_jit.h" 28 29 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) 30 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) 31 #define TCCNT_PTR (MAX_BPF_JIT_REG + 2) 32 #define TMP_REG_3 (MAX_BPF_JIT_REG + 3) 33 #define PRIVATE_SP (MAX_BPF_JIT_REG + 4) 34 #define ARENA_VM_START (MAX_BPF_JIT_REG + 5) 35 36 #define check_imm(bits, imm) do { \ 37 if ((((imm) > 0) && ((imm) >> ((bits) - 1))) || \ 38 (((imm) < 0) && (~(imm) >> ((bits) - 1)))) { \ 39 pr_info("[%2d] imm=%d(0x%x) out of range\n", \ 40 i, imm, imm); \ 41 return -EINVAL; \ 42 } \ 43 } while (0) 44 #define check_imm19(imm) check_imm(19, imm) 45 #define check_imm26(imm) check_imm(26, imm) 46 47 /* Map BPF registers to A64 registers */ 48 static const int bpf2a64[] = { 49 /* return value from in-kernel function, and exit value from eBPF */ 50 [BPF_REG_0] = A64_R(8), 51 /* arguments from eBPF program to in-kernel function */ 52 [BPF_REG_1] = A64_R(0), 53 [BPF_REG_2] = A64_R(1), 54 [BPF_REG_3] = A64_R(2), 55 [BPF_REG_4] = A64_R(3), 56 [BPF_REG_5] = A64_R(4), 57 /* callee saved registers that in-kernel function will preserve */ 58 [BPF_REG_6] = A64_R(19), 59 [BPF_REG_7] = A64_R(20), 60 [BPF_REG_8] = A64_R(21), 61 [BPF_REG_9] = A64_R(22), 62 /* read-only frame pointer to access stack */ 63 [BPF_REG_FP] = A64_R(25), 64 /* temporary registers for BPF JIT */ 65 [TMP_REG_1] = A64_R(10), 66 [TMP_REG_2] = A64_R(11), 67 [TMP_REG_3] = A64_R(12), 68 /* tail_call_cnt_ptr */ 69 [TCCNT_PTR] = A64_R(26), 70 /* temporary register for blinding constants */ 71 [BPF_REG_AX] = A64_R(9), 72 /* callee saved register for private stack pointer */ 73 [PRIVATE_SP] = A64_R(27), 74 /* callee saved register for kern_vm_start address */ 75 [ARENA_VM_START] = A64_R(28), 76 }; 77 78 struct jit_ctx { 79 const struct bpf_prog *prog; 80 int idx; 81 int epilogue_offset; 82 int *offset; 83 int exentry_idx; 84 int nr_used_callee_reg; 85 u8 used_callee_reg[8]; /* r6~r9, fp, arena_vm_start */ 86 __le32 *image; 87 __le32 *ro_image; 88 u32 stack_size; 89 u16 stack_arg_size; 90 u64 user_vm_start; 91 u64 arena_vm_start; 92 bool fp_used; 93 bool priv_sp_used; 94 bool write; 95 }; 96 97 struct bpf_plt { 98 u32 insn_ldr; /* load target */ 99 u32 insn_br; /* branch to target */ 100 u64 target; /* target value */ 101 }; 102 103 #define PLT_TARGET_SIZE sizeof_field(struct bpf_plt, target) 104 #define PLT_TARGET_OFFSET offsetof(struct bpf_plt, target) 105 106 /* Memory size/value to protect private stack overflow/underflow */ 107 #define PRIV_STACK_GUARD_SZ 16 108 #define PRIV_STACK_GUARD_VAL 0xEB9F12345678eb9fULL 109 110 static inline void emit(const u32 insn, struct jit_ctx *ctx) 111 { 112 if (ctx->image != NULL && ctx->write) 113 ctx->image[ctx->idx] = cpu_to_le32(insn); 114 115 ctx->idx++; 116 } 117 118 static inline void emit_u32_data(const u32 data, struct jit_ctx *ctx) 119 { 120 if (ctx->image != NULL && ctx->write) 121 ctx->image[ctx->idx] = (__force __le32)data; 122 123 ctx->idx++; 124 } 125 126 static inline void emit_a64_mov_i(const int is64, const int reg, 127 const s32 val, struct jit_ctx *ctx) 128 { 129 u16 hi = val >> 16; 130 u16 lo = val & 0xffff; 131 132 if (hi & 0x8000) { 133 if (hi == 0xffff) { 134 emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx); 135 } else { 136 emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx); 137 if (lo != 0xffff) 138 emit(A64_MOVK(is64, reg, lo, 0), ctx); 139 } 140 } else { 141 emit(A64_MOVZ(is64, reg, lo, 0), ctx); 142 if (hi) 143 emit(A64_MOVK(is64, reg, hi, 16), ctx); 144 } 145 } 146 147 static int i64_i16_blocks(const u64 val, bool inverse) 148 { 149 return (((val >> 0) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 150 (((val >> 16) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 151 (((val >> 32) & 0xffff) != (inverse ? 0xffff : 0x0000)) + 152 (((val >> 48) & 0xffff) != (inverse ? 0xffff : 0x0000)); 153 } 154 155 static inline void emit_a64_mov_i64(const int reg, const u64 val, 156 struct jit_ctx *ctx) 157 { 158 u64 nrm_tmp = val, rev_tmp = ~val; 159 bool inverse; 160 int shift; 161 162 if (!(nrm_tmp >> 32)) 163 return emit_a64_mov_i(0, reg, (u32)val, ctx); 164 165 inverse = i64_i16_blocks(nrm_tmp, true) < i64_i16_blocks(nrm_tmp, false); 166 shift = max(round_down((inverse ? (fls64(rev_tmp) - 1) : 167 (fls64(nrm_tmp) - 1)), 16), 0); 168 if (inverse) 169 emit(A64_MOVN(1, reg, (rev_tmp >> shift) & 0xffff, shift), ctx); 170 else 171 emit(A64_MOVZ(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); 172 shift -= 16; 173 while (shift >= 0) { 174 if (((nrm_tmp >> shift) & 0xffff) != (inverse ? 0xffff : 0x0000)) 175 emit(A64_MOVK(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); 176 shift -= 16; 177 } 178 } 179 180 static inline void emit_bti(u32 insn, struct jit_ctx *ctx) 181 { 182 if (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL)) 183 emit(insn, ctx); 184 } 185 186 static inline void emit_kcfi(u32 hash, struct jit_ctx *ctx) 187 { 188 if (IS_ENABLED(CONFIG_CFI)) 189 emit_u32_data(hash, ctx); 190 } 191 192 /* 193 * Kernel addresses in the vmalloc space use at most 48 bits, and the 194 * remaining bits are guaranteed to be 0x1. So we can compose the address 195 * with a fixed length movn/movk/movk sequence. 196 */ 197 static inline void emit_addr_mov_i64(const int reg, const u64 val, 198 struct jit_ctx *ctx) 199 { 200 u64 tmp = val; 201 int shift = 0; 202 203 emit(A64_MOVN(1, reg, ~tmp & 0xffff, shift), ctx); 204 while (shift < 32) { 205 tmp >>= 16; 206 shift += 16; 207 emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx); 208 } 209 } 210 211 static bool should_emit_indirect_call(long target, const struct jit_ctx *ctx) 212 { 213 long offset; 214 215 /* when ctx->ro_image is not allocated or the target is unknown, 216 * emit indirect call 217 */ 218 if (!ctx->ro_image || !target) 219 return true; 220 221 offset = target - (long)&ctx->ro_image[ctx->idx]; 222 return offset < -SZ_128M || offset >= SZ_128M; 223 } 224 225 static void emit_direct_call(u64 target, struct jit_ctx *ctx) 226 { 227 u32 insn; 228 unsigned long pc; 229 230 pc = (unsigned long)&ctx->ro_image[ctx->idx]; 231 insn = aarch64_insn_gen_branch_imm(pc, target, AARCH64_INSN_BRANCH_LINK); 232 emit(insn, ctx); 233 } 234 235 static void emit_indirect_call(u64 target, struct jit_ctx *ctx) 236 { 237 u8 tmp; 238 239 tmp = bpf2a64[TMP_REG_1]; 240 emit_addr_mov_i64(tmp, target, ctx); 241 emit(A64_BLR(tmp), ctx); 242 } 243 244 static void emit_call(u64 target, struct jit_ctx *ctx) 245 { 246 if (should_emit_indirect_call((long)target, ctx)) 247 emit_indirect_call(target, ctx); 248 else 249 emit_direct_call(target, ctx); 250 } 251 252 static inline int bpf2a64_offset(int bpf_insn, int off, 253 const struct jit_ctx *ctx) 254 { 255 /* BPF JMP offset is relative to the next instruction */ 256 bpf_insn++; 257 /* 258 * Whereas arm64 branch instructions encode the offset 259 * from the branch itself, so we must subtract 1 from the 260 * instruction offset. 261 */ 262 return ctx->offset[bpf_insn + off] - (ctx->offset[bpf_insn] - 1); 263 } 264 265 static void jit_fill_hole(void *area, unsigned int size) 266 { 267 __le32 *ptr; 268 /* We are guaranteed to have aligned memory. */ 269 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) 270 *ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT); 271 } 272 273 int bpf_arch_text_invalidate(void *dst, size_t len) 274 { 275 if (!aarch64_insn_set(dst, AARCH64_BREAK_FAULT, len)) 276 return -EINVAL; 277 278 return 0; 279 } 280 281 static inline int epilogue_offset(const struct jit_ctx *ctx) 282 { 283 int to = ctx->epilogue_offset; 284 int from = ctx->idx; 285 286 return to - from; 287 } 288 289 static bool is_addsub_imm(u32 imm) 290 { 291 /* Either imm12 or shifted imm12. */ 292 return !(imm & ~0xfff) || !(imm & ~0xfff000); 293 } 294 295 static inline void emit_a64_add_i(const bool is64, const int dst, const int src, 296 const int tmp, const s32 imm, struct jit_ctx *ctx) 297 { 298 if (is_addsub_imm(imm)) { 299 emit(A64_ADD_I(is64, dst, src, imm), ctx); 300 } else if (is_addsub_imm(-(u32)imm)) { 301 emit(A64_SUB_I(is64, dst, src, -imm), ctx); 302 } else { 303 emit_a64_mov_i(is64, tmp, imm, ctx); 304 emit(A64_ADD(is64, dst, src, tmp), ctx); 305 } 306 } 307 308 /* 309 * There are 3 types of AArch64 LDR/STR (immediate) instruction: 310 * Post-index, Pre-index, Unsigned offset. 311 * 312 * For BPF ldr/str, the "unsigned offset" type is sufficient. 313 * 314 * "Unsigned offset" type LDR(immediate) format: 315 * 316 * 3 2 1 0 317 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 318 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 319 * |x x|1 1 1 0 0 1 0 1| imm12 | Rn | Rt | 320 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 321 * scale 322 * 323 * "Unsigned offset" type STR(immediate) format: 324 * 3 2 1 0 325 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 326 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 327 * |x x|1 1 1 0 0 1 0 0| imm12 | Rn | Rt | 328 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 329 * scale 330 * 331 * The offset is calculated from imm12 and scale in the following way: 332 * 333 * offset = (u64)imm12 << scale 334 */ 335 static bool is_lsi_offset(int offset, int scale) 336 { 337 if (offset < 0) 338 return false; 339 340 if (offset > (0xFFF << scale)) 341 return false; 342 343 if (offset & ((1 << scale) - 1)) 344 return false; 345 346 return true; 347 } 348 349 /* generated main prog prologue: 350 * bti c // if CONFIG_ARM64_BTI_KERNEL 351 * mov x9, lr 352 * nop // POKE_OFFSET 353 * paciasp // if CONFIG_ARM64_PTR_AUTH_KERNEL 354 * stp x29, lr, [sp, #-16]! 355 * mov x29, sp 356 * stp xzr, x26, [sp, #-16]! 357 * mov x26, sp 358 * // PROLOGUE_OFFSET 359 * // save callee-saved registers 360 */ 361 static void prepare_bpf_tail_call_cnt(struct jit_ctx *ctx) 362 { 363 const bool is_main_prog = !bpf_is_subprog(ctx->prog); 364 const u8 ptr = bpf2a64[TCCNT_PTR]; 365 366 if (is_main_prog) { 367 /* Initialize tail_call_cnt. */ 368 emit(A64_PUSH(A64_ZR, ptr, A64_SP), ctx); 369 emit(A64_MOV(1, ptr, A64_SP), ctx); 370 } else 371 emit(A64_PUSH(ptr, ptr, A64_SP), ctx); 372 } 373 374 static void find_used_callee_regs(struct jit_ctx *ctx) 375 { 376 int i; 377 const struct bpf_prog *prog = ctx->prog; 378 const struct bpf_insn *insn = &prog->insnsi[0]; 379 int reg_used = 0; 380 381 for (i = 0; i < prog->len; i++, insn++) { 382 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 383 reg_used |= 1; 384 385 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 386 reg_used |= 2; 387 388 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 389 reg_used |= 4; 390 391 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 392 reg_used |= 8; 393 394 if (insn->dst_reg == BPF_REG_FP || insn->src_reg == BPF_REG_FP) { 395 ctx->fp_used = true; 396 reg_used |= 16; 397 } 398 } 399 400 i = 0; 401 if (reg_used & 1) 402 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_6]; 403 404 if (reg_used & 2) 405 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_7]; 406 407 if (reg_used & 4) 408 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_8]; 409 410 if (reg_used & 8) 411 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_9]; 412 413 if (reg_used & 16) { 414 ctx->used_callee_reg[i++] = bpf2a64[BPF_REG_FP]; 415 if (ctx->priv_sp_used) 416 ctx->used_callee_reg[i++] = bpf2a64[PRIVATE_SP]; 417 } 418 419 if (ctx->arena_vm_start) 420 ctx->used_callee_reg[i++] = bpf2a64[ARENA_VM_START]; 421 422 ctx->nr_used_callee_reg = i; 423 } 424 425 /* Save callee-saved registers */ 426 static void push_callee_regs(struct jit_ctx *ctx) 427 { 428 int reg1, reg2, i; 429 430 /* 431 * Program acting as exception boundary should save all ARM64 432 * Callee-saved registers as the exception callback needs to recover 433 * all ARM64 Callee-saved registers in its epilogue. 434 */ 435 if (ctx->prog->aux->exception_boundary) { 436 emit(A64_PUSH(A64_R(19), A64_R(20), A64_SP), ctx); 437 emit(A64_PUSH(A64_R(21), A64_R(22), A64_SP), ctx); 438 emit(A64_PUSH(A64_R(23), A64_R(24), A64_SP), ctx); 439 emit(A64_PUSH(A64_R(25), A64_R(26), A64_SP), ctx); 440 emit(A64_PUSH(A64_R(27), A64_R(28), A64_SP), ctx); 441 ctx->fp_used = true; 442 } else { 443 find_used_callee_regs(ctx); 444 for (i = 0; i + 1 < ctx->nr_used_callee_reg; i += 2) { 445 reg1 = ctx->used_callee_reg[i]; 446 reg2 = ctx->used_callee_reg[i + 1]; 447 emit(A64_PUSH(reg1, reg2, A64_SP), ctx); 448 } 449 if (i < ctx->nr_used_callee_reg) { 450 reg1 = ctx->used_callee_reg[i]; 451 /* keep SP 16-byte aligned */ 452 emit(A64_PUSH(reg1, A64_ZR, A64_SP), ctx); 453 } 454 } 455 } 456 457 /* Restore callee-saved registers */ 458 static void pop_callee_regs(struct jit_ctx *ctx) 459 { 460 struct bpf_prog_aux *aux = ctx->prog->aux; 461 int reg1, reg2, i; 462 463 /* 464 * Program acting as exception boundary pushes R23 and R24 in addition 465 * to BPF callee-saved registers. Exception callback uses the boundary 466 * program's stack frame, so recover these extra registers in the above 467 * two cases. 468 */ 469 if (aux->exception_boundary || aux->exception_cb) { 470 emit(A64_POP(A64_R(27), A64_R(28), A64_SP), ctx); 471 emit(A64_POP(A64_R(25), A64_R(26), A64_SP), ctx); 472 emit(A64_POP(A64_R(23), A64_R(24), A64_SP), ctx); 473 emit(A64_POP(A64_R(21), A64_R(22), A64_SP), ctx); 474 emit(A64_POP(A64_R(19), A64_R(20), A64_SP), ctx); 475 } else { 476 i = ctx->nr_used_callee_reg - 1; 477 if (ctx->nr_used_callee_reg % 2 != 0) { 478 reg1 = ctx->used_callee_reg[i]; 479 emit(A64_POP(reg1, A64_ZR, A64_SP), ctx); 480 i--; 481 } 482 while (i > 0) { 483 reg1 = ctx->used_callee_reg[i - 1]; 484 reg2 = ctx->used_callee_reg[i]; 485 emit(A64_POP(reg1, reg2, A64_SP), ctx); 486 i -= 2; 487 } 488 } 489 } 490 491 static void emit_percpu_ptr(const u8 dst_reg, void __percpu *ptr, 492 struct jit_ctx *ctx) 493 { 494 const u8 tmp = bpf2a64[TMP_REG_1]; 495 496 emit_a64_mov_i64(dst_reg, (__force const u64)ptr, ctx); 497 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) 498 emit(A64_MRS_TPIDR_EL2(tmp), ctx); 499 else 500 emit(A64_MRS_TPIDR_EL1(tmp), ctx); 501 emit(A64_ADD(1, dst_reg, dst_reg, tmp), ctx); 502 } 503 504 #define BTI_INSNS (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) ? 1 : 0) 505 #define PAC_INSNS (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL) ? 1 : 0) 506 507 /* Offset of nop instruction in bpf prog entry to be poked */ 508 #define POKE_OFFSET (BTI_INSNS + 1) 509 510 /* Tail call offset to jump into */ 511 #define PROLOGUE_OFFSET (BTI_INSNS + 2 + PAC_INSNS + 4) 512 513 static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) 514 { 515 const struct bpf_prog *prog = ctx->prog; 516 const bool is_main_prog = !bpf_is_subprog(prog); 517 const u8 fp = bpf2a64[BPF_REG_FP]; 518 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 519 const u8 priv_sp = bpf2a64[PRIVATE_SP]; 520 void __percpu *priv_stack_ptr; 521 int cur_offset; 522 523 /* 524 * BPF prog stack layout 525 * 526 * high 527 * original A64_SP => 0:+-----+ BPF prologue 528 * |FP/LR| 529 * current A64_FP => -16:+-----+ 530 * | ... | callee saved registers 531 * BPF fp register => -64:+-----+ <= (BPF_FP) 532 * | | 533 * | ... | BPF prog stack 534 * | | 535 * +-----+ <= (BPF_FP - prog->aux->stack_depth) 536 * |RSVD | padding 537 * +-----+ <= (BPF_FP - ctx->stack_size) 538 * | | 539 * | ... | outgoing stack args (9+, if any) 540 * | | 541 * current A64_SP => +-----+ 542 * | | 543 * | ... | Function call stack 544 * | | 545 * +-----+ 546 * low 547 * 548 * Stack args 6-8 are passed in x5-x7, args 9+ at [SP]. 549 * Incoming args 9+ are at [A64_FP + 16], [A64_FP + 24], ... 550 * (above the saved FP/LR pair pushed in the callee prologue). 551 */ 552 553 emit_kcfi(is_main_prog ? cfi_bpf_hash : cfi_bpf_subprog_hash, ctx); 554 const int idx0 = ctx->idx; 555 556 /* bpf function may be invoked by 3 instruction types: 557 * 1. bl, attached via freplace to bpf prog via short jump 558 * 2. br, attached via freplace to bpf prog via long jump 559 * 3. blr, working as a function pointer, used by emit_call. 560 * So BTI_JC should used here to support both br and blr. 561 */ 562 emit_bti(A64_BTI_JC, ctx); 563 564 emit(A64_MOV(1, A64_R(9), A64_LR), ctx); 565 emit(A64_NOP, ctx); 566 567 if (!prog->aux->exception_cb) { 568 /* Sign lr */ 569 if (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL)) 570 emit(A64_PACIASP, ctx); 571 572 /* Save FP and LR registers to stay align with ARM64 AAPCS */ 573 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); 574 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 575 576 prepare_bpf_tail_call_cnt(ctx); 577 578 if (!ebpf_from_cbpf && is_main_prog) { 579 cur_offset = ctx->idx - idx0; 580 if (cur_offset != PROLOGUE_OFFSET) { 581 pr_err_once("PROLOGUE_OFFSET = %d, expected %d!\n", 582 cur_offset, PROLOGUE_OFFSET); 583 return -1; 584 } 585 /* BTI landing pad for the tail call, done with a BR */ 586 emit_bti(A64_BTI_J, ctx); 587 } 588 push_callee_regs(ctx); 589 } else { 590 /* 591 * Exception callback receives FP of Main Program as third 592 * parameter 593 */ 594 emit(A64_MOV(1, A64_FP, A64_R(2)), ctx); 595 /* 596 * Main Program already pushed the frame record and the 597 * callee-saved registers. The exception callback will not push 598 * anything and re-use the main program's stack. 599 * 600 * 12 registers are on the stack 601 */ 602 emit(A64_SUB_I(1, A64_SP, A64_FP, 96), ctx); 603 } 604 605 /* Stack must be multiples of 16B */ 606 ctx->stack_size = round_up(prog->aux->stack_depth, 16); 607 608 if (ctx->fp_used) { 609 if (ctx->priv_sp_used) { 610 /* Set up private stack pointer */ 611 priv_stack_ptr = prog->aux->priv_stack_ptr + PRIV_STACK_GUARD_SZ; 612 emit_percpu_ptr(priv_sp, priv_stack_ptr, ctx); 613 emit(A64_ADD_I(1, fp, priv_sp, ctx->stack_size), ctx); 614 } else { 615 /* Set up BPF prog stack base register */ 616 emit(A64_MOV(1, fp, A64_SP), ctx); 617 } 618 } 619 620 /* Set up function call stack */ 621 if (ctx->stack_size && !ctx->priv_sp_used) 622 emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 623 624 if (ctx->stack_arg_size) 625 emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 626 627 if (ctx->arena_vm_start) 628 emit_a64_mov_i64(arena_vm_base, ctx->arena_vm_start, ctx); 629 630 return 0; 631 } 632 633 static int emit_bpf_tail_call(struct jit_ctx *ctx) 634 { 635 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */ 636 const u8 r2 = bpf2a64[BPF_REG_2]; 637 const u8 r3 = bpf2a64[BPF_REG_3]; 638 639 const u8 tmp = bpf2a64[TMP_REG_1]; 640 const u8 prg = bpf2a64[TMP_REG_2]; 641 const u8 tcc = bpf2a64[TMP_REG_3]; 642 const u8 ptr = bpf2a64[TCCNT_PTR]; 643 size_t off; 644 __le32 *branch1 = NULL; 645 __le32 *branch2 = NULL; 646 __le32 *branch3 = NULL; 647 648 /* if (index >= array->map.max_entries) 649 * goto out; 650 */ 651 off = offsetof(struct bpf_array, map.max_entries); 652 emit_a64_mov_i64(tmp, off, ctx); 653 emit(A64_LDR32(tmp, r2, tmp), ctx); 654 emit(A64_MOV(0, r3, r3), ctx); 655 emit(A64_CMP(0, r3, tmp), ctx); 656 branch1 = ctx->image + ctx->idx; 657 emit(A64_NOP, ctx); 658 659 /* 660 * if ((*tail_call_cnt_ptr) >= MAX_TAIL_CALL_CNT) 661 * goto out; 662 */ 663 emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx); 664 emit(A64_LDR64I(tcc, ptr, 0), ctx); 665 emit(A64_CMP(1, tcc, tmp), ctx); 666 branch2 = ctx->image + ctx->idx; 667 emit(A64_NOP, ctx); 668 669 /* (*tail_call_cnt_ptr)++; */ 670 emit(A64_ADD_I(1, tcc, tcc, 1), ctx); 671 672 /* prog = array->ptrs[index]; 673 * if (prog == NULL) 674 * goto out; 675 */ 676 off = offsetof(struct bpf_array, ptrs); 677 emit_a64_mov_i64(tmp, off, ctx); 678 emit(A64_ADD(1, tmp, r2, tmp), ctx); 679 emit(A64_LSL(1, prg, r3, 3), ctx); 680 emit(A64_LDR64(prg, tmp, prg), ctx); 681 branch3 = ctx->image + ctx->idx; 682 emit(A64_NOP, ctx); 683 684 /* Update tail_call_cnt if the slot is populated. */ 685 emit(A64_STR64I(tcc, ptr, 0), ctx); 686 687 if (ctx->stack_arg_size) 688 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 689 690 /* restore SP */ 691 if (ctx->stack_size && !ctx->priv_sp_used) 692 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 693 694 pop_callee_regs(ctx); 695 696 /* goto *(prog->bpf_func + prologue_offset); */ 697 off = offsetof(struct bpf_prog, bpf_func); 698 emit_a64_mov_i64(tmp, off, ctx); 699 emit(A64_LDR64(tmp, prg, tmp), ctx); 700 emit(A64_ADD_I(1, tmp, tmp, sizeof(u32) * PROLOGUE_OFFSET), ctx); 701 emit(A64_BR(tmp), ctx); 702 703 if (ctx->image) { 704 off = &ctx->image[ctx->idx] - branch1; 705 *branch1 = cpu_to_le32(A64_B_(A64_COND_CS, off)); 706 707 off = &ctx->image[ctx->idx] - branch2; 708 *branch2 = cpu_to_le32(A64_B_(A64_COND_CS, off)); 709 710 off = &ctx->image[ctx->idx] - branch3; 711 *branch3 = cpu_to_le32(A64_CBZ(1, prg, off)); 712 } 713 714 return 0; 715 } 716 717 static int emit_atomic_ld_st(const struct bpf_insn *insn, struct jit_ctx *ctx) 718 { 719 const s32 imm = insn->imm; 720 const s16 off = insn->off; 721 const u8 code = insn->code; 722 const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC; 723 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 724 const u8 dst = bpf2a64[insn->dst_reg]; 725 const u8 src = bpf2a64[insn->src_reg]; 726 const u8 tmp = bpf2a64[TMP_REG_1]; 727 u8 reg; 728 729 switch (imm) { 730 case BPF_LOAD_ACQ: 731 reg = src; 732 break; 733 case BPF_STORE_REL: 734 reg = dst; 735 break; 736 default: 737 pr_err_once("unknown atomic load/store op code %02x\n", imm); 738 return -EINVAL; 739 } 740 741 if (off) { 742 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 743 reg = tmp; 744 } 745 if (arena) { 746 emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx); 747 reg = tmp; 748 } 749 750 switch (imm) { 751 case BPF_LOAD_ACQ: 752 switch (BPF_SIZE(code)) { 753 case BPF_B: 754 emit(A64_LDARB(dst, reg), ctx); 755 break; 756 case BPF_H: 757 emit(A64_LDARH(dst, reg), ctx); 758 break; 759 case BPF_W: 760 emit(A64_LDAR32(dst, reg), ctx); 761 break; 762 case BPF_DW: 763 emit(A64_LDAR64(dst, reg), ctx); 764 break; 765 } 766 break; 767 case BPF_STORE_REL: 768 switch (BPF_SIZE(code)) { 769 case BPF_B: 770 emit(A64_STLRB(src, reg), ctx); 771 break; 772 case BPF_H: 773 emit(A64_STLRH(src, reg), ctx); 774 break; 775 case BPF_W: 776 emit(A64_STLR32(src, reg), ctx); 777 break; 778 case BPF_DW: 779 emit(A64_STLR64(src, reg), ctx); 780 break; 781 } 782 break; 783 default: 784 pr_err_once("unexpected atomic load/store op code %02x\n", 785 imm); 786 return -EINVAL; 787 } 788 789 return 0; 790 } 791 792 static int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 793 { 794 const u8 code = insn->code; 795 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 796 const u8 dst = bpf2a64[insn->dst_reg]; 797 const u8 src = bpf2a64[insn->src_reg]; 798 const u8 tmp = bpf2a64[TMP_REG_1]; 799 const u8 tmp2 = bpf2a64[TMP_REG_2]; 800 const bool isdw = BPF_SIZE(code) == BPF_DW; 801 const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC; 802 const s16 off = insn->off; 803 u8 reg = dst; 804 805 if (off) { 806 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 807 reg = tmp; 808 } 809 if (arena) { 810 emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx); 811 reg = tmp; 812 } 813 814 switch (insn->imm) { 815 /* lock *(u32/u64 *)(dst_reg + off) <op>= src_reg */ 816 case BPF_ADD: 817 emit(A64_STADD(isdw, reg, src), ctx); 818 break; 819 case BPF_AND: 820 emit(A64_MVN(isdw, tmp2, src), ctx); 821 emit(A64_STCLR(isdw, reg, tmp2), ctx); 822 break; 823 case BPF_OR: 824 emit(A64_STSET(isdw, reg, src), ctx); 825 break; 826 case BPF_XOR: 827 emit(A64_STEOR(isdw, reg, src), ctx); 828 break; 829 /* src_reg = atomic_fetch_<op>(dst_reg + off, src_reg) */ 830 case BPF_ADD | BPF_FETCH: 831 emit(A64_LDADDAL(isdw, src, reg, src), ctx); 832 break; 833 case BPF_AND | BPF_FETCH: 834 emit(A64_MVN(isdw, tmp2, src), ctx); 835 emit(A64_LDCLRAL(isdw, src, reg, tmp2), ctx); 836 break; 837 case BPF_OR | BPF_FETCH: 838 emit(A64_LDSETAL(isdw, src, reg, src), ctx); 839 break; 840 case BPF_XOR | BPF_FETCH: 841 emit(A64_LDEORAL(isdw, src, reg, src), ctx); 842 break; 843 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 844 case BPF_XCHG: 845 emit(A64_SWPAL(isdw, src, reg, src), ctx); 846 break; 847 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 848 case BPF_CMPXCHG: 849 emit(A64_CASAL(isdw, src, reg, bpf2a64[BPF_REG_0]), ctx); 850 break; 851 default: 852 pr_err_once("unknown atomic op code %02x\n", insn->imm); 853 return -EINVAL; 854 } 855 856 return 0; 857 } 858 859 static int emit_ll_sc_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 860 { 861 const u8 code = insn->code; 862 const u8 dst = bpf2a64[insn->dst_reg]; 863 const u8 src = bpf2a64[insn->src_reg]; 864 const u8 tmp = bpf2a64[TMP_REG_1]; 865 const u8 tmp2 = bpf2a64[TMP_REG_2]; 866 const u8 tmp3 = bpf2a64[TMP_REG_3]; 867 const int i = insn - ctx->prog->insnsi; 868 const s32 imm = insn->imm; 869 const s16 off = insn->off; 870 const bool isdw = BPF_SIZE(code) == BPF_DW; 871 u8 reg = dst; 872 s32 jmp_offset; 873 874 if (BPF_MODE(code) == BPF_PROBE_ATOMIC) { 875 /* ll_sc based atomics don't support unsafe pointers yet. */ 876 pr_err_once("unknown atomic opcode %02x\n", code); 877 return -EINVAL; 878 } 879 880 if (off) { 881 emit_a64_add_i(1, tmp, reg, tmp, off, ctx); 882 reg = tmp; 883 } 884 885 if (imm == BPF_ADD || imm == BPF_AND || 886 imm == BPF_OR || imm == BPF_XOR) { 887 /* lock *(u32/u64 *)(dst_reg + off) <op>= src_reg */ 888 emit(A64_LDXR(isdw, tmp2, reg), ctx); 889 if (imm == BPF_ADD) 890 emit(A64_ADD(isdw, tmp2, tmp2, src), ctx); 891 else if (imm == BPF_AND) 892 emit(A64_AND(isdw, tmp2, tmp2, src), ctx); 893 else if (imm == BPF_OR) 894 emit(A64_ORR(isdw, tmp2, tmp2, src), ctx); 895 else 896 emit(A64_EOR(isdw, tmp2, tmp2, src), ctx); 897 emit(A64_STXR(isdw, tmp2, reg, tmp3), ctx); 898 jmp_offset = -3; 899 check_imm19(jmp_offset); 900 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 901 } else if (imm == (BPF_ADD | BPF_FETCH) || 902 imm == (BPF_AND | BPF_FETCH) || 903 imm == (BPF_OR | BPF_FETCH) || 904 imm == (BPF_XOR | BPF_FETCH)) { 905 /* src_reg = atomic_fetch_<op>(dst_reg + off, src_reg) */ 906 const u8 ax = bpf2a64[BPF_REG_AX]; 907 908 emit(A64_MOV(isdw, ax, src), ctx); 909 emit(A64_LDXR(isdw, src, reg), ctx); 910 if (imm == (BPF_ADD | BPF_FETCH)) 911 emit(A64_ADD(isdw, tmp2, src, ax), ctx); 912 else if (imm == (BPF_AND | BPF_FETCH)) 913 emit(A64_AND(isdw, tmp2, src, ax), ctx); 914 else if (imm == (BPF_OR | BPF_FETCH)) 915 emit(A64_ORR(isdw, tmp2, src, ax), ctx); 916 else 917 emit(A64_EOR(isdw, tmp2, src, ax), ctx); 918 emit(A64_STLXR(isdw, tmp2, reg, tmp3), ctx); 919 jmp_offset = -3; 920 check_imm19(jmp_offset); 921 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 922 emit(A64_DMB_ISH, ctx); 923 } else if (imm == BPF_XCHG) { 924 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 925 emit(A64_MOV(isdw, tmp2, src), ctx); 926 emit(A64_LDXR(isdw, src, reg), ctx); 927 emit(A64_STLXR(isdw, tmp2, reg, tmp3), ctx); 928 jmp_offset = -2; 929 check_imm19(jmp_offset); 930 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 931 emit(A64_DMB_ISH, ctx); 932 } else if (imm == BPF_CMPXCHG) { 933 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 934 const u8 r0 = bpf2a64[BPF_REG_0]; 935 936 emit(A64_MOV(isdw, tmp2, r0), ctx); 937 emit(A64_LDXR(isdw, r0, reg), ctx); 938 emit(A64_EOR(isdw, tmp3, r0, tmp2), ctx); 939 jmp_offset = 4; 940 check_imm19(jmp_offset); 941 emit(A64_CBNZ(isdw, tmp3, jmp_offset), ctx); 942 emit(A64_STLXR(isdw, src, reg, tmp3), ctx); 943 jmp_offset = -4; 944 check_imm19(jmp_offset); 945 emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); 946 emit(A64_DMB_ISH, ctx); 947 } else { 948 pr_err_once("unknown atomic op code %02x\n", imm); 949 return -EINVAL; 950 } 951 952 return 0; 953 } 954 955 void dummy_tramp(void); 956 957 asm ( 958 " .pushsection .text, \"ax\", @progbits\n" 959 " .global dummy_tramp\n" 960 " .type dummy_tramp, %function\n" 961 "dummy_tramp:" 962 #if IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) 963 " bti j\n" /* dummy_tramp is called via "br x10" */ 964 #endif 965 " mov x10, x30\n" 966 " mov x30, x9\n" 967 " ret x10\n" 968 " .size dummy_tramp, .-dummy_tramp\n" 969 " .popsection\n" 970 ); 971 972 /* build a plt initialized like this: 973 * 974 * plt: 975 * ldr tmp, target 976 * br tmp 977 * target: 978 * .quad dummy_tramp 979 * 980 * when a long jump trampoline is attached, target is filled with the 981 * trampoline address, and when the trampoline is removed, target is 982 * restored to dummy_tramp address. 983 */ 984 static void build_plt(struct jit_ctx *ctx) 985 { 986 const u8 tmp = bpf2a64[TMP_REG_1]; 987 struct bpf_plt *plt = NULL; 988 989 /* make sure target is 64-bit aligned */ 990 if ((ctx->idx + PLT_TARGET_OFFSET / AARCH64_INSN_SIZE) % 2) 991 emit(A64_NOP, ctx); 992 993 plt = (struct bpf_plt *)(ctx->image + ctx->idx); 994 /* plt is called via bl, no BTI needed here */ 995 emit(A64_LDR64LIT(tmp, 2 * AARCH64_INSN_SIZE), ctx); 996 emit(A64_BR(tmp), ctx); 997 998 if (ctx->image) 999 plt->target = (u64)&dummy_tramp; 1000 } 1001 1002 /* Clobbers BPF registers 1-4, aka x0-x3 */ 1003 static void __maybe_unused build_bhb_mitigation(struct jit_ctx *ctx) 1004 { 1005 const u8 r1 = bpf2a64[BPF_REG_1]; /* aka x0 */ 1006 u8 k = get_spectre_bhb_loop_value(); 1007 1008 if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY) || 1009 cpu_mitigations_off() || __nospectre_bhb || 1010 arm64_get_spectre_v2_state() == SPECTRE_VULNERABLE) 1011 return; 1012 1013 if (ns_capable_noaudit(&init_user_ns, CAP_SYS_ADMIN)) 1014 return; 1015 1016 if (supports_clearbhb(SCOPE_SYSTEM)) { 1017 emit(aarch64_insn_gen_hint(AARCH64_INSN_HINT_CLEARBHB), ctx); 1018 return; 1019 } 1020 1021 if (k) { 1022 emit_a64_mov_i64(r1, k, ctx); 1023 emit(A64_B(1), ctx); 1024 emit(A64_SUBS_I(true, r1, r1, 1), ctx); 1025 emit(A64_B_(A64_COND_NE, -2), ctx); 1026 emit(aarch64_insn_gen_dsb(AARCH64_INSN_MB_ISH), ctx); 1027 emit(aarch64_insn_get_isb_value(), ctx); 1028 } 1029 1030 if (is_spectre_bhb_fw_mitigated()) { 1031 emit(A64_ORR_I(false, r1, AARCH64_INSN_REG_ZR, 1032 ARM_SMCCC_ARCH_WORKAROUND_3), ctx); 1033 switch (arm_smccc_1_1_get_conduit()) { 1034 case SMCCC_CONDUIT_HVC: 1035 emit(aarch64_insn_get_hvc_value(), ctx); 1036 break; 1037 case SMCCC_CONDUIT_SMC: 1038 emit(aarch64_insn_get_smc_value(), ctx); 1039 break; 1040 default: 1041 pr_err_once("Firmware mitigation enabled with unknown conduit\n"); 1042 } 1043 } 1044 } 1045 1046 static void build_epilogue(struct jit_ctx *ctx, bool was_classic) 1047 { 1048 const u8 r0 = bpf2a64[BPF_REG_0]; 1049 const u8 ptr = bpf2a64[TCCNT_PTR]; 1050 1051 if (ctx->stack_arg_size) 1052 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_arg_size), ctx); 1053 1054 /* We're done with BPF stack */ 1055 if (ctx->stack_size && !ctx->priv_sp_used) 1056 emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); 1057 1058 pop_callee_regs(ctx); 1059 1060 emit(A64_POP(A64_ZR, ptr, A64_SP), ctx); 1061 1062 if (was_classic) 1063 build_bhb_mitigation(ctx); 1064 1065 /* Restore FP/LR registers */ 1066 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 1067 1068 /* Move the return value from bpf:r0 (aka x8) to x0 */ 1069 emit(A64_MOV(1, A64_R(0), r0), ctx); 1070 1071 /* Authenticate lr */ 1072 if (IS_ENABLED(CONFIG_ARM64_PTR_AUTH_KERNEL)) 1073 emit(A64_AUTIASP, ctx); 1074 1075 emit(A64_RET(A64_LR), ctx); 1076 } 1077 1078 /* 1079 * Metadata encoding for exception handling in JITed code. 1080 * 1081 * Format of `fixup` field in `struct exception_table_entry`: 1082 * 1083 * Bit layout of `fixup` (32-bit): 1084 * 1085 * +-----------+--------+-------------+-----------+-----------+----------+ 1086 * | 31-27 | 26-23 | 22 | 21 | 20-16 | 15-0 | 1087 * | | | | | | | 1088 * | FIXUP_REG | Unused | ARENA_WRITE | ARENA_ACC | ARENA_REG | OFFSET | 1089 * +-----------+--------+-------------+-----------+-----------+----------+ 1090 * 1091 * - OFFSET (16 bits): Offset used to compute address for Load/Store instruction. 1092 * - ARENA_REG (5 bits): Register that is used to calculate the address for load/store when 1093 * accessing the arena region. 1094 * - ARENA_ACCESS (1 bit): This bit is set when the faulting instruction accessed the arena region. 1095 * - ARENA_WRITE (1 bit): This bit is set when the faulting instruction wrote to the arena region. 1096 * It is independent of FIXUP_REG, since a read-modify-write both writes to 1097 * memory and reads the old value into a register. 1098 * - FIXUP_REG (5 bits): Destination register for the load instruction (cleared on fault) or set to 1099 * DONT_CLEAR if the instruction does not read into a register. 1100 */ 1101 1102 #define BPF_FIXUP_OFFSET_MASK GENMASK(15, 0) 1103 #define BPF_FIXUP_ARENA_REG_MASK GENMASK(20, 16) 1104 #define BPF_ARENA_ACCESS BIT(21) 1105 #define BPF_ARENA_WRITE BIT(22) 1106 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 1107 #define DONT_CLEAR 5 /* Unused ARM64 register from BPF's POV */ 1108 1109 bool ex_handler_bpf(const struct exception_table_entry *ex, 1110 struct pt_regs *regs) 1111 { 1112 int dst_reg = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 1113 s16 off = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 1114 int arena_reg = FIELD_GET(BPF_FIXUP_ARENA_REG_MASK, ex->fixup); 1115 bool is_arena = !!(ex->fixup & BPF_ARENA_ACCESS); 1116 bool is_write = !!(ex->fixup & BPF_ARENA_WRITE); 1117 unsigned long addr; 1118 1119 if (is_arena) { 1120 addr = regs->regs[arena_reg] + off; 1121 bpf_prog_report_arena_violation(is_write, addr, regs->pc); 1122 } 1123 1124 if (dst_reg != DONT_CLEAR) 1125 regs->regs[dst_reg] = 0; 1126 /* Skip the faulting instruction */ 1127 regs->pc += AARCH64_INSN_SIZE; 1128 1129 return true; 1130 } 1131 1132 /* For accesses to BTF pointers, add an entry to the exception table */ 1133 static int add_exception_handler(const struct bpf_insn *insn, 1134 struct jit_ctx *ctx, 1135 int dst_reg) 1136 { 1137 off_t ins_offset; 1138 s16 off = insn->off; 1139 bool is_arena, is_write; 1140 int arena_reg; 1141 unsigned long pc; 1142 struct exception_table_entry *ex; 1143 1144 if (!ctx->image) 1145 /* First pass */ 1146 return 0; 1147 1148 if (BPF_MODE(insn->code) != BPF_PROBE_MEM && 1149 BPF_MODE(insn->code) != BPF_PROBE_MEMSX && 1150 BPF_MODE(insn->code) != BPF_PROBE_MEM32 && 1151 BPF_MODE(insn->code) != BPF_PROBE_MEM32SX && 1152 BPF_MODE(insn->code) != BPF_PROBE_ATOMIC) 1153 return 0; 1154 1155 is_arena = (BPF_MODE(insn->code) == BPF_PROBE_MEM32) || 1156 (BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) || 1157 (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC); 1158 1159 if (!ctx->prog->aux->extable || 1160 WARN_ON_ONCE(ctx->exentry_idx >= ctx->prog->aux->num_exentries)) 1161 return -EINVAL; 1162 1163 ex = &ctx->prog->aux->extable[ctx->exentry_idx]; 1164 pc = (unsigned long)&ctx->ro_image[ctx->idx - 1]; 1165 1166 /* 1167 * This is the relative offset of the instruction that may fault from 1168 * the exception table itself. This will be written to the exception 1169 * table and if this instruction faults, the destination register will 1170 * be set to '0' and the execution will jump to the next instruction. 1171 */ 1172 ins_offset = pc - (long)&ex->insn; 1173 if (WARN_ON_ONCE(ins_offset >= 0 || ins_offset < INT_MIN)) 1174 return -ERANGE; 1175 1176 /* 1177 * The offsets above have been calculated using the RO buffer but we 1178 * need to use the R/W buffer for writes. 1179 * switch ex to rw buffer for writing. 1180 */ 1181 ex = (void *)ctx->image + ((void *)ex - (void *)ctx->ro_image); 1182 1183 ex->insn = ins_offset; 1184 1185 /* 1186 * A load-acquire is of BPF_STX class, but reads from src_reg into 1187 * dst_reg like a BPF_LDX does, hence it must not be treated as a store 1188 * here. A read-modify-write carrying BPF_FETCH is reported as a write 1189 * even though it does have a register to clear, see the callers. 1190 */ 1191 is_write = BPF_CLASS(insn->code) != BPF_LDX && 1192 !bpf_atomic_is_load_acq(insn); 1193 1194 ex->fixup = FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 1195 1196 if (is_arena) { 1197 ex->fixup |= BPF_ARENA_ACCESS; 1198 if (is_write) 1199 ex->fixup |= BPF_ARENA_WRITE; 1200 /* 1201 * insn->src_reg/dst_reg holds the address in the arena region with upper 32-bits 1202 * being zero because of a preceding addr_space_cast(r<n>, 0x0, 0x1) instruction. 1203 * This address is adjusted with the addition of arena_vm_start (see the 1204 * implementation of BPF_PROBE_MEM32 and BPF_PROBE_ATOMIC) before being used for the 1205 * memory access. Pass the reg holding the unmodified 32-bit address to 1206 * ex_handler_bpf. 1207 */ 1208 if (BPF_CLASS(insn->code) == BPF_LDX || bpf_atomic_is_load_acq(insn)) 1209 arena_reg = bpf2a64[insn->src_reg]; 1210 else 1211 arena_reg = bpf2a64[insn->dst_reg]; 1212 1213 ex->fixup |= FIELD_PREP(BPF_FIXUP_OFFSET_MASK, off) | 1214 FIELD_PREP(BPF_FIXUP_ARENA_REG_MASK, arena_reg); 1215 } 1216 1217 ex->type = EX_TYPE_BPF; 1218 1219 ctx->exentry_idx++; 1220 return 0; 1221 } 1222 1223 static const u8 stack_arg_reg[] = { A64_R(5), A64_R(6), A64_R(7) }; 1224 1225 #define NR_STACK_ARG_REGS ARRAY_SIZE(stack_arg_reg) 1226 1227 static void emit_stack_arg_load(u8 dst, s16 bpf_off, struct jit_ctx *ctx) 1228 { 1229 int idx = bpf_off / sizeof(u64) - 1; 1230 1231 if (idx < NR_STACK_ARG_REGS) 1232 emit(A64_MOV(1, dst, stack_arg_reg[idx]), ctx); 1233 else 1234 emit(A64_LDR64I(dst, A64_FP, (idx - NR_STACK_ARG_REGS) * sizeof(u64) + 16), ctx); 1235 } 1236 1237 static void emit_stack_arg_store(u8 src_a64, s16 bpf_off, struct jit_ctx *ctx) 1238 { 1239 int idx = -bpf_off / sizeof(u64) - 1; 1240 1241 if (idx < NR_STACK_ARG_REGS) 1242 emit(A64_MOV(1, stack_arg_reg[idx], src_a64), ctx); 1243 else 1244 emit(A64_STR64I(src_a64, A64_SP, (idx - NR_STACK_ARG_REGS) * sizeof(u64)), ctx); 1245 } 1246 1247 static void emit_stack_arg_store_imm(s32 imm, s16 bpf_off, const u8 tmp, struct jit_ctx *ctx) 1248 { 1249 int idx = -bpf_off / sizeof(u64) - 1; 1250 1251 if (idx < NR_STACK_ARG_REGS) { 1252 emit_a64_mov_i(1, stack_arg_reg[idx], imm, ctx); 1253 } else { 1254 emit_a64_mov_i(1, tmp, imm, ctx); 1255 emit(A64_STR64I(tmp, A64_SP, (idx - NR_STACK_ARG_REGS) * sizeof(u64)), ctx); 1256 } 1257 } 1258 1259 /* 1260 * Rebase the __arena args of a kfunc call to arena kernel addresses, 1261 * xN = kern_vm_start + (u32)xN, with the arena base register holding 1262 * kern_vm_start. A nullable arg preserves NULL by skipping the add, tested 1263 * on the truncated value as arena NULL is offset 0. 1264 */ 1265 static int emit_kfunc_arena_args(struct jit_ctx *ctx, const struct bpf_insn *insn) 1266 { 1267 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 1268 const struct btf_func_model *fm; 1269 int i; 1270 1271 fm = bpf_jit_find_kfunc_model(ctx->prog, insn); 1272 if (!fm) 1273 return -EINVAL; 1274 1275 for (i = 0; i < min_t(int, fm->nr_args, MAX_BPF_FUNC_REG_ARGS); i++) { 1276 const u8 reg = bpf2a64[BPF_REG_1 + i]; 1277 u8 flags = fm->arg_flags[i]; 1278 1279 if (!(flags & BTF_FMODEL_ARENA_ARG)) 1280 continue; 1281 if (WARN_ON_ONCE(!ctx->arena_vm_start)) 1282 return -EINVAL; 1283 1284 if (flags & BTF_FMODEL_NULLABLE_ARG) { 1285 /* 32-bit mov clears the upper 32 bits */ 1286 emit(A64_MOV(0, reg, reg), ctx); 1287 /* skip the add so that NULL stays NULL */ 1288 emit(A64_CBZ(0, reg, 2), ctx); 1289 } 1290 emit(A64_ADD_UXTW(reg, arena_vm_base, reg), ctx); 1291 } 1292 1293 return 0; 1294 } 1295 1296 /* JITs an eBPF instruction. 1297 * Returns: 1298 * 0 - successfully JITed an 8-byte eBPF instruction. 1299 * >0 - successfully JITed a 16-byte eBPF instruction. 1300 * <0 - failed to JIT. 1301 */ 1302 static int build_insn(const struct bpf_verifier_env *env, const struct bpf_insn *insn, 1303 struct jit_ctx *ctx, bool extra_pass) 1304 { 1305 const u8 code = insn->code; 1306 u8 dst = bpf2a64[insn->dst_reg]; 1307 u8 src = bpf2a64[insn->src_reg]; 1308 const u8 tmp = bpf2a64[TMP_REG_1]; 1309 const u8 tmp2 = bpf2a64[TMP_REG_2]; 1310 const u8 tmp3 = bpf2a64[TMP_REG_3]; 1311 const u8 fp = bpf2a64[BPF_REG_FP]; 1312 const u8 arena_vm_base = bpf2a64[ARENA_VM_START]; 1313 const u8 priv_sp = bpf2a64[PRIVATE_SP]; 1314 const s16 off = insn->off; 1315 const s32 imm = insn->imm; 1316 const int i = insn - ctx->prog->insnsi; 1317 const bool is64 = BPF_CLASS(code) == BPF_ALU64 || 1318 BPF_CLASS(code) == BPF_JMP; 1319 u8 jmp_cond; 1320 s32 jmp_offset; 1321 u32 a64_insn; 1322 u8 src_adj; 1323 u8 dst_adj; 1324 int off_adj; 1325 int ret; 1326 bool sign_extend; 1327 1328 if (bpf_insn_is_indirect_target(env, ctx->prog, i)) 1329 emit_bti(A64_BTI_J, ctx); 1330 1331 switch (code) { 1332 /* dst = src */ 1333 case BPF_ALU | BPF_MOV | BPF_X: 1334 case BPF_ALU64 | BPF_MOV | BPF_X: 1335 if (insn_is_cast_user(insn)) { 1336 u32 upper = ctx->user_vm_start >> 32; 1337 u16 upper_low = upper & 0xffff; 1338 u16 upper_high = upper >> 16; 1339 int nr_movk = !!upper_low + !!upper_high; 1340 1341 /* 1342 * Build the user address: the low 32 bits are the arena 1343 * offset, the upper 32 bits come from user_vm_start. A 1344 * zero offset must stay NULL, so branch over the MOVKs 1345 * when it is zero. 1346 */ 1347 emit(A64_MOV(0, dst, src), ctx); /* 32-bit mov clears the upper 32 bits */ 1348 if (nr_movk) { 1349 emit(A64_CBZ(0, dst, nr_movk + 1), ctx); 1350 if (upper_low) 1351 emit(A64_MOVK(1, dst, upper_low, 32), ctx); 1352 if (upper_high) 1353 emit(A64_MOVK(1, dst, upper_high, 48), ctx); 1354 } 1355 break; 1356 } else if (insn_is_mov_percpu_addr(insn)) { 1357 if (dst != src) 1358 emit(A64_MOV(1, dst, src), ctx); 1359 if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) 1360 emit(A64_MRS_TPIDR_EL2(tmp), ctx); 1361 else 1362 emit(A64_MRS_TPIDR_EL1(tmp), ctx); 1363 emit(A64_ADD(1, dst, dst, tmp), ctx); 1364 break; 1365 } 1366 switch (insn->off) { 1367 case 0: 1368 emit(A64_MOV(is64, dst, src), ctx); 1369 break; 1370 case 8: 1371 emit(A64_SXTB(is64, dst, src), ctx); 1372 break; 1373 case 16: 1374 emit(A64_SXTH(is64, dst, src), ctx); 1375 break; 1376 case 32: 1377 emit(A64_SXTW(is64, dst, src), ctx); 1378 break; 1379 } 1380 break; 1381 /* dst = dst OP src */ 1382 case BPF_ALU | BPF_ADD | BPF_X: 1383 case BPF_ALU64 | BPF_ADD | BPF_X: 1384 emit(A64_ADD(is64, dst, dst, src), ctx); 1385 break; 1386 case BPF_ALU | BPF_SUB | BPF_X: 1387 case BPF_ALU64 | BPF_SUB | BPF_X: 1388 emit(A64_SUB(is64, dst, dst, src), ctx); 1389 break; 1390 case BPF_ALU | BPF_AND | BPF_X: 1391 case BPF_ALU64 | BPF_AND | BPF_X: 1392 emit(A64_AND(is64, dst, dst, src), ctx); 1393 break; 1394 case BPF_ALU | BPF_OR | BPF_X: 1395 case BPF_ALU64 | BPF_OR | BPF_X: 1396 emit(A64_ORR(is64, dst, dst, src), ctx); 1397 break; 1398 case BPF_ALU | BPF_XOR | BPF_X: 1399 case BPF_ALU64 | BPF_XOR | BPF_X: 1400 emit(A64_EOR(is64, dst, dst, src), ctx); 1401 break; 1402 case BPF_ALU | BPF_MUL | BPF_X: 1403 case BPF_ALU64 | BPF_MUL | BPF_X: 1404 emit(A64_MUL(is64, dst, dst, src), ctx); 1405 break; 1406 case BPF_ALU | BPF_DIV | BPF_X: 1407 case BPF_ALU64 | BPF_DIV | BPF_X: 1408 if (!off) 1409 emit(A64_UDIV(is64, dst, dst, src), ctx); 1410 else 1411 emit(A64_SDIV(is64, dst, dst, src), ctx); 1412 break; 1413 case BPF_ALU | BPF_MOD | BPF_X: 1414 case BPF_ALU64 | BPF_MOD | BPF_X: 1415 if (!off) 1416 emit(A64_UDIV(is64, tmp, dst, src), ctx); 1417 else 1418 emit(A64_SDIV(is64, tmp, dst, src), ctx); 1419 emit(A64_MSUB(is64, dst, dst, tmp, src), ctx); 1420 break; 1421 case BPF_ALU | BPF_LSH | BPF_X: 1422 case BPF_ALU64 | BPF_LSH | BPF_X: 1423 emit(A64_LSLV(is64, dst, dst, src), ctx); 1424 break; 1425 case BPF_ALU | BPF_RSH | BPF_X: 1426 case BPF_ALU64 | BPF_RSH | BPF_X: 1427 emit(A64_LSRV(is64, dst, dst, src), ctx); 1428 break; 1429 case BPF_ALU | BPF_ARSH | BPF_X: 1430 case BPF_ALU64 | BPF_ARSH | BPF_X: 1431 emit(A64_ASRV(is64, dst, dst, src), ctx); 1432 break; 1433 /* dst = -dst */ 1434 case BPF_ALU | BPF_NEG: 1435 case BPF_ALU64 | BPF_NEG: 1436 emit(A64_NEG(is64, dst, dst), ctx); 1437 break; 1438 /* dst = BSWAP##imm(dst) */ 1439 case BPF_ALU | BPF_END | BPF_FROM_LE: 1440 case BPF_ALU | BPF_END | BPF_FROM_BE: 1441 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1442 #ifdef CONFIG_CPU_BIG_ENDIAN 1443 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_BE) 1444 goto emit_bswap_uxt; 1445 #else /* !CONFIG_CPU_BIG_ENDIAN */ 1446 if (BPF_CLASS(code) == BPF_ALU && BPF_SRC(code) == BPF_FROM_LE) 1447 goto emit_bswap_uxt; 1448 #endif 1449 switch (imm) { 1450 case 16: 1451 emit(A64_REV16(is64, dst, dst), ctx); 1452 /* zero-extend 16 bits into 64 bits */ 1453 emit(A64_UXTH(is64, dst, dst), ctx); 1454 break; 1455 case 32: 1456 emit(A64_REV32(0, dst, dst), ctx); 1457 /* upper 32 bits already cleared */ 1458 break; 1459 case 64: 1460 emit(A64_REV64(dst, dst), ctx); 1461 break; 1462 } 1463 break; 1464 emit_bswap_uxt: 1465 switch (imm) { 1466 case 16: 1467 /* zero-extend 16 bits into 64 bits */ 1468 emit(A64_UXTH(is64, dst, dst), ctx); 1469 break; 1470 case 32: 1471 /* zero-extend 32 bits into 64 bits */ 1472 emit(A64_UXTW(is64, dst, dst), ctx); 1473 break; 1474 case 64: 1475 /* nop */ 1476 break; 1477 } 1478 break; 1479 /* dst = imm */ 1480 case BPF_ALU | BPF_MOV | BPF_K: 1481 case BPF_ALU64 | BPF_MOV | BPF_K: 1482 emit_a64_mov_i(is64, dst, imm, ctx); 1483 break; 1484 /* dst = dst OP imm */ 1485 case BPF_ALU | BPF_ADD | BPF_K: 1486 case BPF_ALU64 | BPF_ADD | BPF_K: 1487 emit_a64_add_i(is64, dst, dst, tmp, imm, ctx); 1488 break; 1489 case BPF_ALU | BPF_SUB | BPF_K: 1490 case BPF_ALU64 | BPF_SUB | BPF_K: 1491 if (is_addsub_imm(imm)) { 1492 emit(A64_SUB_I(is64, dst, dst, imm), ctx); 1493 } else if (is_addsub_imm(-(u32)imm)) { 1494 emit(A64_ADD_I(is64, dst, dst, -imm), ctx); 1495 } else { 1496 emit_a64_mov_i(is64, tmp, imm, ctx); 1497 emit(A64_SUB(is64, dst, dst, tmp), ctx); 1498 } 1499 break; 1500 case BPF_ALU | BPF_AND | BPF_K: 1501 case BPF_ALU64 | BPF_AND | BPF_K: 1502 a64_insn = A64_AND_I(is64, dst, dst, imm); 1503 if (a64_insn != AARCH64_BREAK_FAULT) { 1504 emit(a64_insn, ctx); 1505 } else { 1506 emit_a64_mov_i(is64, tmp, imm, ctx); 1507 emit(A64_AND(is64, dst, dst, tmp), ctx); 1508 } 1509 break; 1510 case BPF_ALU | BPF_OR | BPF_K: 1511 case BPF_ALU64 | BPF_OR | BPF_K: 1512 a64_insn = A64_ORR_I(is64, dst, dst, imm); 1513 if (a64_insn != AARCH64_BREAK_FAULT) { 1514 emit(a64_insn, ctx); 1515 } else { 1516 emit_a64_mov_i(is64, tmp, imm, ctx); 1517 emit(A64_ORR(is64, dst, dst, tmp), ctx); 1518 } 1519 break; 1520 case BPF_ALU | BPF_XOR | BPF_K: 1521 case BPF_ALU64 | BPF_XOR | BPF_K: 1522 a64_insn = A64_EOR_I(is64, dst, dst, imm); 1523 if (a64_insn != AARCH64_BREAK_FAULT) { 1524 emit(a64_insn, ctx); 1525 } else { 1526 emit_a64_mov_i(is64, tmp, imm, ctx); 1527 emit(A64_EOR(is64, dst, dst, tmp), ctx); 1528 } 1529 break; 1530 case BPF_ALU | BPF_MUL | BPF_K: 1531 case BPF_ALU64 | BPF_MUL | BPF_K: 1532 emit_a64_mov_i(is64, tmp, imm, ctx); 1533 emit(A64_MUL(is64, dst, dst, tmp), ctx); 1534 break; 1535 case BPF_ALU | BPF_DIV | BPF_K: 1536 case BPF_ALU64 | BPF_DIV | BPF_K: 1537 emit_a64_mov_i(is64, tmp, imm, ctx); 1538 if (!off) 1539 emit(A64_UDIV(is64, dst, dst, tmp), ctx); 1540 else 1541 emit(A64_SDIV(is64, dst, dst, tmp), ctx); 1542 break; 1543 case BPF_ALU | BPF_MOD | BPF_K: 1544 case BPF_ALU64 | BPF_MOD | BPF_K: 1545 emit_a64_mov_i(is64, tmp2, imm, ctx); 1546 if (!off) 1547 emit(A64_UDIV(is64, tmp, dst, tmp2), ctx); 1548 else 1549 emit(A64_SDIV(is64, tmp, dst, tmp2), ctx); 1550 emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx); 1551 break; 1552 case BPF_ALU | BPF_LSH | BPF_K: 1553 case BPF_ALU64 | BPF_LSH | BPF_K: 1554 emit(A64_LSL(is64, dst, dst, imm), ctx); 1555 break; 1556 case BPF_ALU | BPF_RSH | BPF_K: 1557 case BPF_ALU64 | BPF_RSH | BPF_K: 1558 emit(A64_LSR(is64, dst, dst, imm), ctx); 1559 break; 1560 case BPF_ALU | BPF_ARSH | BPF_K: 1561 case BPF_ALU64 | BPF_ARSH | BPF_K: 1562 emit(A64_ASR(is64, dst, dst, imm), ctx); 1563 break; 1564 1565 /* JUMP reg */ 1566 case BPF_JMP | BPF_JA | BPF_X: 1567 emit(A64_BR(dst), ctx); 1568 break; 1569 /* JUMP off */ 1570 case BPF_JMP | BPF_JA: 1571 case BPF_JMP32 | BPF_JA: 1572 if (BPF_CLASS(code) == BPF_JMP) 1573 jmp_offset = bpf2a64_offset(i, off, ctx); 1574 else 1575 jmp_offset = bpf2a64_offset(i, imm, ctx); 1576 check_imm26(jmp_offset); 1577 emit(A64_B(jmp_offset), ctx); 1578 break; 1579 /* IF (dst COND src) JUMP off */ 1580 case BPF_JMP | BPF_JEQ | BPF_X: 1581 case BPF_JMP | BPF_JGT | BPF_X: 1582 case BPF_JMP | BPF_JLT | BPF_X: 1583 case BPF_JMP | BPF_JGE | BPF_X: 1584 case BPF_JMP | BPF_JLE | BPF_X: 1585 case BPF_JMP | BPF_JNE | BPF_X: 1586 case BPF_JMP | BPF_JSGT | BPF_X: 1587 case BPF_JMP | BPF_JSLT | BPF_X: 1588 case BPF_JMP | BPF_JSGE | BPF_X: 1589 case BPF_JMP | BPF_JSLE | BPF_X: 1590 case BPF_JMP32 | BPF_JEQ | BPF_X: 1591 case BPF_JMP32 | BPF_JGT | BPF_X: 1592 case BPF_JMP32 | BPF_JLT | BPF_X: 1593 case BPF_JMP32 | BPF_JGE | BPF_X: 1594 case BPF_JMP32 | BPF_JLE | BPF_X: 1595 case BPF_JMP32 | BPF_JNE | BPF_X: 1596 case BPF_JMP32 | BPF_JSGT | BPF_X: 1597 case BPF_JMP32 | BPF_JSLT | BPF_X: 1598 case BPF_JMP32 | BPF_JSGE | BPF_X: 1599 case BPF_JMP32 | BPF_JSLE | BPF_X: 1600 emit(A64_CMP(is64, dst, src), ctx); 1601 emit_cond_jmp: 1602 jmp_offset = bpf2a64_offset(i, off, ctx); 1603 check_imm19(jmp_offset); 1604 switch (BPF_OP(code)) { 1605 case BPF_JEQ: 1606 jmp_cond = A64_COND_EQ; 1607 break; 1608 case BPF_JGT: 1609 jmp_cond = A64_COND_HI; 1610 break; 1611 case BPF_JLT: 1612 jmp_cond = A64_COND_CC; 1613 break; 1614 case BPF_JGE: 1615 jmp_cond = A64_COND_CS; 1616 break; 1617 case BPF_JLE: 1618 jmp_cond = A64_COND_LS; 1619 break; 1620 case BPF_JSET: 1621 case BPF_JNE: 1622 jmp_cond = A64_COND_NE; 1623 break; 1624 case BPF_JSGT: 1625 jmp_cond = A64_COND_GT; 1626 break; 1627 case BPF_JSLT: 1628 jmp_cond = A64_COND_LT; 1629 break; 1630 case BPF_JSGE: 1631 jmp_cond = A64_COND_GE; 1632 break; 1633 case BPF_JSLE: 1634 jmp_cond = A64_COND_LE; 1635 break; 1636 default: 1637 return -EFAULT; 1638 } 1639 emit(A64_B_(jmp_cond, jmp_offset), ctx); 1640 break; 1641 case BPF_JMP | BPF_JSET | BPF_X: 1642 case BPF_JMP32 | BPF_JSET | BPF_X: 1643 emit(A64_TST(is64, dst, src), ctx); 1644 goto emit_cond_jmp; 1645 /* IF (dst COND imm) JUMP off */ 1646 case BPF_JMP | BPF_JEQ | BPF_K: 1647 case BPF_JMP | BPF_JGT | BPF_K: 1648 case BPF_JMP | BPF_JLT | BPF_K: 1649 case BPF_JMP | BPF_JGE | BPF_K: 1650 case BPF_JMP | BPF_JLE | BPF_K: 1651 case BPF_JMP | BPF_JNE | BPF_K: 1652 case BPF_JMP | BPF_JSGT | BPF_K: 1653 case BPF_JMP | BPF_JSLT | BPF_K: 1654 case BPF_JMP | BPF_JSGE | BPF_K: 1655 case BPF_JMP | BPF_JSLE | BPF_K: 1656 case BPF_JMP32 | BPF_JEQ | BPF_K: 1657 case BPF_JMP32 | BPF_JGT | BPF_K: 1658 case BPF_JMP32 | BPF_JLT | BPF_K: 1659 case BPF_JMP32 | BPF_JGE | BPF_K: 1660 case BPF_JMP32 | BPF_JLE | BPF_K: 1661 case BPF_JMP32 | BPF_JNE | BPF_K: 1662 case BPF_JMP32 | BPF_JSGT | BPF_K: 1663 case BPF_JMP32 | BPF_JSLT | BPF_K: 1664 case BPF_JMP32 | BPF_JSGE | BPF_K: 1665 case BPF_JMP32 | BPF_JSLE | BPF_K: 1666 if (is_addsub_imm(imm)) { 1667 emit(A64_CMP_I(is64, dst, imm), ctx); 1668 } else if (is_addsub_imm(-(u32)imm)) { 1669 emit(A64_CMN_I(is64, dst, -imm), ctx); 1670 } else { 1671 emit_a64_mov_i(is64, tmp, imm, ctx); 1672 emit(A64_CMP(is64, dst, tmp), ctx); 1673 } 1674 goto emit_cond_jmp; 1675 case BPF_JMP | BPF_JSET | BPF_K: 1676 case BPF_JMP32 | BPF_JSET | BPF_K: 1677 a64_insn = A64_TST_I(is64, dst, imm); 1678 if (a64_insn != AARCH64_BREAK_FAULT) { 1679 emit(a64_insn, ctx); 1680 } else { 1681 emit_a64_mov_i(is64, tmp, imm, ctx); 1682 emit(A64_TST(is64, dst, tmp), ctx); 1683 } 1684 goto emit_cond_jmp; 1685 /* function call */ 1686 case BPF_JMP | BPF_CALL: 1687 { 1688 const u8 r0 = bpf2a64[BPF_REG_0]; 1689 bool func_addr_fixed; 1690 u64 func_addr; 1691 u32 cpu_offset; 1692 1693 /* Implement helper call to bpf_get_smp_processor_id() inline */ 1694 if (insn->src_reg == 0 && insn->imm == BPF_FUNC_get_smp_processor_id) { 1695 cpu_offset = offsetof(struct thread_info, cpu); 1696 1697 emit(A64_MRS_SP_EL0(tmp), ctx); 1698 if (is_lsi_offset(cpu_offset, 2)) { 1699 emit(A64_LDR32I(r0, tmp, cpu_offset), ctx); 1700 } else { 1701 emit_a64_mov_i(1, tmp2, cpu_offset, ctx); 1702 emit(A64_LDR32(r0, tmp, tmp2), ctx); 1703 } 1704 break; 1705 } 1706 1707 /* Implement helper call to bpf_get_current_task/_btf() inline */ 1708 if (insn->src_reg == 0 && (insn->imm == BPF_FUNC_get_current_task || 1709 insn->imm == BPF_FUNC_get_current_task_btf)) { 1710 emit(A64_MRS_SP_EL0(r0), ctx); 1711 break; 1712 } 1713 1714 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1715 &func_addr, &func_addr_fixed); 1716 if (ret < 0) 1717 return ret; 1718 if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) { 1719 ret = emit_kfunc_arena_args(ctx, insn); 1720 if (ret < 0) 1721 return ret; 1722 } 1723 emit_call(func_addr, ctx); 1724 /* 1725 * Call to arch_bpf_timed_may_goto() is emitted by the 1726 * verifier and called with custom calling convention with 1727 * first argument and return value in BPF_REG_AX (x9). 1728 */ 1729 if (func_addr != (u64)arch_bpf_timed_may_goto) 1730 emit(A64_MOV(1, r0, A64_R(0)), ctx); 1731 break; 1732 } 1733 /* tail call */ 1734 case BPF_JMP | BPF_TAIL_CALL: 1735 if (emit_bpf_tail_call(ctx)) 1736 return -EFAULT; 1737 break; 1738 /* function return */ 1739 case BPF_JMP | BPF_EXIT: 1740 /* Optimization: when last instruction is EXIT, 1741 simply fallthrough to epilogue. */ 1742 if (i == ctx->prog->len - 1) 1743 break; 1744 jmp_offset = epilogue_offset(ctx); 1745 check_imm26(jmp_offset); 1746 emit(A64_B(jmp_offset), ctx); 1747 break; 1748 1749 /* dst = imm64 */ 1750 case BPF_LD | BPF_IMM | BPF_DW: 1751 { 1752 const struct bpf_insn insn1 = insn[1]; 1753 u64 imm64; 1754 1755 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1756 if (bpf_pseudo_func(insn)) 1757 emit_addr_mov_i64(dst, imm64, ctx); 1758 else 1759 emit_a64_mov_i64(dst, imm64, ctx); 1760 1761 return 1; 1762 } 1763 1764 /* LDX: dst = (u64)*(unsigned size *)(src + off) */ 1765 case BPF_LDX | BPF_MEM | BPF_W: 1766 case BPF_LDX | BPF_MEM | BPF_H: 1767 case BPF_LDX | BPF_MEM | BPF_B: 1768 case BPF_LDX | BPF_MEM | BPF_DW: 1769 if (insn->src_reg == BPF_REG_PARAMS) { 1770 emit_stack_arg_load(dst, off, ctx); 1771 break; 1772 } 1773 fallthrough; 1774 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1775 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1776 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1777 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1778 /* LDXS: dst_reg = (s64)*(signed size *)(src_reg + off) */ 1779 case BPF_LDX | BPF_MEMSX | BPF_B: 1780 case BPF_LDX | BPF_MEMSX | BPF_H: 1781 case BPF_LDX | BPF_MEMSX | BPF_W: 1782 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1783 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1784 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1785 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1786 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1787 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1788 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1789 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B: 1790 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H: 1791 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W: 1792 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32 || 1793 BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) { 1794 emit(A64_ADD(1, tmp2, src, arena_vm_base), ctx); 1795 src = tmp2; 1796 } 1797 if (src == fp) { 1798 src_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1799 off_adj = off + ctx->stack_size; 1800 if (!ctx->priv_sp_used) 1801 off_adj += ctx->stack_arg_size; 1802 } else { 1803 src_adj = src; 1804 off_adj = off; 1805 } 1806 sign_extend = (BPF_MODE(insn->code) == BPF_MEMSX || 1807 BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 1808 BPF_MODE(insn->code) == BPF_PROBE_MEM32SX); 1809 switch (BPF_SIZE(code)) { 1810 case BPF_W: 1811 if (is_lsi_offset(off_adj, 2)) { 1812 if (sign_extend) 1813 emit(A64_LDRSWI(dst, src_adj, off_adj), ctx); 1814 else 1815 emit(A64_LDR32I(dst, src_adj, off_adj), ctx); 1816 } else { 1817 emit_a64_mov_i(1, tmp, off, ctx); 1818 if (sign_extend) 1819 emit(A64_LDRSW(dst, src, tmp), ctx); 1820 else 1821 emit(A64_LDR32(dst, src, tmp), ctx); 1822 } 1823 break; 1824 case BPF_H: 1825 if (is_lsi_offset(off_adj, 1)) { 1826 if (sign_extend) 1827 emit(A64_LDRSHI(dst, src_adj, off_adj), ctx); 1828 else 1829 emit(A64_LDRHI(dst, src_adj, off_adj), ctx); 1830 } else { 1831 emit_a64_mov_i(1, tmp, off, ctx); 1832 if (sign_extend) 1833 emit(A64_LDRSH(dst, src, tmp), ctx); 1834 else 1835 emit(A64_LDRH(dst, src, tmp), ctx); 1836 } 1837 break; 1838 case BPF_B: 1839 if (is_lsi_offset(off_adj, 0)) { 1840 if (sign_extend) 1841 emit(A64_LDRSBI(dst, src_adj, off_adj), ctx); 1842 else 1843 emit(A64_LDRBI(dst, src_adj, off_adj), ctx); 1844 } else { 1845 emit_a64_mov_i(1, tmp, off, ctx); 1846 if (sign_extend) 1847 emit(A64_LDRSB(dst, src, tmp), ctx); 1848 else 1849 emit(A64_LDRB(dst, src, tmp), ctx); 1850 } 1851 break; 1852 case BPF_DW: 1853 if (is_lsi_offset(off_adj, 3)) { 1854 emit(A64_LDR64I(dst, src_adj, off_adj), ctx); 1855 } else { 1856 emit_a64_mov_i(1, tmp, off, ctx); 1857 emit(A64_LDR64(dst, src, tmp), ctx); 1858 } 1859 break; 1860 } 1861 1862 ret = add_exception_handler(insn, ctx, dst); 1863 if (ret) 1864 return ret; 1865 break; 1866 1867 /* speculation barrier against v1 and v4 */ 1868 case BPF_ST | BPF_NOSPEC: 1869 if (alternative_has_cap_likely(ARM64_HAS_SB)) { 1870 emit(A64_SB, ctx); 1871 } else { 1872 emit(A64_DSB_NSH, ctx); 1873 emit(A64_ISB, ctx); 1874 } 1875 break; 1876 1877 /* ST: *(size *)(dst + off) = imm */ 1878 case BPF_ST | BPF_MEM | BPF_W: 1879 case BPF_ST | BPF_MEM | BPF_H: 1880 case BPF_ST | BPF_MEM | BPF_B: 1881 case BPF_ST | BPF_MEM | BPF_DW: 1882 if (insn->dst_reg == BPF_REG_PARAMS) { 1883 emit_stack_arg_store_imm(imm, off, tmp, ctx); 1884 break; 1885 } 1886 fallthrough; 1887 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1888 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1889 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1890 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1891 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1892 emit(A64_ADD(1, tmp3, dst, arena_vm_base), ctx); 1893 dst = tmp3; 1894 } 1895 if (dst == fp) { 1896 dst_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1897 off_adj = off + ctx->stack_size; 1898 if (!ctx->priv_sp_used) 1899 off_adj += ctx->stack_arg_size; 1900 } else { 1901 dst_adj = dst; 1902 off_adj = off; 1903 } 1904 /* Load imm to a register then store it */ 1905 emit_a64_mov_i(1, tmp, imm, ctx); 1906 switch (BPF_SIZE(code)) { 1907 case BPF_W: 1908 if (is_lsi_offset(off_adj, 2)) { 1909 emit(A64_STR32I(tmp, dst_adj, off_adj), ctx); 1910 } else { 1911 emit_a64_mov_i(1, tmp2, off, ctx); 1912 emit(A64_STR32(tmp, dst, tmp2), ctx); 1913 } 1914 break; 1915 case BPF_H: 1916 if (is_lsi_offset(off_adj, 1)) { 1917 emit(A64_STRHI(tmp, dst_adj, off_adj), ctx); 1918 } else { 1919 emit_a64_mov_i(1, tmp2, off, ctx); 1920 emit(A64_STRH(tmp, dst, tmp2), ctx); 1921 } 1922 break; 1923 case BPF_B: 1924 if (is_lsi_offset(off_adj, 0)) { 1925 emit(A64_STRBI(tmp, dst_adj, off_adj), ctx); 1926 } else { 1927 emit_a64_mov_i(1, tmp2, off, ctx); 1928 emit(A64_STRB(tmp, dst, tmp2), ctx); 1929 } 1930 break; 1931 case BPF_DW: 1932 if (is_lsi_offset(off_adj, 3)) { 1933 emit(A64_STR64I(tmp, dst_adj, off_adj), ctx); 1934 } else { 1935 emit_a64_mov_i(1, tmp2, off, ctx); 1936 emit(A64_STR64(tmp, dst, tmp2), ctx); 1937 } 1938 break; 1939 } 1940 1941 ret = add_exception_handler(insn, ctx, DONT_CLEAR); 1942 if (ret) 1943 return ret; 1944 break; 1945 1946 /* STX: *(size *)(dst + off) = src */ 1947 case BPF_STX | BPF_MEM | BPF_W: 1948 case BPF_STX | BPF_MEM | BPF_H: 1949 case BPF_STX | BPF_MEM | BPF_B: 1950 case BPF_STX | BPF_MEM | BPF_DW: 1951 if (insn->dst_reg == BPF_REG_PARAMS) { 1952 emit_stack_arg_store(src, off, ctx); 1953 break; 1954 } 1955 fallthrough; 1956 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1957 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1958 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1959 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1960 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1961 emit(A64_ADD(1, tmp2, dst, arena_vm_base), ctx); 1962 dst = tmp2; 1963 } 1964 if (dst == fp) { 1965 dst_adj = ctx->priv_sp_used ? priv_sp : A64_SP; 1966 off_adj = off + ctx->stack_size; 1967 if (!ctx->priv_sp_used) 1968 off_adj += ctx->stack_arg_size; 1969 } else { 1970 dst_adj = dst; 1971 off_adj = off; 1972 } 1973 switch (BPF_SIZE(code)) { 1974 case BPF_W: 1975 if (is_lsi_offset(off_adj, 2)) { 1976 emit(A64_STR32I(src, dst_adj, off_adj), ctx); 1977 } else { 1978 emit_a64_mov_i(1, tmp, off, ctx); 1979 emit(A64_STR32(src, dst, tmp), ctx); 1980 } 1981 break; 1982 case BPF_H: 1983 if (is_lsi_offset(off_adj, 1)) { 1984 emit(A64_STRHI(src, dst_adj, off_adj), ctx); 1985 } else { 1986 emit_a64_mov_i(1, tmp, off, ctx); 1987 emit(A64_STRH(src, dst, tmp), ctx); 1988 } 1989 break; 1990 case BPF_B: 1991 if (is_lsi_offset(off_adj, 0)) { 1992 emit(A64_STRBI(src, dst_adj, off_adj), ctx); 1993 } else { 1994 emit_a64_mov_i(1, tmp, off, ctx); 1995 emit(A64_STRB(src, dst, tmp), ctx); 1996 } 1997 break; 1998 case BPF_DW: 1999 if (is_lsi_offset(off_adj, 3)) { 2000 emit(A64_STR64I(src, dst_adj, off_adj), ctx); 2001 } else { 2002 emit_a64_mov_i(1, tmp, off, ctx); 2003 emit(A64_STR64(src, dst, tmp), ctx); 2004 } 2005 break; 2006 } 2007 2008 ret = add_exception_handler(insn, ctx, DONT_CLEAR); 2009 if (ret) 2010 return ret; 2011 break; 2012 2013 case BPF_STX | BPF_ATOMIC | BPF_B: 2014 case BPF_STX | BPF_ATOMIC | BPF_H: 2015 case BPF_STX | BPF_ATOMIC | BPF_W: 2016 case BPF_STX | BPF_ATOMIC | BPF_DW: 2017 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 2018 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 2019 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2020 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2021 if (bpf_atomic_is_load_store(insn)) 2022 ret = emit_atomic_ld_st(insn, ctx); 2023 else if (cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) 2024 ret = emit_lse_atomic(insn, ctx); 2025 else 2026 ret = emit_ll_sc_atomic(insn, ctx); 2027 if (ret) 2028 return ret; 2029 2030 if (BPF_MODE(insn->code) == BPF_PROBE_ATOMIC) { 2031 /* 2032 * A load-acquire reads into dst_reg, and a read-modify-write 2033 * carrying BPF_FETCH reads the old value into src_reg, or into 2034 * r0 for a BPF_CMPXCHG. Clear that register on fault, the 2035 * remaining atomics have no destination register. 2036 */ 2037 int load_reg = bpf_atomic_load_reg(insn); 2038 2039 ret = add_exception_handler(insn, ctx, load_reg < 0 ? 2040 DONT_CLEAR : bpf2a64[load_reg]); 2041 if (ret) 2042 return ret; 2043 } 2044 break; 2045 2046 default: 2047 pr_err_once("unknown opcode %02x\n", code); 2048 return -EINVAL; 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int build_body(struct bpf_verifier_env *env, struct jit_ctx *ctx, bool extra_pass) 2055 { 2056 const struct bpf_prog *prog = ctx->prog; 2057 int i; 2058 2059 /* 2060 * - offset[0] offset of the end of prologue, 2061 * start of the 1st instruction. 2062 * - offset[1] - offset of the end of 1st instruction, 2063 * start of the 2nd instruction 2064 * [....] 2065 * - offset[3] - offset of the end of 3rd instruction, 2066 * start of 4th instruction 2067 */ 2068 for (i = 0; i < prog->len; i++) { 2069 const struct bpf_insn *insn = &prog->insnsi[i]; 2070 int ret; 2071 2072 ctx->offset[i] = ctx->idx; 2073 ret = build_insn(env, insn, ctx, extra_pass); 2074 if (ret > 0) { 2075 i++; 2076 ctx->offset[i] = ctx->idx; 2077 continue; 2078 } 2079 if (ret) 2080 return ret; 2081 } 2082 /* 2083 * offset is allocated with prog->len + 1 so fill in 2084 * the last element with the offset after the last 2085 * instruction (end of program) 2086 */ 2087 ctx->offset[i] = ctx->idx; 2088 2089 return 0; 2090 } 2091 2092 static int validate_code(struct jit_ctx *ctx) 2093 { 2094 int i; 2095 2096 for (i = 0; i < ctx->idx; i++) { 2097 u32 a64_insn = le32_to_cpu(ctx->image[i]); 2098 2099 if (a64_insn == AARCH64_BREAK_FAULT) 2100 return -1; 2101 } 2102 return 0; 2103 } 2104 2105 static int validate_ctx(struct jit_ctx *ctx) 2106 { 2107 if (validate_code(ctx)) 2108 return -1; 2109 2110 if (WARN_ON_ONCE(ctx->exentry_idx != ctx->prog->aux->num_exentries)) 2111 return -1; 2112 2113 return 0; 2114 } 2115 2116 static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 2117 { 2118 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 2119 u64 *stack_ptr; 2120 2121 for_each_possible_cpu(cpu) { 2122 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 2123 stack_ptr[0] = PRIV_STACK_GUARD_VAL; 2124 stack_ptr[1] = PRIV_STACK_GUARD_VAL; 2125 stack_ptr[underflow_idx] = PRIV_STACK_GUARD_VAL; 2126 stack_ptr[underflow_idx + 1] = PRIV_STACK_GUARD_VAL; 2127 } 2128 } 2129 2130 static void priv_stack_check_guard(void __percpu *priv_stack_ptr, int alloc_size, 2131 struct bpf_prog *prog) 2132 { 2133 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 2134 u64 *stack_ptr; 2135 2136 for_each_possible_cpu(cpu) { 2137 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 2138 if (stack_ptr[0] != PRIV_STACK_GUARD_VAL || 2139 stack_ptr[1] != PRIV_STACK_GUARD_VAL || 2140 stack_ptr[underflow_idx] != PRIV_STACK_GUARD_VAL || 2141 stack_ptr[underflow_idx + 1] != PRIV_STACK_GUARD_VAL) { 2142 pr_err("BPF private stack overflow/underflow detected for prog %sx\n", 2143 bpf_jit_get_prog_name(prog)); 2144 break; 2145 } 2146 } 2147 } 2148 2149 struct arm64_jit_data { 2150 struct bpf_binary_header *header; 2151 u8 *ro_image; 2152 struct bpf_binary_header *ro_header; 2153 struct jit_ctx ctx; 2154 }; 2155 2156 struct bpf_prog *bpf_int_jit_compile(struct bpf_verifier_env *env, struct bpf_prog *prog) 2157 { 2158 int image_size, prog_size, extable_size, extable_align, extable_offset; 2159 struct bpf_binary_header *header; 2160 struct bpf_binary_header *ro_header = NULL; 2161 struct arm64_jit_data *jit_data; 2162 void __percpu *priv_stack_ptr = NULL; 2163 bool was_classic = bpf_prog_was_classic(prog); 2164 int priv_stack_alloc_sz; 2165 bool extra_pass = false; 2166 struct jit_ctx ctx; 2167 u8 *image_ptr; 2168 u8 *ro_image_ptr; 2169 int body_idx; 2170 int exentry_idx; 2171 int out_cnt; 2172 2173 if (!prog->jit_requested) 2174 return prog; 2175 2176 jit_data = prog->aux->jit_data; 2177 if (!jit_data) { 2178 jit_data = kzalloc_obj(*jit_data); 2179 if (!jit_data) 2180 return prog; 2181 prog->aux->jit_data = jit_data; 2182 } 2183 priv_stack_ptr = prog->aux->priv_stack_ptr; 2184 if (!priv_stack_ptr && prog->aux->jits_use_priv_stack) { 2185 /* Allocate actual private stack size with verifier-calculated 2186 * stack size plus two memory guards to protect overflow and 2187 * underflow. 2188 */ 2189 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 16) + 2190 2 * PRIV_STACK_GUARD_SZ; 2191 priv_stack_ptr = __alloc_percpu_gfp(priv_stack_alloc_sz, 16, GFP_KERNEL); 2192 if (!priv_stack_ptr) 2193 goto out_priv_stack; 2194 2195 priv_stack_init_guard(priv_stack_ptr, priv_stack_alloc_sz); 2196 prog->aux->priv_stack_ptr = priv_stack_ptr; 2197 } 2198 if (jit_data->ctx.offset) { 2199 ctx = jit_data->ctx; 2200 ro_image_ptr = jit_data->ro_image; 2201 ro_header = jit_data->ro_header; 2202 header = jit_data->header; 2203 image_ptr = (void *)header + ((void *)ro_image_ptr 2204 - (void *)ro_header); 2205 extra_pass = true; 2206 prog_size = sizeof(u32) * ctx.idx; 2207 goto skip_init_ctx; 2208 } 2209 memset(&ctx, 0, sizeof(ctx)); 2210 ctx.prog = prog; 2211 2212 ctx.offset = kvzalloc_objs(int, prog->len + 1); 2213 if (ctx.offset == NULL) 2214 goto out_off; 2215 2216 ctx.user_vm_start = bpf_arena_get_user_vm_start(prog->aux->arena); 2217 ctx.arena_vm_start = bpf_arena_get_kern_vm_start(prog->aux->arena); 2218 2219 out_cnt = bpf_out_stack_arg_cnt(env, prog); 2220 if (out_cnt) { 2221 int nr_on_stack = out_cnt - NR_STACK_ARG_REGS; 2222 2223 if (nr_on_stack > 0) 2224 ctx.stack_arg_size = round_up(nr_on_stack * sizeof(u64), 16); 2225 } 2226 2227 if (priv_stack_ptr) 2228 ctx.priv_sp_used = true; 2229 2230 /* Pass 1: Estimate the maximum image size. 2231 * 2232 * BPF line info needs ctx->offset[i] to be the offset of 2233 * instruction[i] in jited image, so build prologue first. 2234 */ 2235 if (build_prologue(&ctx, was_classic)) 2236 goto out_off; 2237 2238 if (build_body(env, &ctx, extra_pass)) 2239 goto out_off; 2240 2241 ctx.epilogue_offset = ctx.idx; 2242 build_epilogue(&ctx, was_classic); 2243 build_plt(&ctx); 2244 2245 extable_align = __alignof__(struct exception_table_entry); 2246 extable_size = prog->aux->num_exentries * 2247 sizeof(struct exception_table_entry); 2248 2249 /* Now we know the maximum image size. */ 2250 prog_size = sizeof(u32) * ctx.idx; 2251 /* also allocate space for plt target */ 2252 extable_offset = round_up(prog_size + PLT_TARGET_SIZE, extable_align); 2253 image_size = extable_offset + extable_size; 2254 ro_header = bpf_jit_binary_pack_alloc(image_size, &ro_image_ptr, 2255 sizeof(u64), &header, &image_ptr, 2256 jit_fill_hole, was_classic); 2257 if (!ro_header) 2258 goto out_off; 2259 2260 /* Pass 2: Determine jited position and result for each instruction */ 2261 2262 /* 2263 * Use the image(RW) for writing the JITed instructions. But also save 2264 * the ro_image(RX) for calculating the offsets in the image. The RW 2265 * image will be later copied to the RX image from where the program 2266 * will run. The bpf_jit_binary_pack_finalize() will do this copy in the 2267 * final step. 2268 */ 2269 ctx.image = (__le32 *)image_ptr; 2270 ctx.ro_image = (__le32 *)ro_image_ptr; 2271 if (extable_size) 2272 prog->aux->extable = (void *)ro_image_ptr + extable_offset; 2273 skip_init_ctx: 2274 ctx.idx = 0; 2275 ctx.exentry_idx = 0; 2276 ctx.write = true; 2277 2278 build_prologue(&ctx, was_classic); 2279 2280 /* Record exentry_idx and body_idx before first build_body */ 2281 exentry_idx = ctx.exentry_idx; 2282 body_idx = ctx.idx; 2283 /* Dont write body instructions to memory for now */ 2284 ctx.write = false; 2285 2286 if (build_body(env, &ctx, extra_pass)) 2287 goto out_free_hdr; 2288 2289 ctx.epilogue_offset = ctx.idx; 2290 ctx.exentry_idx = exentry_idx; 2291 ctx.idx = body_idx; 2292 ctx.write = true; 2293 2294 /* Pass 3: Adjust jump offset and write final image */ 2295 if (build_body(env, &ctx, extra_pass) || 2296 WARN_ON_ONCE(ctx.idx != ctx.epilogue_offset)) 2297 goto out_free_hdr; 2298 2299 build_epilogue(&ctx, was_classic); 2300 build_plt(&ctx); 2301 2302 /* Extra pass to validate JITed code. */ 2303 if (validate_ctx(&ctx)) 2304 goto out_free_hdr; 2305 2306 /* update the real prog size */ 2307 prog_size = sizeof(u32) * ctx.idx; 2308 2309 /* And we're done. */ 2310 if (bpf_jit_enable > 1) 2311 bpf_jit_dump(prog->len, prog_size, 2, ctx.image); 2312 2313 if (!prog->is_func || extra_pass) { 2314 /* The jited image may shrink since the jited result for 2315 * BPF_CALL to subprog may be changed from indirect call 2316 * to direct call. 2317 */ 2318 if (extra_pass && ctx.idx > jit_data->ctx.idx) { 2319 pr_err_once("multi-func JIT bug %d > %d\n", 2320 ctx.idx, jit_data->ctx.idx); 2321 goto out_free_hdr; 2322 } 2323 if (WARN_ON(bpf_jit_binary_pack_finalize(ro_header, header))) { 2324 /* ro_header and header has been freed */ 2325 ro_header = NULL; 2326 header = NULL; 2327 goto out_free_hdr; 2328 } 2329 } else { 2330 jit_data->ctx = ctx; 2331 jit_data->ro_image = ro_image_ptr; 2332 jit_data->header = header; 2333 jit_data->ro_header = ro_header; 2334 } 2335 2336 prog->bpf_func = (void *)ctx.ro_image + cfi_get_offset(); 2337 prog->jited = 1; 2338 prog->jited_len = prog_size - cfi_get_offset(); 2339 2340 if (!prog->is_func || extra_pass) { 2341 int i; 2342 2343 /* offset[prog->len] is the size of program */ 2344 for (i = 0; i <= prog->len; i++) 2345 ctx.offset[i] *= AARCH64_INSN_SIZE; 2346 bpf_prog_fill_jited_linfo(prog, ctx.offset + 1); 2347 /* 2348 * The bpf_prog_update_insn_ptrs function expects offsets to 2349 * point to the first byte of the jitted instruction (unlike 2350 * the bpf_prog_fill_jited_linfo above, which, for historical 2351 * reasons, expects to point to the next instruction) 2352 */ 2353 bpf_prog_update_insn_ptrs(prog, ctx.offset, ctx.ro_image); 2354 out_off: 2355 if (!ro_header && priv_stack_ptr) { 2356 free_percpu(priv_stack_ptr); 2357 prog->aux->priv_stack_ptr = NULL; 2358 } 2359 kvfree(ctx.offset); 2360 out_priv_stack: 2361 kfree(jit_data); 2362 prog->aux->jit_data = NULL; 2363 } 2364 2365 return prog; 2366 2367 out_free_hdr: 2368 if (extra_pass) { 2369 prog->bpf_func = NULL; 2370 prog->jited = 0; 2371 prog->jited_len = 0; 2372 } 2373 if (header) { 2374 bpf_arch_text_copy(&ro_header->size, &header->size, 2375 sizeof(header->size)); 2376 bpf_jit_binary_pack_free(ro_header, header); 2377 } 2378 goto out_off; 2379 } 2380 2381 bool bpf_jit_supports_private_stack(void) 2382 { 2383 return true; 2384 } 2385 2386 bool bpf_jit_supports_kfunc_call(void) 2387 { 2388 return true; 2389 } 2390 2391 bool bpf_jit_supports_stack_args(void) 2392 { 2393 return true; 2394 } 2395 2396 bool bpf_jit_supports_arena_args(void) 2397 { 2398 return true; 2399 } 2400 2401 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 2402 { 2403 if (!aarch64_insn_copy(dst, src, len)) 2404 return ERR_PTR(-EINVAL); 2405 return dst; 2406 } 2407 2408 u64 bpf_jit_alloc_exec_limit(void) 2409 { 2410 return VMALLOC_END - VMALLOC_START; 2411 } 2412 2413 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 2414 bool bpf_jit_supports_subprog_tailcalls(void) 2415 { 2416 return true; 2417 } 2418 2419 static void invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_node *node, 2420 int bargs_off, int retval_off, int run_ctx_off, 2421 bool save_ret) 2422 { 2423 __le32 *branch; 2424 u64 enter_prog; 2425 u64 exit_prog; 2426 struct bpf_prog *p = node->link->prog; 2427 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2428 2429 enter_prog = (u64)bpf_trampoline_enter(p); 2430 exit_prog = (u64)bpf_trampoline_exit(p); 2431 2432 if (node->cookie == 0) { 2433 /* if cookie is zero, one instruction is enough to store it */ 2434 emit(A64_STR64I(A64_ZR, A64_SP, run_ctx_off + cookie_off), ctx); 2435 } else { 2436 emit_a64_mov_i64(A64_R(10), node->cookie, ctx); 2437 emit(A64_STR64I(A64_R(10), A64_SP, run_ctx_off + cookie_off), 2438 ctx); 2439 } 2440 2441 /* save p to callee saved register x19 to avoid loading p with mov_i64 2442 * each time. 2443 */ 2444 emit_addr_mov_i64(A64_R(19), (const u64)p, ctx); 2445 2446 /* arg1: prog */ 2447 emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); 2448 /* arg2: &run_ctx */ 2449 emit(A64_ADD_I(1, A64_R(1), A64_SP, run_ctx_off), ctx); 2450 2451 emit_call(enter_prog, ctx); 2452 2453 /* save return value to callee saved register x20 */ 2454 emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx); 2455 2456 /* if (__bpf_prog_enter(prog) == 0) 2457 * goto skip_exec_of_prog; 2458 */ 2459 branch = ctx->image + ctx->idx; 2460 emit(A64_NOP, ctx); 2461 2462 emit(A64_ADD_I(1, A64_R(0), A64_SP, bargs_off), ctx); 2463 if (!p->jited) 2464 emit_addr_mov_i64(A64_R(1), (const u64)p->insnsi, ctx); 2465 2466 emit_call((const u64)p->bpf_func, ctx); 2467 2468 if (save_ret) 2469 emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); 2470 2471 if (ctx->image) { 2472 int offset = &ctx->image[ctx->idx] - branch; 2473 *branch = cpu_to_le32(A64_CBZ(1, A64_R(0), offset)); 2474 } 2475 2476 /* arg1: prog */ 2477 emit(A64_MOV(1, A64_R(0), A64_R(19)), ctx); 2478 /* arg2: start time */ 2479 emit(A64_MOV(1, A64_R(1), A64_R(20)), ctx); 2480 /* arg3: &run_ctx */ 2481 emit(A64_ADD_I(1, A64_R(2), A64_SP, run_ctx_off), ctx); 2482 2483 emit_call(exit_prog, ctx); 2484 } 2485 2486 static void invoke_bpf_mod_ret(struct jit_ctx *ctx, struct bpf_tramp_nodes *tn, 2487 int bargs_off, int retval_off, int run_ctx_off, 2488 __le32 **branches) 2489 { 2490 int i; 2491 2492 /* The first fmod_ret program will receive a garbage return value. 2493 * Set this to 0 to avoid confusing the program. 2494 */ 2495 emit(A64_STR64I(A64_ZR, A64_SP, retval_off), ctx); 2496 for (i = 0; i < tn->nr_nodes; i++) { 2497 invoke_bpf_prog(ctx, tn->nodes[i], bargs_off, retval_off, 2498 run_ctx_off, true); 2499 /* if (*(u64 *)(sp + retval_off) != 0) 2500 * goto do_fexit; 2501 */ 2502 emit(A64_LDR64I(A64_R(10), A64_SP, retval_off), ctx); 2503 /* Save the location of branch, and generate a nop. 2504 * This nop will be replaced with a cbnz later. 2505 */ 2506 branches[i] = ctx->image + ctx->idx; 2507 emit(A64_NOP, ctx); 2508 } 2509 } 2510 2511 struct arg_aux { 2512 /* how many args are passed through registers, the rest of the args are 2513 * passed through stack 2514 */ 2515 int args_in_regs; 2516 /* how many registers are used to pass arguments */ 2517 int regs_for_args; 2518 /* how much stack is used for additional args passed to bpf program 2519 * that did not fit in original function registers 2520 */ 2521 int bstack_for_args; 2522 /* home much stack is used for additional args passed to the 2523 * original function when called from trampoline (this one needs 2524 * arguments to be properly aligned) 2525 */ 2526 int ostack_for_args; 2527 }; 2528 2529 static int calc_arg_aux(const struct btf_func_model *m, 2530 struct arg_aux *a) 2531 { 2532 int stack_slots, nregs, slots, i; 2533 2534 /* verifier ensures m->nr_args <= MAX_BPF_FUNC_ARGS */ 2535 for (i = 0, nregs = 0; i < m->nr_args; i++) { 2536 slots = (m->arg_size[i] + 7) / 8; 2537 if (nregs + slots <= 8) /* passed through register ? */ 2538 nregs += slots; 2539 else 2540 break; 2541 } 2542 2543 a->args_in_regs = i; 2544 a->regs_for_args = nregs; 2545 a->ostack_for_args = 0; 2546 a->bstack_for_args = 0; 2547 2548 /* the rest arguments are passed through stack */ 2549 for (; i < m->nr_args; i++) { 2550 stack_slots = (m->arg_size[i] + 7) / 8; 2551 a->bstack_for_args += stack_slots * 8; 2552 a->ostack_for_args = a->ostack_for_args + stack_slots * 8; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static void clear_garbage(struct jit_ctx *ctx, int reg, int effective_bytes) 2559 { 2560 if (effective_bytes) { 2561 int garbage_bits = 64 - 8 * effective_bytes; 2562 #ifdef CONFIG_CPU_BIG_ENDIAN 2563 /* garbage bits are at the right end */ 2564 emit(A64_LSR(1, reg, reg, garbage_bits), ctx); 2565 emit(A64_LSL(1, reg, reg, garbage_bits), ctx); 2566 #else 2567 /* garbage bits are at the left end */ 2568 emit(A64_LSL(1, reg, reg, garbage_bits), ctx); 2569 emit(A64_LSR(1, reg, reg, garbage_bits), ctx); 2570 #endif 2571 } 2572 } 2573 2574 /* 2575 * Convert an arena kernel address into the arena pointer form on its way into 2576 * the BPF ctx, dst = (u32)(src - kern_vm_start), with @base_lo holding the low 2577 * 32 bits of kern_vm_start. A nullable arg preserves NULL, tested on the full 2578 * 64-bit kernel pointer. The 32-bit subtraction both truncates and clears the 2579 * upper half, so the stored value satisfies the JIT invariant for arena 2580 * pointer registers. 2581 */ 2582 static void emit_arena_arg_conv(struct jit_ctx *ctx, u8 dst, u8 src, bool nullable, u8 base_lo) 2583 { 2584 if (nullable) { 2585 if (dst != src) 2586 emit(A64_MOV(1, dst, src), ctx); 2587 /* skip the subtraction so that NULL stays NULL */ 2588 emit(A64_CBZ(1, dst, 2), ctx); 2589 src = dst; 2590 } 2591 emit(A64_SUB(0, dst, src, base_lo), ctx); 2592 } 2593 2594 static void save_args(struct jit_ctx *ctx, int bargs_off, int oargs_off, 2595 const struct btf_func_model *m, const struct arg_aux *a, 2596 bool for_call_origin, bool is_struct_ops, u64 arena_base) 2597 { 2598 u8 tmp = bpf2a64[TMP_REG_1]; 2599 u8 base_lo = bpf2a64[TMP_REG_2]; 2600 int i, reg, doff, soff, slots; 2601 2602 /* only the low 32 bits of the base take part in the subtraction */ 2603 if (arena_base) 2604 emit_a64_mov_i(0, base_lo, (s32)(u32)arena_base, ctx); 2605 2606 /* store arguments to the stack for the bpf program, or restore 2607 * arguments from stack for the original function 2608 */ 2609 for (i = 0, reg = 0; i < a->args_in_regs; i++) { 2610 bool arena_arg = arena_base && (m->arg_flags[i] & BTF_FMODEL_ARENA_ARG); 2611 bool nullable = m->arg_flags[i] & BTF_FMODEL_NULLABLE_ARG; 2612 2613 slots = (m->arg_size[i] + 7) / 8; 2614 while (slots-- > 0) { 2615 if (for_call_origin) { 2616 emit(A64_LDR64I(reg, A64_SP, bargs_off), ctx); 2617 } else if (arena_arg) { 2618 emit_arena_arg_conv(ctx, tmp, reg, nullable, base_lo); 2619 emit(A64_STR64I(tmp, A64_SP, bargs_off), ctx); 2620 } else { 2621 emit(A64_STR64I(reg, A64_SP, bargs_off), ctx); 2622 } 2623 reg++; 2624 bargs_off += 8; 2625 } 2626 } 2627 2628 /* 2629 * On-stack arguments start above the frame(s) pushed by the trampoline 2630 * prologue. Entered through the fentry call from a traced function, the 2631 * prologue saves both the parent (FP/x9) and the traced function 2632 * (FP/LR) frames, so the arguments start at FP + 32. A struct_ops 2633 * callback is called indirectly and only the FP/LR frame is saved, so 2634 * they start at FP + 16. 2635 */ 2636 soff = is_struct_ops ? 16 : 32; 2637 doff = (for_call_origin ? oargs_off : bargs_off); 2638 2639 /* save on stack arguments */ 2640 for (i = a->args_in_regs; i < m->nr_args; i++) { 2641 bool arena_arg = arena_base && (m->arg_flags[i] & BTF_FMODEL_ARENA_ARG); 2642 bool nullable = m->arg_flags[i] & BTF_FMODEL_NULLABLE_ARG; 2643 2644 slots = (m->arg_size[i] + 7) / 8; 2645 /* verifier ensures arg_size <= 16, so slots equals 1 or 2 */ 2646 while (slots-- > 0) { 2647 emit(A64_LDR64I(tmp, A64_FP, soff), ctx); 2648 /* if there is unused space in the last slot, clear 2649 * the garbage contained in the space. 2650 */ 2651 if (slots == 0 && !for_call_origin) 2652 clear_garbage(ctx, tmp, m->arg_size[i] % 8); 2653 /* 2654 * No guard on for_call_origin here: only the indirect 2655 * trampoline is given a base, and it never calls the 2656 * original function, so arguments are never converted 2657 * on their way back out to it. See the WARN_ON_ONCE() 2658 * in prepare_trampoline(). 2659 */ 2660 if (arena_arg) 2661 emit_arena_arg_conv(ctx, tmp, tmp, nullable, base_lo); 2662 emit(A64_STR64I(tmp, A64_SP, doff), ctx); 2663 soff += 8; 2664 doff += 8; 2665 } 2666 } 2667 } 2668 2669 static void restore_args(struct jit_ctx *ctx, int bargs_off, int nregs) 2670 { 2671 int reg; 2672 2673 for (reg = 0; reg < nregs; reg++) { 2674 emit(A64_LDR64I(reg, A64_SP, bargs_off), ctx); 2675 bargs_off += 8; 2676 } 2677 } 2678 2679 static void store_func_meta(struct jit_ctx *ctx, u64 func_meta, int func_meta_off) 2680 { 2681 emit_a64_mov_i64(A64_R(10), func_meta, ctx); 2682 emit(A64_STR64I(A64_R(10), A64_SP, func_meta_off), ctx); 2683 } 2684 2685 /* Based on the x86's implementation of arch_prepare_bpf_trampoline(). 2686 * 2687 * bpf prog and function entry before bpf trampoline hooked: 2688 * mov x9, lr 2689 * nop 2690 * 2691 * bpf prog and function entry after bpf trampoline hooked: 2692 * mov x9, lr 2693 * bl <bpf_trampoline or plt> 2694 * 2695 */ 2696 static int prepare_trampoline(struct jit_ctx *ctx, struct bpf_tramp_image *im, 2697 struct bpf_tramp_nodes *tnodes, void *func_addr, 2698 const struct btf_func_model *m, 2699 const struct arg_aux *a, 2700 u32 flags) 2701 { 2702 int i; 2703 int stack_size; 2704 int retaddr_off; 2705 int regs_off; 2706 int retval_off; 2707 int bargs_off; 2708 int func_meta_off; 2709 int ip_off; 2710 int run_ctx_off; 2711 int oargs_off; 2712 int nfuncargs; 2713 struct bpf_tramp_nodes *fentry = &tnodes[BPF_TRAMP_FENTRY]; 2714 struct bpf_tramp_nodes *fexit = &tnodes[BPF_TRAMP_FEXIT]; 2715 struct bpf_tramp_nodes *fmod_ret = &tnodes[BPF_TRAMP_MODIFY_RETURN]; 2716 bool save_ret; 2717 __le32 **branches = NULL; 2718 bool is_struct_ops = is_struct_ops_tramp(fentry); 2719 int cookie_off, cookie_cnt, cookie_bargs_off; 2720 int fsession_cnt = bpf_fsession_cnt(tnodes); 2721 u64 arena_base; 2722 u64 func_meta; 2723 2724 /* 2725 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is explicitly 2726 * incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG because 2727 * @func_addr. Arena conversion relies on this: bpf_tramp_arena_base() 2728 * only returns a base for the indirect trampoline, which therefore 2729 * never calls the original function with converted arguments. 2730 */ 2731 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 2732 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 2733 2734 arena_base = bpf_tramp_arena_base(m, tnodes, flags); 2735 2736 /* trampoline stack layout: 2737 * [ parent ip ] 2738 * [ FP ] 2739 * SP + retaddr_off [ self ip ] 2740 * [ FP ] 2741 * 2742 * [ padding ] align SP to multiples of 16 2743 * 2744 * [ x20 ] callee saved reg x20 2745 * SP + regs_off [ x19 ] callee saved reg x19 2746 * 2747 * SP + retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 2748 * BPF_TRAMP_F_RET_FENTRY_RET 2749 * [ arg reg N ] 2750 * [ ... ] 2751 * SP + bargs_off [ arg reg 1 ] for bpf 2752 * 2753 * SP + func_meta_off [ regs count, etc ] 2754 * 2755 * SP + ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 2756 * 2757 * [ stack cookie N ] 2758 * [ ... ] 2759 * SP + cookie_off [ stack cookie 1 ] 2760 * 2761 * SP + run_ctx_off [ bpf_tramp_run_ctx ] 2762 * 2763 * [ stack arg N ] 2764 * [ ... ] 2765 * SP + oargs_off [ stack arg 1 ] for original func 2766 */ 2767 2768 stack_size = 0; 2769 oargs_off = stack_size; 2770 if (flags & BPF_TRAMP_F_CALL_ORIG) 2771 stack_size += a->ostack_for_args; 2772 2773 run_ctx_off = stack_size; 2774 /* room for bpf_tramp_run_ctx */ 2775 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 2776 2777 cookie_off = stack_size; 2778 /* room for session cookies */ 2779 cookie_cnt = bpf_fsession_cookie_cnt(tnodes); 2780 stack_size += cookie_cnt * 8; 2781 2782 ip_off = stack_size; 2783 /* room for IP address argument */ 2784 if (flags & BPF_TRAMP_F_IP_ARG) 2785 stack_size += 8; 2786 2787 func_meta_off = stack_size; 2788 /* room for function metadata, such as regs count */ 2789 stack_size += 8; 2790 2791 bargs_off = stack_size; 2792 /* room for args */ 2793 nfuncargs = a->regs_for_args + a->bstack_for_args / 8; 2794 stack_size += 8 * nfuncargs; 2795 2796 /* room for return value */ 2797 retval_off = stack_size; 2798 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 2799 if (save_ret) 2800 stack_size += 8; 2801 2802 /* room for callee saved registers, currently x19 and x20 are used */ 2803 regs_off = stack_size; 2804 stack_size += 16; 2805 2806 /* round up to multiples of 16 to avoid SPAlignmentFault */ 2807 stack_size = round_up(stack_size, 16); 2808 2809 /* return address locates above FP */ 2810 retaddr_off = stack_size + 8; 2811 2812 if (flags & BPF_TRAMP_F_INDIRECT) { 2813 /* 2814 * Indirect call for bpf_struct_ops 2815 */ 2816 emit_kcfi(cfi_get_func_hash(func_addr), ctx); 2817 } 2818 /* bpf trampoline may be invoked by 3 instruction types: 2819 * 1. bl, attached to bpf prog or kernel function via short jump 2820 * 2. br, attached to bpf prog or kernel function via long jump 2821 * 3. blr, working as a function pointer, used by struct_ops. 2822 * So BTI_JC should used here to support both br and blr. 2823 */ 2824 emit_bti(A64_BTI_JC, ctx); 2825 2826 /* x9 is not set for struct_ops */ 2827 if (!is_struct_ops) { 2828 /* frame for parent function */ 2829 emit(A64_PUSH(A64_FP, A64_R(9), A64_SP), ctx); 2830 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 2831 } 2832 2833 /* frame for patched function for tracing, or caller for struct_ops */ 2834 emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); 2835 emit(A64_MOV(1, A64_FP, A64_SP), ctx); 2836 2837 /* allocate stack space */ 2838 emit(A64_SUB_I(1, A64_SP, A64_SP, stack_size), ctx); 2839 2840 if (flags & BPF_TRAMP_F_IP_ARG) { 2841 /* save ip address of the traced function */ 2842 emit_addr_mov_i64(A64_R(10), (const u64)func_addr, ctx); 2843 emit(A64_STR64I(A64_R(10), A64_SP, ip_off), ctx); 2844 } 2845 2846 /* save function metadata */ 2847 func_meta = nfuncargs; 2848 store_func_meta(ctx, func_meta, func_meta_off); 2849 2850 /* save args for bpf */ 2851 save_args(ctx, bargs_off, oargs_off, m, a, false, is_struct_ops, arena_base); 2852 2853 /* save callee saved registers */ 2854 emit(A64_STR64I(A64_R(19), A64_SP, regs_off), ctx); 2855 emit(A64_STR64I(A64_R(20), A64_SP, regs_off + 8), ctx); 2856 2857 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2858 /* for the first pass, assume the worst case */ 2859 if (!ctx->image) 2860 ctx->idx += 4; 2861 else 2862 emit_a64_mov_i64(A64_R(0), (const u64)im, ctx); 2863 emit_call((const u64)__bpf_tramp_enter, ctx); 2864 } 2865 2866 if (fsession_cnt) { 2867 /* clear all the session cookies' value */ 2868 emit(A64_MOVZ(1, A64_R(10), 0, 0), ctx); 2869 for (int i = 0; i < cookie_cnt; i++) 2870 emit(A64_STR64I(A64_R(10), A64_SP, cookie_off + 8 * i), ctx); 2871 /* clear the return value to make sure fentry always gets 0 */ 2872 emit(A64_STR64I(A64_R(10), A64_SP, retval_off), ctx); 2873 } 2874 2875 cookie_bargs_off = (bargs_off - cookie_off) / 8; 2876 for (i = 0; i < fentry->nr_nodes; i++) { 2877 if (bpf_prog_calls_session_cookie(fentry->nodes[i])) { 2878 u64 meta = func_meta | (cookie_bargs_off << BPF_TRAMP_COOKIE_INDEX_SHIFT); 2879 2880 store_func_meta(ctx, meta, func_meta_off); 2881 cookie_bargs_off--; 2882 } 2883 invoke_bpf_prog(ctx, fentry->nodes[i], bargs_off, 2884 retval_off, run_ctx_off, 2885 flags & BPF_TRAMP_F_RET_FENTRY_RET); 2886 } 2887 2888 if (fmod_ret->nr_nodes) { 2889 branches = kcalloc(fmod_ret->nr_nodes, sizeof(__le32 *), 2890 GFP_KERNEL); 2891 if (!branches) 2892 return -ENOMEM; 2893 2894 invoke_bpf_mod_ret(ctx, fmod_ret, bargs_off, retval_off, 2895 run_ctx_off, branches); 2896 } 2897 2898 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2899 /* the original func takes kernel addresses, never converted ones */ 2900 save_args(ctx, bargs_off, oargs_off, m, a, true, is_struct_ops, 0); 2901 /* call original func */ 2902 emit(A64_LDR64I(A64_R(10), A64_SP, retaddr_off), ctx); 2903 emit(A64_ADR(A64_LR, AARCH64_INSN_SIZE * 2), ctx); 2904 emit(A64_RET(A64_R(10)), ctx); 2905 /* store return value */ 2906 emit(A64_STR64I(A64_R(0), A64_SP, retval_off), ctx); 2907 /* reserve a nop for bpf_tramp_image_put */ 2908 im->ip_after_call = ctx->ro_image + ctx->idx; 2909 emit(A64_NOP, ctx); 2910 } 2911 2912 /* update the branches saved in invoke_bpf_mod_ret with cbnz */ 2913 for (i = 0; i < fmod_ret->nr_nodes && ctx->image != NULL; i++) { 2914 int offset = &ctx->image[ctx->idx] - branches[i]; 2915 *branches[i] = cpu_to_le32(A64_CBNZ(1, A64_R(10), offset)); 2916 } 2917 2918 /* set the "is_return" flag for fsession */ 2919 func_meta |= (1ULL << BPF_TRAMP_IS_RETURN_SHIFT); 2920 if (fsession_cnt) 2921 store_func_meta(ctx, func_meta, func_meta_off); 2922 2923 cookie_bargs_off = (bargs_off - cookie_off) / 8; 2924 for (i = 0; i < fexit->nr_nodes; i++) { 2925 if (bpf_prog_calls_session_cookie(fexit->nodes[i])) { 2926 u64 meta = func_meta | (cookie_bargs_off << BPF_TRAMP_COOKIE_INDEX_SHIFT); 2927 2928 store_func_meta(ctx, meta, func_meta_off); 2929 cookie_bargs_off--; 2930 } 2931 invoke_bpf_prog(ctx, fexit->nodes[i], bargs_off, retval_off, 2932 run_ctx_off, false); 2933 } 2934 2935 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2936 im->ip_epilogue = ctx->ro_image + ctx->idx; 2937 /* for the first pass, assume the worst case */ 2938 if (!ctx->image) 2939 ctx->idx += 4; 2940 else 2941 emit_a64_mov_i64(A64_R(0), (const u64)im, ctx); 2942 emit_call((const u64)__bpf_tramp_exit, ctx); 2943 } 2944 2945 if (flags & BPF_TRAMP_F_RESTORE_REGS) 2946 restore_args(ctx, bargs_off, a->regs_for_args); 2947 2948 /* restore callee saved register x19 and x20 */ 2949 emit(A64_LDR64I(A64_R(19), A64_SP, regs_off), ctx); 2950 emit(A64_LDR64I(A64_R(20), A64_SP, regs_off + 8), ctx); 2951 2952 if (save_ret) 2953 emit(A64_LDR64I(A64_R(0), A64_SP, retval_off), ctx); 2954 2955 /* reset SP */ 2956 emit(A64_MOV(1, A64_SP, A64_FP), ctx); 2957 2958 if (is_struct_ops) { 2959 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 2960 emit(A64_RET(A64_LR), ctx); 2961 } else { 2962 /* pop frames */ 2963 emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); 2964 emit(A64_POP(A64_FP, A64_R(9), A64_SP), ctx); 2965 2966 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 2967 /* skip patched function, return to parent */ 2968 emit(A64_MOV(1, A64_LR, A64_R(9)), ctx); 2969 emit(A64_RET(A64_R(9)), ctx); 2970 } else { 2971 /* return to patched function */ 2972 emit(A64_MOV(1, A64_R(10), A64_LR), ctx); 2973 emit(A64_MOV(1, A64_LR, A64_R(9)), ctx); 2974 emit(A64_RET(A64_R(10)), ctx); 2975 } 2976 } 2977 2978 kfree(branches); 2979 2980 return ctx->idx; 2981 } 2982 2983 bool bpf_jit_supports_fsession(void) 2984 { 2985 return true; 2986 } 2987 2988 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 2989 struct bpf_tramp_nodes *tnodes, void *func_addr) 2990 { 2991 struct jit_ctx ctx = { 2992 .image = NULL, 2993 .idx = 0, 2994 }; 2995 struct bpf_tramp_image im; 2996 struct arg_aux aaux; 2997 int ret; 2998 2999 ret = calc_arg_aux(m, &aaux); 3000 if (ret < 0) 3001 return ret; 3002 3003 ret = prepare_trampoline(&ctx, &im, tnodes, func_addr, m, &aaux, flags); 3004 if (ret < 0) 3005 return ret; 3006 3007 return ret < 0 ? ret : ret * AARCH64_INSN_SIZE; 3008 } 3009 3010 void *arch_alloc_bpf_trampoline(unsigned int size) 3011 { 3012 return bpf_prog_pack_alloc(size, jit_fill_hole, false); 3013 } 3014 3015 void arch_free_bpf_trampoline(void *image, unsigned int size) 3016 { 3017 bpf_prog_pack_free(image, size); 3018 } 3019 3020 int arch_protect_bpf_trampoline(void *image, unsigned int size) 3021 { 3022 return 0; 3023 } 3024 3025 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image, 3026 void *ro_image_end, const struct btf_func_model *m, 3027 u32 flags, struct bpf_tramp_nodes *tnodes, 3028 void *func_addr) 3029 { 3030 u32 size = ro_image_end - ro_image; 3031 struct arg_aux aaux; 3032 void *image, *tmp; 3033 int ret; 3034 3035 /* image doesn't need to be in module memory range, so we can 3036 * use kvmalloc. 3037 */ 3038 image = kvmalloc(size, GFP_KERNEL); 3039 if (!image) 3040 return -ENOMEM; 3041 3042 struct jit_ctx ctx = { 3043 .image = image, 3044 .ro_image = ro_image, 3045 .idx = 0, 3046 .write = true, 3047 }; 3048 3049 3050 jit_fill_hole(image, (unsigned int)(ro_image_end - ro_image)); 3051 ret = calc_arg_aux(m, &aaux); 3052 if (ret) 3053 goto out; 3054 ret = prepare_trampoline(&ctx, im, tnodes, func_addr, m, &aaux, flags); 3055 3056 if (ret > 0 && validate_code(&ctx) < 0) { 3057 ret = -EINVAL; 3058 goto out; 3059 } 3060 3061 if (ret > 0) 3062 ret *= AARCH64_INSN_SIZE; 3063 3064 tmp = bpf_arch_text_copy(ro_image, image, size); 3065 if (IS_ERR(tmp)) { 3066 ret = PTR_ERR(tmp); 3067 goto out; 3068 } 3069 3070 out: 3071 kvfree(image); 3072 return ret; 3073 } 3074 3075 static bool is_long_jump(void *ip, void *target) 3076 { 3077 long offset; 3078 3079 /* NULL target means this is a NOP */ 3080 if (!target) 3081 return false; 3082 3083 offset = (long)target - (long)ip; 3084 return offset < -SZ_128M || offset >= SZ_128M; 3085 } 3086 3087 static int gen_branch_or_nop(enum aarch64_insn_branch_type type, void *ip, 3088 void *addr, void *plt, u32 *insn) 3089 { 3090 void *target; 3091 3092 if (!addr) { 3093 *insn = aarch64_insn_gen_nop(); 3094 return 0; 3095 } 3096 3097 if (is_long_jump(ip, addr)) 3098 target = plt; 3099 else 3100 target = addr; 3101 3102 *insn = aarch64_insn_gen_branch_imm((unsigned long)ip, 3103 (unsigned long)target, 3104 type); 3105 3106 return *insn != AARCH64_BREAK_FAULT ? 0 : -EFAULT; 3107 } 3108 3109 /* Replace the branch instruction from @ip to @old_addr in a bpf prog or a bpf 3110 * trampoline with the branch instruction from @ip to @new_addr. If @old_addr 3111 * or @new_addr is NULL, the old or new instruction is NOP. 3112 * 3113 * When @ip is the bpf prog entry, a bpf trampoline is being attached or 3114 * detached. Since bpf trampoline and bpf prog are allocated separately with 3115 * vmalloc, the address distance may exceed 128MB, the maximum branch range. 3116 * So long jump should be handled. 3117 * 3118 * When a bpf prog is constructed, a plt pointing to empty trampoline 3119 * dummy_tramp is placed at the end: 3120 * 3121 * bpf_prog: 3122 * mov x9, lr 3123 * nop // patchsite 3124 * ... 3125 * ret 3126 * 3127 * plt: 3128 * ldr x10, target 3129 * br x10 3130 * target: 3131 * .quad dummy_tramp // plt target 3132 * 3133 * This is also the state when no trampoline is attached. 3134 * 3135 * When a short-jump bpf trampoline is attached, the patchsite is patched 3136 * to a bl instruction to the trampoline directly: 3137 * 3138 * bpf_prog: 3139 * mov x9, lr 3140 * bl <short-jump bpf trampoline address> // patchsite 3141 * ... 3142 * ret 3143 * 3144 * plt: 3145 * ldr x10, target 3146 * br x10 3147 * target: 3148 * .quad dummy_tramp // plt target 3149 * 3150 * When a long-jump bpf trampoline is attached, the plt target is filled with 3151 * the trampoline address and the patchsite is patched to a bl instruction to 3152 * the plt: 3153 * 3154 * bpf_prog: 3155 * mov x9, lr 3156 * bl plt // patchsite 3157 * ... 3158 * ret 3159 * 3160 * plt: 3161 * ldr x10, target 3162 * br x10 3163 * target: 3164 * .quad <long-jump bpf trampoline address> // plt target 3165 * 3166 * The dummy_tramp is used to prevent another CPU from jumping to unknown 3167 * locations during the patching process, making the patching process easier. 3168 */ 3169 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type old_t, 3170 enum bpf_text_poke_type new_t, void *old_addr, 3171 void *new_addr) 3172 { 3173 int ret; 3174 u32 old_insn; 3175 u32 new_insn; 3176 u32 replaced; 3177 struct bpf_plt *plt = NULL; 3178 unsigned long size = 0UL; 3179 unsigned long offset = ~0UL; 3180 enum aarch64_insn_branch_type branch_type; 3181 char namebuf[KSYM_NAME_LEN]; 3182 void *image = NULL; 3183 u64 plt_target = 0ULL; 3184 bool poking_bpf_entry; 3185 3186 if (!bpf_address_lookup((unsigned long)ip, &size, &offset, namebuf)) 3187 /* Only poking bpf text is supported. Since kernel function 3188 * entry is set up by ftrace, we reply on ftrace to poke kernel 3189 * functions. 3190 */ 3191 return -ENOTSUPP; 3192 3193 image = ip - offset; 3194 /* zero offset means we're poking bpf prog entry */ 3195 poking_bpf_entry = (offset == 0UL); 3196 3197 /* bpf prog entry, find plt and the real patchsite */ 3198 if (poking_bpf_entry) { 3199 /* plt locates at the end of bpf prog */ 3200 plt = image + size - PLT_TARGET_OFFSET; 3201 3202 /* skip to the nop instruction in bpf prog entry: 3203 * bti c // if BTI enabled 3204 * mov x9, x30 3205 * nop 3206 */ 3207 ip = image + POKE_OFFSET * AARCH64_INSN_SIZE; 3208 } 3209 3210 /* long jump is only possible at bpf prog entry */ 3211 if (WARN_ON((is_long_jump(ip, new_addr) || is_long_jump(ip, old_addr)) && 3212 !poking_bpf_entry)) 3213 return -EINVAL; 3214 3215 branch_type = old_t == BPF_MOD_CALL ? AARCH64_INSN_BRANCH_LINK : 3216 AARCH64_INSN_BRANCH_NOLINK; 3217 if (gen_branch_or_nop(branch_type, ip, old_addr, plt, &old_insn) < 0) 3218 return -EFAULT; 3219 3220 branch_type = new_t == BPF_MOD_CALL ? AARCH64_INSN_BRANCH_LINK : 3221 AARCH64_INSN_BRANCH_NOLINK; 3222 if (gen_branch_or_nop(branch_type, ip, new_addr, plt, &new_insn) < 0) 3223 return -EFAULT; 3224 3225 if (is_long_jump(ip, new_addr)) 3226 plt_target = (u64)new_addr; 3227 else if (is_long_jump(ip, old_addr)) 3228 /* if the old target is a long jump and the new target is not, 3229 * restore the plt target to dummy_tramp, so there is always a 3230 * legal and harmless address stored in plt target, and we'll 3231 * never jump from plt to an unknown place. 3232 */ 3233 plt_target = (u64)&dummy_tramp; 3234 3235 if (plt_target) { 3236 /* non-zero plt_target indicates we're patching a bpf prog, 3237 * which is read only. 3238 */ 3239 if (set_memory_rw(PAGE_MASK & ((uintptr_t)&plt->target), 1)) 3240 return -EFAULT; 3241 WRITE_ONCE(plt->target, plt_target); 3242 set_memory_ro(PAGE_MASK & ((uintptr_t)&plt->target), 1); 3243 /* since plt target points to either the new trampoline 3244 * or dummy_tramp, even if another CPU reads the old plt 3245 * target value before fetching the bl instruction to plt, 3246 * it will be brought back by dummy_tramp, so no barrier is 3247 * required here. 3248 */ 3249 } 3250 3251 /* if the old target and the new target are both long jumps, no 3252 * patching is required 3253 */ 3254 if (old_insn == new_insn) 3255 return 0; 3256 3257 mutex_lock(&text_mutex); 3258 if (aarch64_insn_read(ip, &replaced)) { 3259 ret = -EFAULT; 3260 goto out; 3261 } 3262 3263 if (replaced != old_insn) { 3264 ret = -EFAULT; 3265 goto out; 3266 } 3267 3268 /* We call aarch64_insn_patch_text_nosync() to replace instruction 3269 * atomically, so no other CPUs will fetch a half-new and half-old 3270 * instruction. But there is chance that another CPU executes the 3271 * old instruction after the patching operation finishes (e.g., 3272 * pipeline not flushed, or icache not synchronized yet). 3273 * 3274 * 1. when a new trampoline is attached, it is not a problem for 3275 * different CPUs to jump to different trampolines temporarily. 3276 * 3277 * 2. when an old trampoline is freed, we should wait for all other 3278 * CPUs to exit the trampoline and make sure the trampoline is no 3279 * longer reachable, since bpf_tramp_image_put() function already 3280 * uses percpu_ref and task-based rcu to do the sync, no need to call 3281 * the sync version here, see bpf_tramp_image_put() for details. 3282 */ 3283 ret = aarch64_insn_patch_text_nosync(ip, new_insn); 3284 out: 3285 mutex_unlock(&text_mutex); 3286 3287 return ret; 3288 } 3289 3290 bool bpf_jit_supports_ptr_xchg(void) 3291 { 3292 return true; 3293 } 3294 3295 bool bpf_jit_supports_exceptions(void) 3296 { 3297 /* We unwind through both kernel frames starting from within bpf_throw 3298 * call and BPF frames. Therefore we require FP unwinder to be enabled 3299 * to walk kernel frames and reach BPF frames in the stack trace. 3300 * ARM64 kernel is always compiled with CONFIG_FRAME_POINTER=y 3301 */ 3302 return true; 3303 } 3304 3305 bool bpf_jit_supports_arena(void) 3306 { 3307 return true; 3308 } 3309 3310 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 3311 { 3312 if (!in_arena) 3313 return true; 3314 switch (insn->code) { 3315 case BPF_STX | BPF_ATOMIC | BPF_W: 3316 case BPF_STX | BPF_ATOMIC | BPF_DW: 3317 if (!bpf_atomic_is_load_store(insn) && 3318 !cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) 3319 return false; 3320 } 3321 return true; 3322 } 3323 3324 bool bpf_jit_supports_percpu_insn(void) 3325 { 3326 return true; 3327 } 3328 3329 bool bpf_jit_bypass_spec_v4(void) 3330 { 3331 /* In case of arm64, we rely on the firmware mitigation of Speculative 3332 * Store Bypass as controlled via the ssbd kernel parameter. Whenever 3333 * the mitigation is enabled, it works for all of the kernel code with 3334 * no need to provide any additional instructions. Therefore, skip 3335 * inserting nospec insns against Spectre v4. 3336 */ 3337 return true; 3338 } 3339 3340 bool bpf_jit_supports_timed_may_goto(void) 3341 { 3342 return true; 3343 } 3344 3345 bool bpf_jit_inlines_helper_call(s32 imm) 3346 { 3347 switch (imm) { 3348 case BPF_FUNC_get_smp_processor_id: 3349 case BPF_FUNC_get_current_task: 3350 case BPF_FUNC_get_current_task_btf: 3351 return true; 3352 default: 3353 return false; 3354 } 3355 } 3356 3357 void bpf_jit_free(struct bpf_prog *prog) 3358 { 3359 if (prog->jited) { 3360 struct arm64_jit_data *jit_data = prog->aux->jit_data; 3361 struct bpf_binary_header *hdr; 3362 void __percpu *priv_stack_ptr; 3363 int priv_stack_alloc_sz; 3364 3365 /* 3366 * If we fail the final pass of JIT (from jit_subprogs), 3367 * the program may not be finalized yet. Call finalize here 3368 * before freeing it. 3369 */ 3370 if (jit_data) { 3371 bpf_jit_binary_pack_finalize(jit_data->ro_header, jit_data->header); 3372 kfree(jit_data); 3373 } 3374 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3375 hdr = bpf_jit_binary_pack_hdr(prog); 3376 bpf_jit_binary_pack_free(hdr, NULL); 3377 priv_stack_ptr = prog->aux->priv_stack_ptr; 3378 if (priv_stack_ptr) { 3379 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 16) + 3380 2 * PRIV_STACK_GUARD_SZ; 3381 priv_stack_check_guard(priv_stack_ptr, priv_stack_alloc_sz, prog); 3382 free_percpu(prog->aux->priv_stack_ptr); 3383 } 3384 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3385 } 3386 3387 bpf_prog_unlock_free(prog); 3388 } 3389