1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28 29#include "proc-macros.S" 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#else 34#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 35#endif 36 37#define TCR_SMP_FLAGS TCR_SHARED 38 39/* PTWs cacheable, inner/outer WBWA */ 40#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 41 42#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 43 44/* 45 * cpu_do_idle() 46 * 47 * Idle the processor (wait for interrupt). 48 */ 49ENTRY(cpu_do_idle) 50 dsb sy // WFI may enter a low-power mode 51 wfi 52 ret 53ENDPROC(cpu_do_idle) 54 55#ifdef CONFIG_CPU_PM 56/** 57 * cpu_do_suspend - save CPU registers context 58 * 59 * x0: virtual address of context pointer 60 */ 61ENTRY(cpu_do_suspend) 62 mrs x2, tpidr_el0 63 mrs x3, tpidrro_el0 64 mrs x4, contextidr_el1 65 mrs x5, mair_el1 66 mrs x6, cpacr_el1 67 mrs x7, ttbr1_el1 68 mrs x8, tcr_el1 69 mrs x9, vbar_el1 70 mrs x10, mdscr_el1 71 mrs x11, oslsr_el1 72 mrs x12, sctlr_el1 73 stp x2, x3, [x0] 74 stp x4, x5, [x0, #16] 75 stp x6, x7, [x0, #32] 76 stp x8, x9, [x0, #48] 77 stp x10, x11, [x0, #64] 78 str x12, [x0, #80] 79 ret 80ENDPROC(cpu_do_suspend) 81 82/** 83 * cpu_do_resume - restore CPU register context 84 * 85 * x0: Physical address of context pointer 86 * x1: ttbr0_el1 to be restored 87 * 88 * Returns: 89 * sctlr_el1 value in x0 90 */ 91ENTRY(cpu_do_resume) 92 /* 93 * Invalidate local tlb entries before turning on MMU 94 */ 95 tlbi vmalle1 96 ldp x2, x3, [x0] 97 ldp x4, x5, [x0, #16] 98 ldp x6, x7, [x0, #32] 99 ldp x8, x9, [x0, #48] 100 ldp x10, x11, [x0, #64] 101 ldr x12, [x0, #80] 102 msr tpidr_el0, x2 103 msr tpidrro_el0, x3 104 msr contextidr_el1, x4 105 msr mair_el1, x5 106 msr cpacr_el1, x6 107 msr ttbr0_el1, x1 108 msr ttbr1_el1, x7 109 tcr_set_idmap_t0sz x8, x7 110 msr tcr_el1, x8 111 msr vbar_el1, x9 112 msr mdscr_el1, x10 113 /* 114 * Restore oslsr_el1 by writing oslar_el1 115 */ 116 ubfx x11, x11, #1, #1 117 msr oslar_el1, x11 118 mov x0, x12 119 dsb nsh // Make sure local tlb invalidation completed 120 isb 121 ret 122ENDPROC(cpu_do_resume) 123#endif 124 125/* 126 * cpu_do_switch_mm(pgd_phys, tsk) 127 * 128 * Set the translation table base pointer to be pgd_phys. 129 * 130 * - pgd_phys - physical address of new TTB 131 */ 132ENTRY(cpu_do_switch_mm) 133 mmid w1, x1 // get mm->context.id 134 bfi x0, x1, #48, #16 // set the ASID 135 msr ttbr0_el1, x0 // set TTBR0 136 isb 137 ret 138ENDPROC(cpu_do_switch_mm) 139 140 .section ".text.init", #alloc, #execinstr 141 142/* 143 * __cpu_setup 144 * 145 * Initialise the processor for turning the MMU on. Return in x0 the 146 * value of the SCTLR_EL1 register. 147 */ 148ENTRY(__cpu_setup) 149 tlbi vmalle1is // invalidate I + D TLBs 150 dsb ish 151 152 mov x0, #3 << 20 153 msr cpacr_el1, x0 // Enable FP/ASIMD 154 mov x0, #1 << 12 // Reset mdscr_el1 and disable 155 msr mdscr_el1, x0 // access to the DCC from EL0 156 /* 157 * Memory region attributes for LPAE: 158 * 159 * n = AttrIndx[2:0] 160 * n MAIR 161 * DEVICE_nGnRnE 000 00000000 162 * DEVICE_nGnRE 001 00000100 163 * DEVICE_GRE 010 00001100 164 * NORMAL_NC 011 01000100 165 * NORMAL 100 11111111 166 */ 167 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 168 MAIR(0x04, MT_DEVICE_nGnRE) | \ 169 MAIR(0x0c, MT_DEVICE_GRE) | \ 170 MAIR(0x44, MT_NORMAL_NC) | \ 171 MAIR(0xff, MT_NORMAL) 172 msr mair_el1, x5 173 /* 174 * Prepare SCTLR 175 */ 176 adr x5, crval 177 ldp w5, w6, [x5] 178 mrs x0, sctlr_el1 179 bic x0, x0, x5 // clear bits 180 orr x0, x0, x6 // set bits 181 /* 182 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 183 * both user and kernel. 184 */ 185 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 186 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 187 tcr_set_idmap_t0sz x10, x9 188 189 /* 190 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in 191 * TCR_EL1. 192 */ 193 mrs x9, ID_AA64MMFR0_EL1 194 bfi x10, x9, #32, #3 195#ifdef CONFIG_ARM64_HW_AFDBM 196 /* 197 * Hardware update of the Access and Dirty bits. 198 */ 199 mrs x9, ID_AA64MMFR1_EL1 200 and x9, x9, #0xf 201 cbz x9, 2f 202 cmp x9, #2 203 b.lt 1f 204 orr x10, x10, #TCR_HD // hardware Dirty flag update 2051: orr x10, x10, #TCR_HA // hardware Access flag update 2062: 207#endif /* CONFIG_ARM64_HW_AFDBM */ 208 msr tcr_el1, x10 209 ret // return to head.S 210ENDPROC(__cpu_setup) 211 212 /* 213 * We set the desired value explicitly, including those of the 214 * reserved bits. The values of bits EE & E0E were set early in 215 * el2_setup, which are left untouched below. 216 * 217 * n n T 218 * U E WT T UD US IHBS 219 * CE0 XWHW CZ ME TEEA S 220 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 221 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 222 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 223 */ 224 .type crval, #object 225crval: 226 .word 0xfcffffff // clear 227 .word 0x34d5d91d // set 228