1/* 2 * Based on arch/arm/mm/proc.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include <linux/init.h> 22#include <linux/linkage.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/hwcap.h> 26#include <asm/pgtable-hwdef.h> 27#include <asm/pgtable.h> 28 29#include "proc-macros.S" 30 31#ifdef CONFIG_ARM64_64K_PAGES 32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K 33#else 34#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K 35#endif 36 37#ifdef CONFIG_SMP 38#define TCR_SMP_FLAGS TCR_SHARED 39#else 40#define TCR_SMP_FLAGS 0 41#endif 42 43/* PTWs cacheable, inner/outer WBWA */ 44#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA 45 46#define MAIR(attr, mt) ((attr) << ((mt) * 8)) 47 48/* 49 * cpu_do_idle() 50 * 51 * Idle the processor (wait for interrupt). 52 */ 53ENTRY(cpu_do_idle) 54 dsb sy // WFI may enter a low-power mode 55 wfi 56 ret 57ENDPROC(cpu_do_idle) 58 59#ifdef CONFIG_CPU_PM 60/** 61 * cpu_do_suspend - save CPU registers context 62 * 63 * x0: virtual address of context pointer 64 */ 65ENTRY(cpu_do_suspend) 66 mrs x2, tpidr_el0 67 mrs x3, tpidrro_el0 68 mrs x4, contextidr_el1 69 mrs x5, mair_el1 70 mrs x6, cpacr_el1 71 mrs x7, ttbr1_el1 72 mrs x8, tcr_el1 73 mrs x9, vbar_el1 74 mrs x10, mdscr_el1 75 mrs x11, oslsr_el1 76 mrs x12, sctlr_el1 77 stp x2, x3, [x0] 78 stp x4, x5, [x0, #16] 79 stp x6, x7, [x0, #32] 80 stp x8, x9, [x0, #48] 81 stp x10, x11, [x0, #64] 82 str x12, [x0, #80] 83 ret 84ENDPROC(cpu_do_suspend) 85 86/** 87 * cpu_do_resume - restore CPU register context 88 * 89 * x0: Physical address of context pointer 90 * x1: ttbr0_el1 to be restored 91 * 92 * Returns: 93 * sctlr_el1 value in x0 94 */ 95ENTRY(cpu_do_resume) 96 /* 97 * Invalidate local tlb entries before turning on MMU 98 */ 99 tlbi vmalle1 100 ldp x2, x3, [x0] 101 ldp x4, x5, [x0, #16] 102 ldp x6, x7, [x0, #32] 103 ldp x8, x9, [x0, #48] 104 ldp x10, x11, [x0, #64] 105 ldr x12, [x0, #80] 106 msr tpidr_el0, x2 107 msr tpidrro_el0, x3 108 msr contextidr_el1, x4 109 msr mair_el1, x5 110 msr cpacr_el1, x6 111 msr ttbr0_el1, x1 112 msr ttbr1_el1, x7 113 tcr_set_idmap_t0sz x8, x7 114 msr tcr_el1, x8 115 msr vbar_el1, x9 116 msr mdscr_el1, x10 117 /* 118 * Restore oslsr_el1 by writing oslar_el1 119 */ 120 ubfx x11, x11, #1, #1 121 msr oslar_el1, x11 122 mov x0, x12 123 dsb nsh // Make sure local tlb invalidation completed 124 isb 125 ret 126ENDPROC(cpu_do_resume) 127#endif 128 129/* 130 * cpu_do_switch_mm(pgd_phys, tsk) 131 * 132 * Set the translation table base pointer to be pgd_phys. 133 * 134 * - pgd_phys - physical address of new TTB 135 */ 136ENTRY(cpu_do_switch_mm) 137 mmid w1, x1 // get mm->context.id 138 bfi x0, x1, #48, #16 // set the ASID 139 msr ttbr0_el1, x0 // set TTBR0 140 isb 141 ret 142ENDPROC(cpu_do_switch_mm) 143 144 .section ".text.init", #alloc, #execinstr 145 146/* 147 * __cpu_setup 148 * 149 * Initialise the processor for turning the MMU on. Return in x0 the 150 * value of the SCTLR_EL1 register. 151 */ 152ENTRY(__cpu_setup) 153 ic iallu // I+BTB cache invalidate 154 tlbi vmalle1is // invalidate I + D TLBs 155 dsb ish 156 157 mov x0, #3 << 20 158 msr cpacr_el1, x0 // Enable FP/ASIMD 159 msr mdscr_el1, xzr // Reset mdscr_el1 160 /* 161 * Memory region attributes for LPAE: 162 * 163 * n = AttrIndx[2:0] 164 * n MAIR 165 * DEVICE_nGnRnE 000 00000000 166 * DEVICE_nGnRE 001 00000100 167 * DEVICE_GRE 010 00001100 168 * NORMAL_NC 011 01000100 169 * NORMAL 100 11111111 170 */ 171 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ 172 MAIR(0x04, MT_DEVICE_nGnRE) | \ 173 MAIR(0x0c, MT_DEVICE_GRE) | \ 174 MAIR(0x44, MT_NORMAL_NC) | \ 175 MAIR(0xff, MT_NORMAL) 176 msr mair_el1, x5 177 /* 178 * Prepare SCTLR 179 */ 180 adr x5, crval 181 ldp w5, w6, [x5] 182 mrs x0, sctlr_el1 183 bic x0, x0, x5 // clear bits 184 orr x0, x0, x6 // set bits 185 /* 186 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 187 * both user and kernel. 188 */ 189 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 190 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 191 tcr_set_idmap_t0sz x10, x9 192 193 /* 194 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in 195 * TCR_EL1. 196 */ 197 mrs x9, ID_AA64MMFR0_EL1 198 bfi x10, x9, #32, #3 199 msr tcr_el1, x10 200 ret // return to head.S 201ENDPROC(__cpu_setup) 202 203 /* 204 * We set the desired value explicitly, including those of the 205 * reserved bits. The values of bits EE & E0E were set early in 206 * el2_setup, which are left untouched below. 207 * 208 * n n T 209 * U E WT T UD US IHBS 210 * CE0 XWHW CZ ME TEEA S 211 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM 212 * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved 213 * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings 214 */ 215 .type crval, #object 216crval: 217 .word 0xfcffffff // clear 218 .word 0x34d5d91d // set 219