xref: /linux/arch/arm64/mm/proc.S (revision 302df34c4e64b9e83ee31cbf508b38b62b428bd6) 
1/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/cpufeature.h>
29#include <asm/alternative.h>
30
31#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
33#elif defined(CONFIG_ARM64_16K_PAGES)
34#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
35#else /* CONFIG_ARM64_4K_PAGES */
36#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
37#endif
38
39#ifdef CONFIG_RANDOMIZE_BASE
40#define TCR_KASLR_FLAGS	TCR_NFD1
41#else
42#define TCR_KASLR_FLAGS	0
43#endif
44
45#define TCR_SMP_FLAGS	TCR_SHARED
46
47/* PTWs cacheable, inner/outer WBWA */
48#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
49
50#define MAIR(attr, mt)	((attr) << ((mt) * 8))
51
52/*
53 *	cpu_do_idle()
54 *
55 *	Idle the processor (wait for interrupt).
56 */
57ENTRY(cpu_do_idle)
58	dsb	sy				// WFI may enter a low-power mode
59	wfi
60	ret
61ENDPROC(cpu_do_idle)
62
63#ifdef CONFIG_CPU_PM
64/**
65 * cpu_do_suspend - save CPU registers context
66 *
67 * x0: virtual address of context pointer
68 */
69ENTRY(cpu_do_suspend)
70	mrs	x2, tpidr_el0
71	mrs	x3, tpidrro_el0
72	mrs	x4, contextidr_el1
73	mrs	x5, cpacr_el1
74	mrs	x6, tcr_el1
75	mrs	x7, vbar_el1
76	mrs	x8, mdscr_el1
77	mrs	x9, oslsr_el1
78	mrs	x10, sctlr_el1
79alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
80	mrs	x11, tpidr_el1
81alternative_else
82	mrs	x11, tpidr_el2
83alternative_endif
84	mrs	x12, sp_el0
85	stp	x2, x3, [x0]
86	stp	x4, xzr, [x0, #16]
87	stp	x5, x6, [x0, #32]
88	stp	x7, x8, [x0, #48]
89	stp	x9, x10, [x0, #64]
90	stp	x11, x12, [x0, #80]
91	ret
92ENDPROC(cpu_do_suspend)
93
94/**
95 * cpu_do_resume - restore CPU register context
96 *
97 * x0: Address of context pointer
98 */
99	.pushsection ".idmap.text", "awx"
100ENTRY(cpu_do_resume)
101	ldp	x2, x3, [x0]
102	ldp	x4, x5, [x0, #16]
103	ldp	x6, x8, [x0, #32]
104	ldp	x9, x10, [x0, #48]
105	ldp	x11, x12, [x0, #64]
106	ldp	x13, x14, [x0, #80]
107	msr	tpidr_el0, x2
108	msr	tpidrro_el0, x3
109	msr	contextidr_el1, x4
110	msr	cpacr_el1, x6
111
112	/* Don't change t0sz here, mask those bits when restoring */
113	mrs	x5, tcr_el1
114	bfi	x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
115
116	msr	tcr_el1, x8
117	msr	vbar_el1, x9
118
119	/*
120	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
121	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
122	 * exception. Mask them until local_daif_restore() in cpu_suspend()
123	 * resets them.
124	 */
125	disable_daif
126	msr	mdscr_el1, x10
127
128	msr	sctlr_el1, x12
129alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
130	msr	tpidr_el1, x13
131alternative_else
132	msr	tpidr_el2, x13
133alternative_endif
134	msr	sp_el0, x14
135	/*
136	 * Restore oslsr_el1 by writing oslar_el1
137	 */
138	ubfx	x11, x11, #1, #1
139	msr	oslar_el1, x11
140	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
141
142alternative_if ARM64_HAS_RAS_EXTN
143	msr_s	SYS_DISR_EL1, xzr
144alternative_else_nop_endif
145
146	isb
147	ret
148ENDPROC(cpu_do_resume)
149	.popsection
150#endif
151
152/*
153 *	cpu_do_switch_mm(pgd_phys, tsk)
154 *
155 *	Set the translation table base pointer to be pgd_phys.
156 *
157 *	- pgd_phys - physical address of new TTB
158 */
159ENTRY(cpu_do_switch_mm)
160	mrs	x2, ttbr1_el1
161	mmid	x1, x1				// get mm->context.id
162	phys_to_ttbr x3, x0
163
164alternative_if ARM64_HAS_CNP
165	cbz     x1, 1f                          // skip CNP for reserved ASID
166	orr     x3, x3, #TTBR_CNP_BIT
1671:
168alternative_else_nop_endif
169#ifdef CONFIG_ARM64_SW_TTBR0_PAN
170	bfi	x3, x1, #48, #16		// set the ASID field in TTBR0
171#endif
172	bfi	x2, x1, #48, #16		// set the ASID
173	msr	ttbr1_el1, x2			// in TTBR1 (since TCR.A1 is set)
174	isb
175	msr	ttbr0_el1, x3			// now update TTBR0
176	isb
177	b	post_ttbr_update_workaround	// Back to C code...
178ENDPROC(cpu_do_switch_mm)
179
180	.pushsection ".idmap.text", "awx"
181
182.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
183	adrp	\tmp1, empty_zero_page
184	phys_to_ttbr \tmp2, \tmp1
185	offset_ttbr1 \tmp2
186	msr	ttbr1_el1, \tmp2
187	isb
188	tlbi	vmalle1
189	dsb	nsh
190	isb
191.endm
192
193/*
194 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
195 *
196 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
197 * called by anything else. It can only be executed from a TTBR0 mapping.
198 */
199ENTRY(idmap_cpu_replace_ttbr1)
200	save_and_disable_daif flags=x2
201
202	__idmap_cpu_set_reserved_ttbr1 x1, x3
203
204	offset_ttbr1 x0
205	msr	ttbr1_el1, x0
206	isb
207
208	restore_daif x2
209
210	ret
211ENDPROC(idmap_cpu_replace_ttbr1)
212	.popsection
213
214#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
215	.pushsection ".idmap.text", "awx"
216
217	.macro	__idmap_kpti_get_pgtable_ent, type
218	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
219	dmb	sy				// lines are written back before
220	ldr	\type, [cur_\()\type\()p]	// loading the entry
221	tbz	\type, #0, skip_\()\type	// Skip invalid and
222	tbnz	\type, #11, skip_\()\type	// non-global entries
223	.endm
224
225	.macro __idmap_kpti_put_pgtable_ent_ng, type
226	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
227	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
228	dmb	sy				// that it is visible to all
229	dc	civac, cur_\()\type\()p		// CPUs.
230	.endm
231
232/*
233 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
234 *
235 * Called exactly once from stop_machine context by each CPU found during boot.
236 */
237__idmap_kpti_flag:
238	.long	1
239ENTRY(idmap_kpti_install_ng_mappings)
240	cpu		.req	w0
241	num_cpus	.req	w1
242	swapper_pa	.req	x2
243	swapper_ttb	.req	x3
244	flag_ptr	.req	x4
245	cur_pgdp	.req	x5
246	end_pgdp	.req	x6
247	pgd		.req	x7
248	cur_pudp	.req	x8
249	end_pudp	.req	x9
250	pud		.req	x10
251	cur_pmdp	.req	x11
252	end_pmdp	.req	x12
253	pmd		.req	x13
254	cur_ptep	.req	x14
255	end_ptep	.req	x15
256	pte		.req	x16
257
258	mrs	swapper_ttb, ttbr1_el1
259	restore_ttbr1	swapper_ttb
260	adr	flag_ptr, __idmap_kpti_flag
261
262	cbnz	cpu, __idmap_kpti_secondary
263
264	/* We're the boot CPU. Wait for the others to catch up */
265	sevl
2661:	wfe
267	ldaxr	w18, [flag_ptr]
268	eor	w18, w18, num_cpus
269	cbnz	w18, 1b
270
271	/* We need to walk swapper, so turn off the MMU. */
272	pre_disable_mmu_workaround
273	mrs	x18, sctlr_el1
274	bic	x18, x18, #SCTLR_ELx_M
275	msr	sctlr_el1, x18
276	isb
277
278	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
279	/* PGD */
280	mov	cur_pgdp, swapper_pa
281	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
282do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
283	tbnz	pgd, #1, walk_puds
284next_pgd:
285	__idmap_kpti_put_pgtable_ent_ng	pgd
286skip_pgd:
287	add	cur_pgdp, cur_pgdp, #8
288	cmp	cur_pgdp, end_pgdp
289	b.ne	do_pgd
290
291	/* Publish the updated tables and nuke all the TLBs */
292	dsb	sy
293	tlbi	vmalle1is
294	dsb	ish
295	isb
296
297	/* We're done: fire up the MMU again */
298	mrs	x18, sctlr_el1
299	orr	x18, x18, #SCTLR_ELx_M
300	msr	sctlr_el1, x18
301	isb
302
303	/* Set the flag to zero to indicate that we're all done */
304	str	wzr, [flag_ptr]
305	ret
306
307	/* PUD */
308walk_puds:
309	.if CONFIG_PGTABLE_LEVELS > 3
310	pte_to_phys	cur_pudp, pgd
311	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
312do_pud:	__idmap_kpti_get_pgtable_ent	pud
313	tbnz	pud, #1, walk_pmds
314next_pud:
315	__idmap_kpti_put_pgtable_ent_ng	pud
316skip_pud:
317	add	cur_pudp, cur_pudp, 8
318	cmp	cur_pudp, end_pudp
319	b.ne	do_pud
320	b	next_pgd
321	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
322	mov	pud, pgd
323	b	walk_pmds
324next_pud:
325	b	next_pgd
326	.endif
327
328	/* PMD */
329walk_pmds:
330	.if CONFIG_PGTABLE_LEVELS > 2
331	pte_to_phys	cur_pmdp, pud
332	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
333do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
334	tbnz	pmd, #1, walk_ptes
335next_pmd:
336	__idmap_kpti_put_pgtable_ent_ng	pmd
337skip_pmd:
338	add	cur_pmdp, cur_pmdp, #8
339	cmp	cur_pmdp, end_pmdp
340	b.ne	do_pmd
341	b	next_pud
342	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
343	mov	pmd, pud
344	b	walk_ptes
345next_pmd:
346	b	next_pud
347	.endif
348
349	/* PTE */
350walk_ptes:
351	pte_to_phys	cur_ptep, pmd
352	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
353do_pte:	__idmap_kpti_get_pgtable_ent	pte
354	__idmap_kpti_put_pgtable_ent_ng	pte
355skip_pte:
356	add	cur_ptep, cur_ptep, #8
357	cmp	cur_ptep, end_ptep
358	b.ne	do_pte
359	b	next_pmd
360
361	/* Secondary CPUs end up here */
362__idmap_kpti_secondary:
363	/* Uninstall swapper before surgery begins */
364	__idmap_cpu_set_reserved_ttbr1 x18, x17
365
366	/* Increment the flag to let the boot CPU we're ready */
3671:	ldxr	w18, [flag_ptr]
368	add	w18, w18, #1
369	stxr	w17, w18, [flag_ptr]
370	cbnz	w17, 1b
371
372	/* Wait for the boot CPU to finish messing around with swapper */
373	sevl
3741:	wfe
375	ldxr	w18, [flag_ptr]
376	cbnz	w18, 1b
377
378	/* All done, act like nothing happened */
379	offset_ttbr1 swapper_ttb
380	msr	ttbr1_el1, swapper_ttb
381	isb
382	ret
383
384	.unreq	cpu
385	.unreq	num_cpus
386	.unreq	swapper_pa
387	.unreq	swapper_ttb
388	.unreq	flag_ptr
389	.unreq	cur_pgdp
390	.unreq	end_pgdp
391	.unreq	pgd
392	.unreq	cur_pudp
393	.unreq	end_pudp
394	.unreq	pud
395	.unreq	cur_pmdp
396	.unreq	end_pmdp
397	.unreq	pmd
398	.unreq	cur_ptep
399	.unreq	end_ptep
400	.unreq	pte
401ENDPROC(idmap_kpti_install_ng_mappings)
402	.popsection
403#endif
404
405/*
406 *	__cpu_setup
407 *
408 *	Initialise the processor for turning the MMU on.  Return in x0 the
409 *	value of the SCTLR_EL1 register.
410 */
411	.pushsection ".idmap.text", "awx"
412ENTRY(__cpu_setup)
413	tlbi	vmalle1				// Invalidate local TLB
414	dsb	nsh
415
416	mov	x0, #3 << 20
417	msr	cpacr_el1, x0			// Enable FP/ASIMD
418	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
419	msr	mdscr_el1, x0			// access to the DCC from EL0
420	isb					// Unmask debug exceptions now,
421	enable_dbg				// since this is per-cpu
422	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
423	/*
424	 * Memory region attributes for LPAE:
425	 *
426	 *   n = AttrIndx[2:0]
427	 *			n	MAIR
428	 *   DEVICE_nGnRnE	000	00000000
429	 *   DEVICE_nGnRE	001	00000100
430	 *   DEVICE_GRE		010	00001100
431	 *   NORMAL_NC		011	01000100
432	 *   NORMAL		100	11111111
433	 *   NORMAL_WT		101	10111011
434	 */
435	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
436		     MAIR(0x04, MT_DEVICE_nGnRE) | \
437		     MAIR(0x0c, MT_DEVICE_GRE) | \
438		     MAIR(0x44, MT_NORMAL_NC) | \
439		     MAIR(0xff, MT_NORMAL) | \
440		     MAIR(0xbb, MT_NORMAL_WT)
441	msr	mair_el1, x5
442	/*
443	 * Prepare SCTLR
444	 */
445	mov_q	x0, SCTLR_EL1_SET
446	/*
447	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
448	 * both user and kernel.
449	 */
450	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
451			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
452			TCR_TBI0 | TCR_A1
453
454#ifdef CONFIG_ARM64_USER_VA_BITS_52
455	ldr_l		x9, vabits_user
456	sub		x9, xzr, x9
457	add		x9, x9, #64
458#else
459	ldr_l		x9, idmap_t0sz
460#endif
461	tcr_set_t0sz	x10, x9
462
463	/*
464	 * Set the IPS bits in TCR_EL1.
465	 */
466	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
467#ifdef CONFIG_ARM64_HW_AFDBM
468	/*
469	 * Enable hardware update of the Access Flags bit.
470	 * Hardware dirty bit management is enabled later,
471	 * via capabilities.
472	 */
473	mrs	x9, ID_AA64MMFR1_EL1
474	and	x9, x9, #0xf
475	cbz	x9, 1f
476	orr	x10, x10, #TCR_HA		// hardware Access flag update
4771:
478#endif	/* CONFIG_ARM64_HW_AFDBM */
479	msr	tcr_el1, x10
480	ret					// return to head.S
481ENDPROC(__cpu_setup)
482