1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/bpf_defs.h> 13 #include <linux/extable.h> 14 #include <linux/kfence.h> 15 #include <linux/signal.h> 16 #include <linux/mm.h> 17 #include <linux/hardirq.h> 18 #include <linux/init.h> 19 #include <linux/kasan.h> 20 #include <linux/kprobes.h> 21 #include <linux/uaccess.h> 22 #include <linux/page-flags.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/highmem.h> 26 #include <linux/perf_event.h> 27 #include <linux/pkeys.h> 28 #include <linux/preempt.h> 29 #include <linux/hugetlb.h> 30 31 #include <asm/acpi.h> 32 #include <asm/bug.h> 33 #include <asm/cmpxchg.h> 34 #include <asm/cpufeature.h> 35 #include <asm/efi.h> 36 #include <asm/exception.h> 37 #include <asm/daifflags.h> 38 #include <asm/debug-monitors.h> 39 #include <asm/esr.h> 40 #include <asm/kprobes.h> 41 #include <asm/mte.h> 42 #include <asm/processor.h> 43 #include <asm/sysreg.h> 44 #include <asm/system_misc.h> 45 #include <asm/tlbflush.h> 46 #include <asm/traps.h> 47 #include <asm/virt.h> 48 49 struct fault_info { 50 int (*fn)(unsigned long far, unsigned long esr, 51 struct pt_regs *regs); 52 int sig; 53 int code; 54 const char *name; 55 }; 56 57 static const struct fault_info fault_info[]; 58 59 static inline const struct fault_info *esr_to_fault_info(unsigned long esr) 60 { 61 return fault_info + (esr & ESR_ELx_FSC); 62 } 63 64 static void data_abort_decode(unsigned long esr) 65 { 66 unsigned long iss2 = ESR_ELx_ISS2(esr); 67 68 pr_alert("Data abort info:\n"); 69 70 if (esr & ESR_ELx_ISV) { 71 pr_alert(" Access size = %u byte(s)\n", 72 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 73 pr_alert(" SSE = %lu, SRT = %lu\n", 74 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 75 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 76 pr_alert(" SF = %lu, AR = %lu\n", 77 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 78 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 79 pr_alert(" Xs = %llu\n", 80 (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT); 81 } else { 82 pr_alert(" ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n", 83 esr & ESR_ELx_ISS_MASK, iss2); 84 } 85 86 pr_alert(" CM = %lu, WnR = %lu, TnD = %lu, TagAccess = %lu\n", 87 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 88 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT, 89 (iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT, 90 (iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT); 91 92 pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu\n", 93 (iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT, 94 (iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT, 95 (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT); 96 } 97 98 static void mem_abort_decode(unsigned long esr) 99 { 100 pr_alert("Mem abort info:\n"); 101 102 pr_alert(" ESR = 0x%016lx\n", esr); 103 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", 104 ESR_ELx_EC(esr), esr_get_class_string(esr), 105 (esr & ESR_ELx_IL) ? 32 : 16); 106 pr_alert(" SET = %lu, FnV = %lu\n", 107 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 108 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 109 pr_alert(" EA = %lu, S1PTW = %lu\n", 110 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 111 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 112 pr_alert(" FSC = 0x%02lx: %s\n", (esr & ESR_ELx_FSC), 113 esr_to_fault_info(esr)->name); 114 115 if (esr_is_data_abort(esr)) 116 data_abort_decode(esr); 117 } 118 119 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm) 120 { 121 /* Either init_pg_dir or swapper_pg_dir */ 122 if (mm == &init_mm) 123 return __pa_symbol(mm->pgd); 124 125 return (unsigned long)virt_to_phys(mm->pgd); 126 } 127 128 /* 129 * Dump out the page tables associated with 'addr' in the currently active mm. 130 */ 131 static void show_pte(unsigned long addr) 132 { 133 struct mm_struct *mm; 134 pgd_t *pgdp; 135 pgd_t pgd; 136 137 if (is_ttbr0_addr(addr)) { 138 /* TTBR0 */ 139 mm = current->active_mm; 140 if (mm == &init_mm) { 141 pr_alert("[%016lx] user address but active_mm is swapper\n", 142 addr); 143 return; 144 } 145 } else if (is_ttbr1_addr(addr)) { 146 /* TTBR1 */ 147 mm = &init_mm; 148 } else { 149 pr_alert("[%016lx] address between user and kernel address ranges\n", 150 addr); 151 return; 152 } 153 154 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", 155 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 156 vabits_actual, mm_to_pgd_phys(mm)); 157 pgdp = pgd_offset(mm, addr); 158 pgd = READ_ONCE(*pgdp); 159 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 160 161 do { 162 p4d_t *p4dp, p4d; 163 pud_t *pudp, pud; 164 pmd_t *pmdp, pmd; 165 pte_t *ptep, pte; 166 167 if (pgd_none(pgd) || pgd_bad(pgd)) 168 break; 169 170 p4dp = p4d_offset(pgdp, addr); 171 p4d = READ_ONCE(*p4dp); 172 pr_cont(", p4d=%016llx", p4d_val(p4d)); 173 if (p4d_none(p4d) || p4d_bad(p4d)) 174 break; 175 176 pudp = pud_offset(p4dp, addr); 177 pud = READ_ONCE(*pudp); 178 pr_cont(", pud=%016llx", pud_val(pud)); 179 if (pud_none(pud) || pud_bad(pud)) 180 break; 181 182 pmdp = pmd_offset(pudp, addr); 183 pmd = READ_ONCE(*pmdp); 184 pr_cont(", pmd=%016llx", pmd_val(pmd)); 185 if (pmd_none(pmd) || pmd_bad(pmd)) 186 break; 187 188 ptep = pte_offset_map(pmdp, addr); 189 if (!ptep) 190 break; 191 192 pte = __ptep_get(ptep); 193 pr_cont(", pte=%016llx", pte_val(pte)); 194 pte_unmap(ptep); 195 } while(0); 196 197 pr_cont("\n"); 198 } 199 200 /* 201 * This function sets the access flags (dirty, accessed), as well as write 202 * permission, and only to a more permissive setting. 203 * 204 * It needs to cope with hardware update of the accessed/dirty state by other 205 * agents in the system and can safely skip the __sync_icache_dcache() call as, 206 * like __set_ptes(), the PTE is never changed from no-exec to exec here. 207 * 208 * Returns whether or not the PTE actually changed. 209 */ 210 int __ptep_set_access_flags_anysz(struct vm_area_struct *vma, 211 unsigned long address, pte_t *ptep, 212 pte_t entry, int dirty, unsigned long pgsize) 213 { 214 pteval_t old_pteval, pteval; 215 pte_t pte = __ptep_get(ptep); 216 int level; 217 218 if (pte_same(pte, entry)) 219 return 0; 220 221 /* only preserve the access flags and write permission */ 222 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 223 224 /* 225 * Setting the flags must be done atomically to avoid racing with the 226 * hardware update of the access/dirty state. The PTE_RDONLY bit must 227 * be set to the most permissive (lowest value) of *ptep and entry 228 * (calculated as: a & b == ~(~a | ~b)). 229 */ 230 pte_val(entry) ^= PTE_RDONLY; 231 pteval = pte_val(pte); 232 do { 233 old_pteval = pteval; 234 pteval ^= PTE_RDONLY; 235 pteval |= pte_val(entry); 236 pteval ^= PTE_RDONLY; 237 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 238 } while (pteval != old_pteval); 239 240 /* 241 * Invalidate the local stale read-only entry. Remote stale entries 242 * may still cause page faults and be invalidated via 243 * flush_tlb_fix_spurious_fault(). 244 */ 245 if (dirty) { 246 switch (pgsize) { 247 case PAGE_SIZE: 248 level = 3; 249 break; 250 case PMD_SIZE: 251 level = 2; 252 break; 253 #ifndef __PAGETABLE_PMD_FOLDED 254 case PUD_SIZE: 255 level = 1; 256 break; 257 #endif 258 default: 259 level = TLBI_TTL_UNKNOWN; 260 WARN_ON(1); 261 } 262 263 __flush_tlb_range(vma, address, address + pgsize, pgsize, level, 264 TLBF_NOWALKCACHE | TLBF_NOBROADCAST); 265 } 266 return 1; 267 } 268 269 static bool is_el1_instruction_abort(unsigned long esr) 270 { 271 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 272 } 273 274 static bool is_el1_data_abort(unsigned long esr) 275 { 276 return ESR_ELx_EC(esr) == ESR_ELx_EC_DABT_CUR; 277 } 278 279 static inline bool is_el1_permission_fault(unsigned long addr, unsigned long esr, 280 struct pt_regs *regs) 281 { 282 if (!is_el1_data_abort(esr) && !is_el1_instruction_abort(esr)) 283 return false; 284 285 if (esr_fsc_is_permission_fault(esr)) 286 return true; 287 288 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 289 return esr_fsc_is_translation_fault(esr) && 290 (regs->pstate & PSR_PAN_BIT); 291 292 return false; 293 } 294 295 static bool is_pkvm_stage2_abort(unsigned int esr) 296 { 297 /* 298 * S1PTW should only ever be set in ESR_EL1 if the pkvm hypervisor 299 * injected a stage-2 abort -- see host_inject_mem_abort(). 300 */ 301 return is_pkvm_initialized() && (esr & ESR_ELx_S1PTW); 302 } 303 304 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, 305 unsigned long esr, 306 struct pt_regs *regs) 307 { 308 unsigned long flags; 309 u64 par, dfsc; 310 311 if (!is_el1_data_abort(esr) || !esr_fsc_is_translation_fault(esr)) 312 return false; 313 314 local_irq_save(flags); 315 asm volatile("at s1e1r, %0" :: "r" (addr)); 316 isb(); 317 par = read_sysreg_par(); 318 local_irq_restore(flags); 319 320 /* 321 * If we now have a valid translation, treat the translation fault as 322 * spurious. 323 */ 324 if (!(par & SYS_PAR_EL1_F)) { 325 if (is_pkvm_stage2_abort(esr)) { 326 par &= SYS_PAR_EL1_PA; 327 return pkvm_force_reclaim_guest_page(par); 328 } 329 330 return true; 331 } 332 333 /* 334 * If we got a different type of fault from the AT instruction, 335 * treat the translation fault as spurious. 336 */ 337 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par); 338 return !esr_fsc_is_translation_fault(dfsc); 339 } 340 341 static void die_kernel_fault(const char *msg, unsigned long addr, 342 unsigned long esr, struct pt_regs *regs) 343 { 344 bust_spinlocks(1); 345 346 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 347 addr); 348 349 kasan_non_canonical_hook(addr); 350 351 mem_abort_decode(esr); 352 353 show_pte(addr); 354 die("Oops", regs, esr); 355 bust_spinlocks(0); 356 make_task_dead(SIGKILL); 357 } 358 359 #ifdef CONFIG_KASAN_HW_TAGS 360 static void report_tag_fault(unsigned long addr, unsigned long esr, 361 struct pt_regs *regs) 362 { 363 /* 364 * SAS bits aren't set for all faults reported in EL1, so we can't 365 * find out access size. 366 */ 367 bool is_write = !!(esr & ESR_ELx_WNR); 368 kasan_report((void *)addr, 0, is_write, regs->pc); 369 } 370 #else 371 /* Tag faults aren't enabled without CONFIG_KASAN_HW_TAGS. */ 372 static inline void report_tag_fault(unsigned long addr, unsigned long esr, 373 struct pt_regs *regs) { } 374 #endif 375 376 static void do_tag_recovery(unsigned long addr, unsigned long esr, 377 struct pt_regs *regs) 378 { 379 380 report_tag_fault(addr, esr, regs); 381 382 /* 383 * Disable MTE Tag Checking on the local CPU for the current EL. 384 * It will be done lazily on the other CPUs when they will hit a 385 * tag fault. 386 */ 387 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, 388 SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF, NONE)); 389 isb(); 390 } 391 392 static bool is_el1_mte_sync_tag_check_fault(unsigned long esr) 393 { 394 unsigned long fsc = esr & ESR_ELx_FSC; 395 396 if (!is_el1_data_abort(esr)) 397 return false; 398 399 if (fsc == ESR_ELx_FSC_MTE) 400 return true; 401 402 return false; 403 } 404 405 static void __do_kernel_fault(unsigned long addr, unsigned long esr, 406 struct pt_regs *regs) 407 { 408 const char *msg; 409 410 /* 411 * Are we prepared to handle this kernel fault? 412 * We are almost certainly not prepared to handle instruction faults. 413 */ 414 if (!is_el1_instruction_abort(esr) && fixup_exception(regs, esr)) 415 return; 416 417 if (is_spurious_el1_translation_fault(addr, esr, regs)) { 418 WARN_RATELIMIT(!is_pkvm_stage2_abort(esr), 419 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr); 420 return; 421 } 422 423 if (is_el1_mte_sync_tag_check_fault(esr)) { 424 do_tag_recovery(addr, esr, regs); 425 426 return; 427 } 428 429 if (is_el1_permission_fault(addr, esr, regs)) { 430 if (esr & ESR_ELx_WNR) 431 msg = "write to read-only memory"; 432 else if (is_el1_instruction_abort(esr)) 433 msg = "execute from non-executable memory"; 434 else 435 msg = "read from unreadable memory"; 436 } else if (addr < PAGE_SIZE) { 437 msg = "NULL pointer dereference"; 438 } else if (is_pkvm_stage2_abort(esr)) { 439 msg = "access to hypervisor-protected memory"; 440 } else { 441 if (esr_fsc_is_translation_fault(esr)) { 442 if (kfence_handle_page_fault(addr, esr & ESR_ELx_WNR, regs)) 443 return; 444 if (bpf_arena_handle_page_fault(addr, esr & ESR_ELx_WNR, regs->pc)) 445 return; 446 } 447 448 msg = "paging request"; 449 } 450 451 if (efi_runtime_fixup_exception(regs, msg)) 452 return; 453 454 die_kernel_fault(msg, addr, esr, regs); 455 } 456 457 static void set_thread_esr(unsigned long address, unsigned long esr) 458 { 459 current->thread.fault_address = address; 460 461 /* 462 * If the faulting address is in the kernel, we must sanitize the ESR. 463 * From userspace's point of view, kernel-only mappings don't exist 464 * at all, so we report them as level 0 translation faults. 465 * (This is not quite the way that "no mapping there at all" behaves: 466 * an alignment fault not caused by the memory type would take 467 * precedence over translation fault for a real access to empty 468 * space. Unfortunately we can't easily distinguish "alignment fault 469 * not caused by memory type" from "alignment fault caused by memory 470 * type", so we ignore this wrinkle and just return the translation 471 * fault.) 472 */ 473 if (!is_ttbr0_addr(current->thread.fault_address)) { 474 switch (ESR_ELx_EC(esr)) { 475 case ESR_ELx_EC_DABT_LOW: 476 /* 477 * These bits provide only information about the 478 * faulting instruction, which userspace knows already. 479 * We explicitly clear bits which are architecturally 480 * RES0 in case they are given meanings in future. 481 * We always report the ESR as if the fault was taken 482 * to EL1 and so ISV and the bits in ISS[23:14] are 483 * clear. (In fact it always will be a fault to EL1.) 484 */ 485 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 486 ESR_ELx_CM | ESR_ELx_WNR; 487 esr |= ESR_ELx_FSC_FAULT; 488 break; 489 case ESR_ELx_EC_IABT_LOW: 490 /* 491 * Claim a level 0 translation fault. 492 * All other bits are architecturally RES0 for faults 493 * reported with that DFSC value, so we clear them. 494 */ 495 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 496 esr |= ESR_ELx_FSC_FAULT; 497 break; 498 default: 499 /* 500 * This should never happen (entry.S only brings us 501 * into this code for insn and data aborts from a lower 502 * exception level). Fail safe by not providing an ESR 503 * context record at all. 504 */ 505 WARN(1, "ESR 0x%lx is not DABT or IABT from EL0\n", esr); 506 esr = 0; 507 break; 508 } 509 } 510 511 current->thread.fault_code = esr; 512 } 513 514 static void do_bad_area(unsigned long far, unsigned long esr, 515 struct pt_regs *regs) 516 { 517 unsigned long addr = untagged_addr(far); 518 519 /* 520 * If we are in kernel mode at this point, we have no context to 521 * handle this fault with. 522 */ 523 if (user_mode(regs)) { 524 const struct fault_info *inf = esr_to_fault_info(esr); 525 526 set_thread_esr(addr, esr); 527 arm64_force_sig_fault(inf->sig, inf->code, far, inf->name); 528 } else { 529 __do_kernel_fault(addr, esr, regs); 530 } 531 } 532 533 static bool fault_from_pkey(struct vm_area_struct *vma, unsigned int mm_flags) 534 { 535 if (!system_supports_poe()) 536 return false; 537 538 /* 539 * We do not check whether an Overlay fault has occurred because we 540 * cannot make a decision based solely on its value: 541 * 542 * - If Overlay is set, a fault did occur due to POE, but it may be 543 * spurious in those cases where we update POR_EL0 without ISB (e.g. 544 * on context-switch). We would then need to manually check POR_EL0 545 * against vma_pkey(vma), which is exactly what 546 * arch_vma_access_permitted() does. 547 * 548 * - If Overlay is not set, we may still need to report a pkey fault. 549 * This is the case if an access was made within a mapping but with no 550 * page mapped, and POR_EL0 forbids the access (according to 551 * vma_pkey()). Such access will result in a SIGSEGV regardless 552 * because core code checks arch_vma_access_permitted(), but in order 553 * to report the correct error code - SEGV_PKUERR - we must handle 554 * that case here. 555 */ 556 return !arch_vma_access_permitted(vma, 557 mm_flags & FAULT_FLAG_WRITE, 558 mm_flags & FAULT_FLAG_INSTRUCTION, 559 false); 560 } 561 562 static bool is_gcs_fault(unsigned long esr) 563 { 564 if (!esr_is_data_abort(esr)) 565 return false; 566 567 return ESR_ELx_ISS2(esr) & ESR_ELx_GCS; 568 } 569 570 static bool is_el0_instruction_abort(unsigned long esr) 571 { 572 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 573 } 574 575 /* 576 * Note: not valid for EL1 DC IVAC, but we never use that such that it 577 * should fault. EL0 cannot issue DC IVAC (undef). 578 */ 579 static bool is_write_abort(unsigned long esr) 580 { 581 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 582 } 583 584 static bool is_invalid_gcs_access(struct vm_area_struct *vma, u64 esr) 585 { 586 if (!system_supports_gcs()) 587 return false; 588 589 if (unlikely(is_gcs_fault(esr))) { 590 /* GCS accesses must be performed on a GCS page */ 591 if (!(vma->vm_flags & VM_SHADOW_STACK)) 592 return true; 593 } else if (unlikely(vma->vm_flags & VM_SHADOW_STACK)) { 594 /* Only GCS operations can write to a GCS page */ 595 return esr_is_data_abort(esr) && is_write_abort(esr); 596 } 597 598 return false; 599 } 600 601 static int __kprobes do_page_fault(unsigned long far, unsigned long esr, 602 struct pt_regs *regs) 603 { 604 const struct fault_info *inf; 605 struct mm_struct *mm = current->mm; 606 vm_fault_t fault; 607 vm_flags_t vm_flags; 608 unsigned int mm_flags = FAULT_FLAG_DEFAULT; 609 unsigned long addr = untagged_addr(far); 610 struct vm_area_struct *vma; 611 int si_code; 612 int pkey = -1; 613 614 if (kprobe_page_fault(regs, esr)) 615 return 0; 616 617 /* 618 * If we're in an interrupt or have no user context, we must not take 619 * the fault. 620 */ 621 if (faulthandler_disabled() || !mm) 622 goto no_context; 623 624 if (user_mode(regs)) 625 mm_flags |= FAULT_FLAG_USER; 626 627 /* 628 * vm_flags tells us what bits we must have in vma->vm_flags 629 * for the fault to be benign, __do_page_fault() would check 630 * vma->vm_flags & vm_flags and returns an error if the 631 * intersection is empty 632 */ 633 if (is_el0_instruction_abort(esr)) { 634 /* It was exec fault */ 635 vm_flags = VM_EXEC; 636 mm_flags |= FAULT_FLAG_INSTRUCTION; 637 } else if (is_gcs_fault(esr)) { 638 /* 639 * The GCS permission on a page implies both read and 640 * write so always handle any GCS fault as a write fault, 641 * we need to trigger CoW even for GCS reads. 642 */ 643 vm_flags = VM_WRITE; 644 mm_flags |= FAULT_FLAG_WRITE; 645 } else if (is_write_abort(esr)) { 646 /* It was write fault */ 647 vm_flags = VM_WRITE; 648 mm_flags |= FAULT_FLAG_WRITE; 649 } else { 650 /* It was read fault */ 651 vm_flags = VM_READ; 652 /* Write implies read */ 653 vm_flags |= VM_WRITE; 654 /* If EPAN is absent then exec implies read */ 655 if (!alternative_has_cap_unlikely(ARM64_HAS_EPAN)) 656 vm_flags |= VM_EXEC; 657 } 658 659 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 660 if (is_el1_instruction_abort(esr)) 661 die_kernel_fault("execution of user memory", 662 addr, esr, regs); 663 664 if (!insn_may_access_user(regs->pc, esr)) 665 die_kernel_fault("access to user memory outside uaccess routines", 666 addr, esr, regs); 667 } 668 669 if (is_pkvm_stage2_abort(esr)) { 670 if (!user_mode(regs)) 671 goto no_context; 672 arm64_force_sig_fault(SIGSEGV, SEGV_ACCERR, far, "stage-2 fault"); 673 return 0; 674 } 675 676 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 677 678 if (!(mm_flags & FAULT_FLAG_USER)) 679 goto lock_mmap; 680 681 vma = lock_vma_under_rcu(mm, addr); 682 if (!vma) 683 goto lock_mmap; 684 685 if (is_invalid_gcs_access(vma, esr)) { 686 vma_end_read(vma); 687 fault = 0; 688 si_code = SEGV_ACCERR; 689 goto bad_area; 690 } 691 692 if (!(vma->vm_flags & vm_flags)) { 693 vma_end_read(vma); 694 fault = 0; 695 si_code = SEGV_ACCERR; 696 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 697 goto bad_area; 698 } 699 700 if (fault_from_pkey(vma, mm_flags)) { 701 pkey = vma_pkey(vma); 702 vma_end_read(vma); 703 fault = 0; 704 si_code = SEGV_PKUERR; 705 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 706 goto bad_area; 707 } 708 709 fault = handle_mm_fault(vma, addr, mm_flags | FAULT_FLAG_VMA_LOCK, regs); 710 if (!(fault & (VM_FAULT_RETRY | VM_FAULT_COMPLETED))) 711 vma_end_read(vma); 712 713 if (!(fault & VM_FAULT_RETRY)) { 714 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 715 goto done; 716 } 717 count_vm_vma_lock_event(VMA_LOCK_RETRY); 718 if (fault & VM_FAULT_MAJOR) 719 mm_flags |= FAULT_FLAG_TRIED; 720 721 /* Quick path to respond to signals */ 722 if (fault_signal_pending(fault, regs)) { 723 if (!user_mode(regs)) 724 goto no_context; 725 return 0; 726 } 727 lock_mmap: 728 729 retry: 730 vma = lock_mm_and_find_vma(mm, addr, regs); 731 if (unlikely(!vma)) { 732 fault = 0; 733 si_code = SEGV_MAPERR; 734 goto bad_area; 735 } 736 737 if (!(vma->vm_flags & vm_flags)) { 738 mmap_read_unlock(mm); 739 fault = 0; 740 si_code = SEGV_ACCERR; 741 goto bad_area; 742 } 743 744 if (fault_from_pkey(vma, mm_flags)) { 745 pkey = vma_pkey(vma); 746 mmap_read_unlock(mm); 747 fault = 0; 748 si_code = SEGV_PKUERR; 749 goto bad_area; 750 } 751 752 fault = handle_mm_fault(vma, addr, mm_flags, regs); 753 754 /* Quick path to respond to signals */ 755 if (fault_signal_pending(fault, regs)) { 756 if (!user_mode(regs)) 757 goto no_context; 758 return 0; 759 } 760 761 /* The fault is fully completed (including releasing mmap lock) */ 762 if (fault & VM_FAULT_COMPLETED) 763 return 0; 764 765 if (fault & VM_FAULT_RETRY) { 766 mm_flags |= FAULT_FLAG_TRIED; 767 goto retry; 768 } 769 mmap_read_unlock(mm); 770 771 done: 772 /* Handle the "normal" (no error) case first. */ 773 if (likely(!(fault & VM_FAULT_ERROR))) 774 return 0; 775 776 si_code = SEGV_MAPERR; 777 bad_area: 778 /* 779 * If we are in kernel mode at this point, we have no context to 780 * handle this fault with. 781 */ 782 if (!user_mode(regs)) 783 goto no_context; 784 785 if (fault & VM_FAULT_OOM) { 786 /* 787 * We ran out of memory, call the OOM killer, and return to 788 * userspace (which will retry the fault, or kill us if we got 789 * oom-killed). 790 */ 791 pagefault_out_of_memory(); 792 return 0; 793 } 794 795 inf = esr_to_fault_info(esr); 796 set_thread_esr(addr, esr); 797 if (fault & VM_FAULT_SIGBUS) { 798 /* 799 * We had some memory, but were unable to successfully fix up 800 * this page fault. 801 */ 802 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, far, inf->name); 803 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 804 unsigned int lsb; 805 806 lsb = PAGE_SHIFT; 807 if (fault & VM_FAULT_HWPOISON_LARGE) 808 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 809 810 arm64_force_sig_mceerr(BUS_MCEERR_AR, far, lsb, inf->name); 811 } else { 812 /* 813 * The pkey value that we return to userspace can be different 814 * from the pkey that caused the fault. 815 * 816 * 1. T1 : mprotect_key(foo, PAGE_SIZE, pkey=4); 817 * 2. T1 : set POR_EL0 to deny access to pkey=4, touches, page 818 * 3. T1 : faults... 819 * 4. T2: mprotect_key(foo, PAGE_SIZE, pkey=5); 820 * 5. T1 : enters fault handler, takes mmap_lock, etc... 821 * 6. T1 : reaches here, sees vma_pkey(vma)=5, when we really 822 * faulted on a pte with its pkey=4. 823 */ 824 /* Something tried to access memory that out of memory map */ 825 if (si_code == SEGV_PKUERR) 826 arm64_force_sig_fault_pkey(far, inf->name, pkey); 827 else 828 arm64_force_sig_fault(SIGSEGV, si_code, far, inf->name); 829 } 830 831 return 0; 832 833 no_context: 834 __do_kernel_fault(addr, esr, regs); 835 return 0; 836 } 837 838 static int __kprobes do_translation_fault(unsigned long far, 839 unsigned long esr, 840 struct pt_regs *regs) 841 { 842 unsigned long addr = untagged_addr(far); 843 844 if (is_ttbr0_addr(addr)) 845 return do_page_fault(far, esr, regs); 846 847 do_bad_area(far, esr, regs); 848 return 0; 849 } 850 851 static int do_alignment_fault(unsigned long far, unsigned long esr, 852 struct pt_regs *regs) 853 { 854 if (IS_ENABLED(CONFIG_COMPAT_ALIGNMENT_FIXUPS) && 855 compat_user_mode(regs)) 856 return do_compat_alignment_fixup(far, regs); 857 do_bad_area(far, esr, regs); 858 return 0; 859 } 860 861 static int do_bad(unsigned long far, unsigned long esr, struct pt_regs *regs) 862 { 863 return 1; /* "fault" */ 864 } 865 866 static int do_sea(unsigned long far, unsigned long esr, struct pt_regs *regs) 867 { 868 const struct fault_info *inf; 869 unsigned long siaddr; 870 871 inf = esr_to_fault_info(esr); 872 873 if (user_mode(regs) && apei_claim_sea(regs) == 0) { 874 /* 875 * APEI claimed this as a firmware-first notification. 876 * Some processing deferred to task_work before ret_to_user(). 877 */ 878 return 0; 879 } 880 881 if (esr & ESR_ELx_FnV) { 882 siaddr = 0; 883 } else { 884 /* 885 * The architecture specifies that the tag bits of FAR_EL1 are 886 * UNKNOWN for synchronous external aborts. Mask them out now 887 * so that userspace doesn't see them. 888 */ 889 siaddr = untagged_addr(far); 890 } 891 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 892 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 893 894 return 0; 895 } 896 897 static int do_tag_check_fault(unsigned long far, unsigned long esr, 898 struct pt_regs *regs) 899 { 900 /* 901 * The architecture specifies that bits 63:60 of FAR_EL1 are UNKNOWN 902 * for tag check faults. Set them to corresponding bits in the untagged 903 * address if ARM64_MTE_FAR isn't supported. 904 * Otherwise, bits 63:60 of FAR_EL1 are not UNKNOWN. 905 */ 906 if (!cpus_have_cap(ARM64_MTE_FAR)) 907 far = (__untagged_addr(far) & ~MTE_TAG_MASK) | (far & MTE_TAG_MASK); 908 909 do_bad_area(far, esr, regs); 910 return 0; 911 } 912 913 static const struct fault_info fault_info[] = { 914 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 915 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 916 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 917 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 918 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 919 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 920 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 921 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 922 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 0 access flag fault" }, 923 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 924 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 925 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 926 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 0 permission fault" }, 927 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 928 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 929 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 930 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 931 { do_tag_check_fault, SIGSEGV, SEGV_MTESERR, "synchronous tag check fault" }, 932 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 933 { do_sea, SIGKILL, SI_KERNEL, "level -1 (translation table walk)" }, 934 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 935 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 936 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 937 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 938 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 939 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 940 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 941 { do_sea, SIGKILL, SI_KERNEL, "level -1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 942 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 943 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 944 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 945 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 946 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 947 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 948 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 949 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 950 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 951 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 952 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 953 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 954 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 955 { do_bad, SIGKILL, SI_KERNEL, "level -1 address size fault" }, 956 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 957 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level -1 translation fault" }, 958 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 959 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 960 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 961 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 962 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 963 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 964 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 965 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 966 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 967 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 968 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 969 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 970 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 971 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 972 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 973 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 974 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 975 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 976 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 977 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 978 }; 979 980 void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *regs) 981 { 982 const struct fault_info *inf = esr_to_fault_info(esr); 983 unsigned long addr = untagged_addr(far); 984 985 if (!inf->fn(far, esr, regs)) 986 return; 987 988 if (!user_mode(regs)) 989 die_kernel_fault(inf->name, addr, esr, regs); 990 991 /* 992 * At this point we have an unrecognized fault type whose tag bits may 993 * have been defined as UNKNOWN. Therefore we only expose the untagged 994 * address to the signal handler. 995 */ 996 arm64_notify_die(inf->name, regs, inf->sig, inf->code, addr, esr); 997 } 998 NOKPROBE_SYMBOL(do_mem_abort); 999 1000 void do_sp_pc_abort(unsigned long addr, unsigned long esr, struct pt_regs *regs) 1001 { 1002 arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN, 1003 addr, esr); 1004 } 1005 NOKPROBE_SYMBOL(do_sp_pc_abort); 1006 1007 /* 1008 * Used during anonymous page fault handling. 1009 */ 1010 struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma, 1011 unsigned long vaddr) 1012 { 1013 gfp_t flags = GFP_HIGHUSER_MOVABLE | __GFP_ZERO; 1014 1015 /* 1016 * If the page is mapped with PROT_MTE, initialise the tags at the 1017 * point of allocation and page zeroing as this is usually faster than 1018 * separate DC ZVA and STGM. 1019 */ 1020 if (vma->vm_flags & VM_MTE) 1021 flags |= __GFP_ZEROTAGS; 1022 1023 return vma_alloc_folio(flags, 0, vma, vaddr); 1024 } 1025 1026 bool tag_clear_highpages(struct page *page, int numpages, bool clear_pages) 1027 { 1028 /* 1029 * Check if MTE is supported and fall back to clear_highpage(). 1030 * get_huge_zero_folio() unconditionally passes __GFP_ZEROTAGS and 1031 * post_alloc_hook() will invoke tag_clear_highpages(). 1032 */ 1033 if (!system_supports_mte()) 1034 return clear_pages; 1035 1036 /* Newly allocated pages, shouldn't have been tagged yet */ 1037 for (int i = 0; i < numpages; i++, page++) { 1038 WARN_ON_ONCE(!try_page_mte_tagging(page)); 1039 if (clear_pages) 1040 mte_zero_clear_page_tags(page_address(page)); 1041 else 1042 mte_clear_page_tags(page_address(page)); 1043 set_page_mte_tagged(page); 1044 } 1045 return false; 1046 } 1047