1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/extable.h> 13 #include <linux/kfence.h> 14 #include <linux/signal.h> 15 #include <linux/mm.h> 16 #include <linux/hardirq.h> 17 #include <linux/init.h> 18 #include <linux/kasan.h> 19 #include <linux/kprobes.h> 20 #include <linux/uaccess.h> 21 #include <linux/page-flags.h> 22 #include <linux/sched/signal.h> 23 #include <linux/sched/debug.h> 24 #include <linux/highmem.h> 25 #include <linux/perf_event.h> 26 #include <linux/pkeys.h> 27 #include <linux/preempt.h> 28 #include <linux/hugetlb.h> 29 30 #include <asm/acpi.h> 31 #include <asm/bug.h> 32 #include <asm/cmpxchg.h> 33 #include <asm/cpufeature.h> 34 #include <asm/efi.h> 35 #include <asm/exception.h> 36 #include <asm/daifflags.h> 37 #include <asm/debug-monitors.h> 38 #include <asm/esr.h> 39 #include <asm/kprobes.h> 40 #include <asm/mte.h> 41 #include <asm/processor.h> 42 #include <asm/sysreg.h> 43 #include <asm/system_misc.h> 44 #include <asm/tlbflush.h> 45 #include <asm/traps.h> 46 47 struct fault_info { 48 int (*fn)(unsigned long far, unsigned long esr, 49 struct pt_regs *regs); 50 int sig; 51 int code; 52 const char *name; 53 }; 54 55 static const struct fault_info fault_info[]; 56 57 static inline const struct fault_info *esr_to_fault_info(unsigned long esr) 58 { 59 return fault_info + (esr & ESR_ELx_FSC); 60 } 61 62 static void data_abort_decode(unsigned long esr) 63 { 64 unsigned long iss2 = ESR_ELx_ISS2(esr); 65 66 pr_alert("Data abort info:\n"); 67 68 if (esr & ESR_ELx_ISV) { 69 pr_alert(" Access size = %u byte(s)\n", 70 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 71 pr_alert(" SSE = %lu, SRT = %lu\n", 72 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 73 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 74 pr_alert(" SF = %lu, AR = %lu\n", 75 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 76 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 77 } else { 78 pr_alert(" ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n", 79 esr & ESR_ELx_ISS_MASK, iss2); 80 } 81 82 pr_alert(" CM = %lu, WnR = %lu, TnD = %lu, TagAccess = %lu\n", 83 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 84 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT, 85 (iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT, 86 (iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT); 87 88 pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n", 89 (iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT, 90 (iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT, 91 (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT, 92 (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT); 93 } 94 95 static void mem_abort_decode(unsigned long esr) 96 { 97 pr_alert("Mem abort info:\n"); 98 99 pr_alert(" ESR = 0x%016lx\n", esr); 100 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", 101 ESR_ELx_EC(esr), esr_get_class_string(esr), 102 (esr & ESR_ELx_IL) ? 32 : 16); 103 pr_alert(" SET = %lu, FnV = %lu\n", 104 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 105 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 106 pr_alert(" EA = %lu, S1PTW = %lu\n", 107 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 108 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 109 pr_alert(" FSC = 0x%02lx: %s\n", (esr & ESR_ELx_FSC), 110 esr_to_fault_info(esr)->name); 111 112 if (esr_is_data_abort(esr)) 113 data_abort_decode(esr); 114 } 115 116 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm) 117 { 118 /* Either init_pg_dir or swapper_pg_dir */ 119 if (mm == &init_mm) 120 return __pa_symbol(mm->pgd); 121 122 return (unsigned long)virt_to_phys(mm->pgd); 123 } 124 125 /* 126 * Dump out the page tables associated with 'addr' in the currently active mm. 127 */ 128 static void show_pte(unsigned long addr) 129 { 130 struct mm_struct *mm; 131 pgd_t *pgdp; 132 pgd_t pgd; 133 134 if (is_ttbr0_addr(addr)) { 135 /* TTBR0 */ 136 mm = current->active_mm; 137 if (mm == &init_mm) { 138 pr_alert("[%016lx] user address but active_mm is swapper\n", 139 addr); 140 return; 141 } 142 } else if (is_ttbr1_addr(addr)) { 143 /* TTBR1 */ 144 mm = &init_mm; 145 } else { 146 pr_alert("[%016lx] address between user and kernel address ranges\n", 147 addr); 148 return; 149 } 150 151 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", 152 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 153 vabits_actual, mm_to_pgd_phys(mm)); 154 pgdp = pgd_offset(mm, addr); 155 pgd = READ_ONCE(*pgdp); 156 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 157 158 do { 159 p4d_t *p4dp, p4d; 160 pud_t *pudp, pud; 161 pmd_t *pmdp, pmd; 162 pte_t *ptep, pte; 163 164 if (pgd_none(pgd) || pgd_bad(pgd)) 165 break; 166 167 p4dp = p4d_offset(pgdp, addr); 168 p4d = READ_ONCE(*p4dp); 169 pr_cont(", p4d=%016llx", p4d_val(p4d)); 170 if (p4d_none(p4d) || p4d_bad(p4d)) 171 break; 172 173 pudp = pud_offset(p4dp, addr); 174 pud = READ_ONCE(*pudp); 175 pr_cont(", pud=%016llx", pud_val(pud)); 176 if (pud_none(pud) || pud_bad(pud)) 177 break; 178 179 pmdp = pmd_offset(pudp, addr); 180 pmd = READ_ONCE(*pmdp); 181 pr_cont(", pmd=%016llx", pmd_val(pmd)); 182 if (pmd_none(pmd) || pmd_bad(pmd)) 183 break; 184 185 ptep = pte_offset_map(pmdp, addr); 186 if (!ptep) 187 break; 188 189 pte = __ptep_get(ptep); 190 pr_cont(", pte=%016llx", pte_val(pte)); 191 pte_unmap(ptep); 192 } while(0); 193 194 pr_cont("\n"); 195 } 196 197 /* 198 * This function sets the access flags (dirty, accessed), as well as write 199 * permission, and only to a more permissive setting. 200 * 201 * It needs to cope with hardware update of the accessed/dirty state by other 202 * agents in the system and can safely skip the __sync_icache_dcache() call as, 203 * like __set_ptes(), the PTE is never changed from no-exec to exec here. 204 * 205 * Returns whether or not the PTE actually changed. 206 */ 207 int __ptep_set_access_flags_anysz(struct vm_area_struct *vma, 208 unsigned long address, pte_t *ptep, 209 pte_t entry, int dirty, unsigned long pgsize) 210 { 211 pteval_t old_pteval, pteval; 212 pte_t pte = __ptep_get(ptep); 213 int level; 214 215 if (pte_same(pte, entry)) 216 return 0; 217 218 /* only preserve the access flags and write permission */ 219 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 220 221 /* 222 * Setting the flags must be done atomically to avoid racing with the 223 * hardware update of the access/dirty state. The PTE_RDONLY bit must 224 * be set to the most permissive (lowest value) of *ptep and entry 225 * (calculated as: a & b == ~(~a | ~b)). 226 */ 227 pte_val(entry) ^= PTE_RDONLY; 228 pteval = pte_val(pte); 229 do { 230 old_pteval = pteval; 231 pteval ^= PTE_RDONLY; 232 pteval |= pte_val(entry); 233 pteval ^= PTE_RDONLY; 234 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 235 } while (pteval != old_pteval); 236 237 /* 238 * Invalidate the local stale read-only entry. Remote stale entries 239 * may still cause page faults and be invalidated via 240 * flush_tlb_fix_spurious_fault(). 241 */ 242 if (dirty) { 243 switch (pgsize) { 244 case PAGE_SIZE: 245 level = 3; 246 break; 247 case PMD_SIZE: 248 level = 2; 249 break; 250 #ifndef __PAGETABLE_PMD_FOLDED 251 case PUD_SIZE: 252 level = 1; 253 break; 254 #endif 255 default: 256 level = TLBI_TTL_UNKNOWN; 257 WARN_ON(1); 258 } 259 260 __flush_tlb_range(vma, address, address + pgsize, pgsize, level, 261 TLBF_NOWALKCACHE | TLBF_NOBROADCAST); 262 } 263 return 1; 264 } 265 266 static bool is_el1_instruction_abort(unsigned long esr) 267 { 268 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 269 } 270 271 static bool is_el1_data_abort(unsigned long esr) 272 { 273 return ESR_ELx_EC(esr) == ESR_ELx_EC_DABT_CUR; 274 } 275 276 static inline bool is_el1_permission_fault(unsigned long addr, unsigned long esr, 277 struct pt_regs *regs) 278 { 279 if (!is_el1_data_abort(esr) && !is_el1_instruction_abort(esr)) 280 return false; 281 282 if (esr_fsc_is_permission_fault(esr)) 283 return true; 284 285 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 286 return esr_fsc_is_translation_fault(esr) && 287 (regs->pstate & PSR_PAN_BIT); 288 289 return false; 290 } 291 292 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, 293 unsigned long esr, 294 struct pt_regs *regs) 295 { 296 unsigned long flags; 297 u64 par, dfsc; 298 299 if (!is_el1_data_abort(esr) || !esr_fsc_is_translation_fault(esr)) 300 return false; 301 302 local_irq_save(flags); 303 asm volatile("at s1e1r, %0" :: "r" (addr)); 304 isb(); 305 par = read_sysreg_par(); 306 local_irq_restore(flags); 307 308 /* 309 * If we now have a valid translation, treat the translation fault as 310 * spurious. 311 */ 312 if (!(par & SYS_PAR_EL1_F)) 313 return true; 314 315 /* 316 * If we got a different type of fault from the AT instruction, 317 * treat the translation fault as spurious. 318 */ 319 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par); 320 return !esr_fsc_is_translation_fault(dfsc); 321 } 322 323 static void die_kernel_fault(const char *msg, unsigned long addr, 324 unsigned long esr, struct pt_regs *regs) 325 { 326 bust_spinlocks(1); 327 328 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 329 addr); 330 331 kasan_non_canonical_hook(addr); 332 333 mem_abort_decode(esr); 334 335 show_pte(addr); 336 die("Oops", regs, esr); 337 bust_spinlocks(0); 338 make_task_dead(SIGKILL); 339 } 340 341 #ifdef CONFIG_KASAN_HW_TAGS 342 static void report_tag_fault(unsigned long addr, unsigned long esr, 343 struct pt_regs *regs) 344 { 345 /* 346 * SAS bits aren't set for all faults reported in EL1, so we can't 347 * find out access size. 348 */ 349 bool is_write = !!(esr & ESR_ELx_WNR); 350 kasan_report((void *)addr, 0, is_write, regs->pc); 351 } 352 #else 353 /* Tag faults aren't enabled without CONFIG_KASAN_HW_TAGS. */ 354 static inline void report_tag_fault(unsigned long addr, unsigned long esr, 355 struct pt_regs *regs) { } 356 #endif 357 358 static void do_tag_recovery(unsigned long addr, unsigned long esr, 359 struct pt_regs *regs) 360 { 361 362 report_tag_fault(addr, esr, regs); 363 364 /* 365 * Disable MTE Tag Checking on the local CPU for the current EL. 366 * It will be done lazily on the other CPUs when they will hit a 367 * tag fault. 368 */ 369 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, 370 SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF, NONE)); 371 isb(); 372 } 373 374 static bool is_el1_mte_sync_tag_check_fault(unsigned long esr) 375 { 376 unsigned long fsc = esr & ESR_ELx_FSC; 377 378 if (!is_el1_data_abort(esr)) 379 return false; 380 381 if (fsc == ESR_ELx_FSC_MTE) 382 return true; 383 384 return false; 385 } 386 387 static void __do_kernel_fault(unsigned long addr, unsigned long esr, 388 struct pt_regs *regs) 389 { 390 const char *msg; 391 392 /* 393 * Are we prepared to handle this kernel fault? 394 * We are almost certainly not prepared to handle instruction faults. 395 */ 396 if (!is_el1_instruction_abort(esr) && fixup_exception(regs, esr)) 397 return; 398 399 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs), 400 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr)) 401 return; 402 403 if (is_el1_mte_sync_tag_check_fault(esr)) { 404 do_tag_recovery(addr, esr, regs); 405 406 return; 407 } 408 409 if (is_el1_permission_fault(addr, esr, regs)) { 410 if (esr & ESR_ELx_WNR) 411 msg = "write to read-only memory"; 412 else if (is_el1_instruction_abort(esr)) 413 msg = "execute from non-executable memory"; 414 else 415 msg = "read from unreadable memory"; 416 } else if (addr < PAGE_SIZE) { 417 msg = "NULL pointer dereference"; 418 } else { 419 if (esr_fsc_is_translation_fault(esr) && 420 kfence_handle_page_fault(addr, esr & ESR_ELx_WNR, regs)) 421 return; 422 423 msg = "paging request"; 424 } 425 426 if (efi_runtime_fixup_exception(regs, msg)) 427 return; 428 429 die_kernel_fault(msg, addr, esr, regs); 430 } 431 432 static void set_thread_esr(unsigned long address, unsigned long esr) 433 { 434 current->thread.fault_address = address; 435 436 /* 437 * If the faulting address is in the kernel, we must sanitize the ESR. 438 * From userspace's point of view, kernel-only mappings don't exist 439 * at all, so we report them as level 0 translation faults. 440 * (This is not quite the way that "no mapping there at all" behaves: 441 * an alignment fault not caused by the memory type would take 442 * precedence over translation fault for a real access to empty 443 * space. Unfortunately we can't easily distinguish "alignment fault 444 * not caused by memory type" from "alignment fault caused by memory 445 * type", so we ignore this wrinkle and just return the translation 446 * fault.) 447 */ 448 if (!is_ttbr0_addr(current->thread.fault_address)) { 449 switch (ESR_ELx_EC(esr)) { 450 case ESR_ELx_EC_DABT_LOW: 451 /* 452 * These bits provide only information about the 453 * faulting instruction, which userspace knows already. 454 * We explicitly clear bits which are architecturally 455 * RES0 in case they are given meanings in future. 456 * We always report the ESR as if the fault was taken 457 * to EL1 and so ISV and the bits in ISS[23:14] are 458 * clear. (In fact it always will be a fault to EL1.) 459 */ 460 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 461 ESR_ELx_CM | ESR_ELx_WNR; 462 esr |= ESR_ELx_FSC_FAULT; 463 break; 464 case ESR_ELx_EC_IABT_LOW: 465 /* 466 * Claim a level 0 translation fault. 467 * All other bits are architecturally RES0 for faults 468 * reported with that DFSC value, so we clear them. 469 */ 470 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 471 esr |= ESR_ELx_FSC_FAULT; 472 break; 473 default: 474 /* 475 * This should never happen (entry.S only brings us 476 * into this code for insn and data aborts from a lower 477 * exception level). Fail safe by not providing an ESR 478 * context record at all. 479 */ 480 WARN(1, "ESR 0x%lx is not DABT or IABT from EL0\n", esr); 481 esr = 0; 482 break; 483 } 484 } 485 486 current->thread.fault_code = esr; 487 } 488 489 static void do_bad_area(unsigned long far, unsigned long esr, 490 struct pt_regs *regs) 491 { 492 unsigned long addr = untagged_addr(far); 493 494 /* 495 * If we are in kernel mode at this point, we have no context to 496 * handle this fault with. 497 */ 498 if (user_mode(regs)) { 499 const struct fault_info *inf = esr_to_fault_info(esr); 500 501 set_thread_esr(addr, esr); 502 arm64_force_sig_fault(inf->sig, inf->code, far, inf->name); 503 } else { 504 __do_kernel_fault(addr, esr, regs); 505 } 506 } 507 508 static bool fault_from_pkey(struct vm_area_struct *vma, unsigned int mm_flags) 509 { 510 if (!system_supports_poe()) 511 return false; 512 513 /* 514 * We do not check whether an Overlay fault has occurred because we 515 * cannot make a decision based solely on its value: 516 * 517 * - If Overlay is set, a fault did occur due to POE, but it may be 518 * spurious in those cases where we update POR_EL0 without ISB (e.g. 519 * on context-switch). We would then need to manually check POR_EL0 520 * against vma_pkey(vma), which is exactly what 521 * arch_vma_access_permitted() does. 522 * 523 * - If Overlay is not set, we may still need to report a pkey fault. 524 * This is the case if an access was made within a mapping but with no 525 * page mapped, and POR_EL0 forbids the access (according to 526 * vma_pkey()). Such access will result in a SIGSEGV regardless 527 * because core code checks arch_vma_access_permitted(), but in order 528 * to report the correct error code - SEGV_PKUERR - we must handle 529 * that case here. 530 */ 531 return !arch_vma_access_permitted(vma, 532 mm_flags & FAULT_FLAG_WRITE, 533 mm_flags & FAULT_FLAG_INSTRUCTION, 534 false); 535 } 536 537 static bool is_gcs_fault(unsigned long esr) 538 { 539 if (!esr_is_data_abort(esr)) 540 return false; 541 542 return ESR_ELx_ISS2(esr) & ESR_ELx_GCS; 543 } 544 545 static bool is_el0_instruction_abort(unsigned long esr) 546 { 547 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 548 } 549 550 /* 551 * Note: not valid for EL1 DC IVAC, but we never use that such that it 552 * should fault. EL0 cannot issue DC IVAC (undef). 553 */ 554 static bool is_write_abort(unsigned long esr) 555 { 556 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 557 } 558 559 static bool is_invalid_gcs_access(struct vm_area_struct *vma, u64 esr) 560 { 561 if (!system_supports_gcs()) 562 return false; 563 564 if (unlikely(is_gcs_fault(esr))) { 565 /* GCS accesses must be performed on a GCS page */ 566 if (!(vma->vm_flags & VM_SHADOW_STACK)) 567 return true; 568 } else if (unlikely(vma->vm_flags & VM_SHADOW_STACK)) { 569 /* Only GCS operations can write to a GCS page */ 570 return esr_is_data_abort(esr) && is_write_abort(esr); 571 } 572 573 return false; 574 } 575 576 static int __kprobes do_page_fault(unsigned long far, unsigned long esr, 577 struct pt_regs *regs) 578 { 579 const struct fault_info *inf; 580 struct mm_struct *mm = current->mm; 581 vm_fault_t fault; 582 vm_flags_t vm_flags; 583 unsigned int mm_flags = FAULT_FLAG_DEFAULT; 584 unsigned long addr = untagged_addr(far); 585 struct vm_area_struct *vma; 586 int si_code; 587 int pkey = -1; 588 589 if (kprobe_page_fault(regs, esr)) 590 return 0; 591 592 /* 593 * If we're in an interrupt or have no user context, we must not take 594 * the fault. 595 */ 596 if (faulthandler_disabled() || !mm) 597 goto no_context; 598 599 if (user_mode(regs)) 600 mm_flags |= FAULT_FLAG_USER; 601 602 /* 603 * vm_flags tells us what bits we must have in vma->vm_flags 604 * for the fault to be benign, __do_page_fault() would check 605 * vma->vm_flags & vm_flags and returns an error if the 606 * intersection is empty 607 */ 608 if (is_el0_instruction_abort(esr)) { 609 /* It was exec fault */ 610 vm_flags = VM_EXEC; 611 mm_flags |= FAULT_FLAG_INSTRUCTION; 612 } else if (is_gcs_fault(esr)) { 613 /* 614 * The GCS permission on a page implies both read and 615 * write so always handle any GCS fault as a write fault, 616 * we need to trigger CoW even for GCS reads. 617 */ 618 vm_flags = VM_WRITE; 619 mm_flags |= FAULT_FLAG_WRITE; 620 } else if (is_write_abort(esr)) { 621 /* It was write fault */ 622 vm_flags = VM_WRITE; 623 mm_flags |= FAULT_FLAG_WRITE; 624 } else { 625 /* It was read fault */ 626 vm_flags = VM_READ; 627 /* Write implies read */ 628 vm_flags |= VM_WRITE; 629 /* If EPAN is absent then exec implies read */ 630 if (!alternative_has_cap_unlikely(ARM64_HAS_EPAN)) 631 vm_flags |= VM_EXEC; 632 } 633 634 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 635 if (is_el1_instruction_abort(esr)) 636 die_kernel_fault("execution of user memory", 637 addr, esr, regs); 638 639 if (!insn_may_access_user(regs->pc, esr)) 640 die_kernel_fault("access to user memory outside uaccess routines", 641 addr, esr, regs); 642 } 643 644 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 645 646 if (!(mm_flags & FAULT_FLAG_USER)) 647 goto lock_mmap; 648 649 vma = lock_vma_under_rcu(mm, addr); 650 if (!vma) 651 goto lock_mmap; 652 653 if (is_invalid_gcs_access(vma, esr)) { 654 vma_end_read(vma); 655 fault = 0; 656 si_code = SEGV_ACCERR; 657 goto bad_area; 658 } 659 660 if (!(vma->vm_flags & vm_flags)) { 661 vma_end_read(vma); 662 fault = 0; 663 si_code = SEGV_ACCERR; 664 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 665 goto bad_area; 666 } 667 668 if (fault_from_pkey(vma, mm_flags)) { 669 pkey = vma_pkey(vma); 670 vma_end_read(vma); 671 fault = 0; 672 si_code = SEGV_PKUERR; 673 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 674 goto bad_area; 675 } 676 677 fault = handle_mm_fault(vma, addr, mm_flags | FAULT_FLAG_VMA_LOCK, regs); 678 if (!(fault & (VM_FAULT_RETRY | VM_FAULT_COMPLETED))) 679 vma_end_read(vma); 680 681 if (!(fault & VM_FAULT_RETRY)) { 682 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 683 goto done; 684 } 685 count_vm_vma_lock_event(VMA_LOCK_RETRY); 686 if (fault & VM_FAULT_MAJOR) 687 mm_flags |= FAULT_FLAG_TRIED; 688 689 /* Quick path to respond to signals */ 690 if (fault_signal_pending(fault, regs)) { 691 if (!user_mode(regs)) 692 goto no_context; 693 return 0; 694 } 695 lock_mmap: 696 697 retry: 698 vma = lock_mm_and_find_vma(mm, addr, regs); 699 if (unlikely(!vma)) { 700 fault = 0; 701 si_code = SEGV_MAPERR; 702 goto bad_area; 703 } 704 705 if (!(vma->vm_flags & vm_flags)) { 706 mmap_read_unlock(mm); 707 fault = 0; 708 si_code = SEGV_ACCERR; 709 goto bad_area; 710 } 711 712 if (fault_from_pkey(vma, mm_flags)) { 713 pkey = vma_pkey(vma); 714 mmap_read_unlock(mm); 715 fault = 0; 716 si_code = SEGV_PKUERR; 717 goto bad_area; 718 } 719 720 fault = handle_mm_fault(vma, addr, mm_flags, regs); 721 722 /* Quick path to respond to signals */ 723 if (fault_signal_pending(fault, regs)) { 724 if (!user_mode(regs)) 725 goto no_context; 726 return 0; 727 } 728 729 /* The fault is fully completed (including releasing mmap lock) */ 730 if (fault & VM_FAULT_COMPLETED) 731 return 0; 732 733 if (fault & VM_FAULT_RETRY) { 734 mm_flags |= FAULT_FLAG_TRIED; 735 goto retry; 736 } 737 mmap_read_unlock(mm); 738 739 done: 740 /* Handle the "normal" (no error) case first. */ 741 if (likely(!(fault & VM_FAULT_ERROR))) 742 return 0; 743 744 si_code = SEGV_MAPERR; 745 bad_area: 746 /* 747 * If we are in kernel mode at this point, we have no context to 748 * handle this fault with. 749 */ 750 if (!user_mode(regs)) 751 goto no_context; 752 753 if (fault & VM_FAULT_OOM) { 754 /* 755 * We ran out of memory, call the OOM killer, and return to 756 * userspace (which will retry the fault, or kill us if we got 757 * oom-killed). 758 */ 759 pagefault_out_of_memory(); 760 return 0; 761 } 762 763 inf = esr_to_fault_info(esr); 764 set_thread_esr(addr, esr); 765 if (fault & VM_FAULT_SIGBUS) { 766 /* 767 * We had some memory, but were unable to successfully fix up 768 * this page fault. 769 */ 770 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, far, inf->name); 771 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 772 unsigned int lsb; 773 774 lsb = PAGE_SHIFT; 775 if (fault & VM_FAULT_HWPOISON_LARGE) 776 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 777 778 arm64_force_sig_mceerr(BUS_MCEERR_AR, far, lsb, inf->name); 779 } else { 780 /* 781 * The pkey value that we return to userspace can be different 782 * from the pkey that caused the fault. 783 * 784 * 1. T1 : mprotect_key(foo, PAGE_SIZE, pkey=4); 785 * 2. T1 : set POR_EL0 to deny access to pkey=4, touches, page 786 * 3. T1 : faults... 787 * 4. T2: mprotect_key(foo, PAGE_SIZE, pkey=5); 788 * 5. T1 : enters fault handler, takes mmap_lock, etc... 789 * 6. T1 : reaches here, sees vma_pkey(vma)=5, when we really 790 * faulted on a pte with its pkey=4. 791 */ 792 /* Something tried to access memory that out of memory map */ 793 if (si_code == SEGV_PKUERR) 794 arm64_force_sig_fault_pkey(far, inf->name, pkey); 795 else 796 arm64_force_sig_fault(SIGSEGV, si_code, far, inf->name); 797 } 798 799 return 0; 800 801 no_context: 802 __do_kernel_fault(addr, esr, regs); 803 return 0; 804 } 805 806 static int __kprobes do_translation_fault(unsigned long far, 807 unsigned long esr, 808 struct pt_regs *regs) 809 { 810 unsigned long addr = untagged_addr(far); 811 812 if (is_ttbr0_addr(addr)) 813 return do_page_fault(far, esr, regs); 814 815 do_bad_area(far, esr, regs); 816 return 0; 817 } 818 819 static int do_alignment_fault(unsigned long far, unsigned long esr, 820 struct pt_regs *regs) 821 { 822 if (IS_ENABLED(CONFIG_COMPAT_ALIGNMENT_FIXUPS) && 823 compat_user_mode(regs)) 824 return do_compat_alignment_fixup(far, regs); 825 do_bad_area(far, esr, regs); 826 return 0; 827 } 828 829 static int do_bad(unsigned long far, unsigned long esr, struct pt_regs *regs) 830 { 831 return 1; /* "fault" */ 832 } 833 834 static int do_sea(unsigned long far, unsigned long esr, struct pt_regs *regs) 835 { 836 const struct fault_info *inf; 837 unsigned long siaddr; 838 839 inf = esr_to_fault_info(esr); 840 841 if (user_mode(regs) && apei_claim_sea(regs) == 0) { 842 /* 843 * APEI claimed this as a firmware-first notification. 844 * Some processing deferred to task_work before ret_to_user(). 845 */ 846 return 0; 847 } 848 849 if (esr & ESR_ELx_FnV) { 850 siaddr = 0; 851 } else { 852 /* 853 * The architecture specifies that the tag bits of FAR_EL1 are 854 * UNKNOWN for synchronous external aborts. Mask them out now 855 * so that userspace doesn't see them. 856 */ 857 siaddr = untagged_addr(far); 858 } 859 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 860 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 861 862 return 0; 863 } 864 865 static int do_tag_check_fault(unsigned long far, unsigned long esr, 866 struct pt_regs *regs) 867 { 868 /* 869 * The architecture specifies that bits 63:60 of FAR_EL1 are UNKNOWN 870 * for tag check faults. Set them to corresponding bits in the untagged 871 * address if ARM64_MTE_FAR isn't supported. 872 * Otherwise, bits 63:60 of FAR_EL1 are not UNKNOWN. 873 */ 874 if (!cpus_have_cap(ARM64_MTE_FAR)) 875 far = (__untagged_addr(far) & ~MTE_TAG_MASK) | (far & MTE_TAG_MASK); 876 877 do_bad_area(far, esr, regs); 878 return 0; 879 } 880 881 static const struct fault_info fault_info[] = { 882 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 883 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 884 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 885 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 886 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 887 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 888 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 889 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 890 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 0 access flag fault" }, 891 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 892 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 893 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 894 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 0 permission fault" }, 895 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 896 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 897 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 898 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 899 { do_tag_check_fault, SIGSEGV, SEGV_MTESERR, "synchronous tag check fault" }, 900 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 901 { do_sea, SIGKILL, SI_KERNEL, "level -1 (translation table walk)" }, 902 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 903 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 904 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 905 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 906 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 907 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 908 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 909 { do_sea, SIGKILL, SI_KERNEL, "level -1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 910 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 911 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 912 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 913 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 914 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 915 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 916 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 917 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 918 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 919 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 920 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 921 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 922 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 923 { do_bad, SIGKILL, SI_KERNEL, "level -1 address size fault" }, 924 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 925 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level -1 translation fault" }, 926 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 927 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 928 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 929 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 930 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 931 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 932 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 933 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 934 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 935 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 936 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 937 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 938 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 939 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 940 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 941 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 942 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 943 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 944 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 945 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 946 }; 947 948 void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *regs) 949 { 950 const struct fault_info *inf = esr_to_fault_info(esr); 951 unsigned long addr = untagged_addr(far); 952 953 if (!inf->fn(far, esr, regs)) 954 return; 955 956 if (!user_mode(regs)) 957 die_kernel_fault(inf->name, addr, esr, regs); 958 959 /* 960 * At this point we have an unrecognized fault type whose tag bits may 961 * have been defined as UNKNOWN. Therefore we only expose the untagged 962 * address to the signal handler. 963 */ 964 arm64_notify_die(inf->name, regs, inf->sig, inf->code, addr, esr); 965 } 966 NOKPROBE_SYMBOL(do_mem_abort); 967 968 void do_sp_pc_abort(unsigned long addr, unsigned long esr, struct pt_regs *regs) 969 { 970 arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN, 971 addr, esr); 972 } 973 NOKPROBE_SYMBOL(do_sp_pc_abort); 974 975 /* 976 * Used during anonymous page fault handling. 977 */ 978 struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma, 979 unsigned long vaddr) 980 { 981 gfp_t flags = GFP_HIGHUSER_MOVABLE | __GFP_ZERO; 982 983 /* 984 * If the page is mapped with PROT_MTE, initialise the tags at the 985 * point of allocation and page zeroing as this is usually faster than 986 * separate DC ZVA and STGM. 987 */ 988 if (vma->vm_flags & VM_MTE) 989 flags |= __GFP_ZEROTAGS; 990 991 return vma_alloc_folio(flags, 0, vma, vaddr); 992 } 993 994 bool tag_clear_highpages(struct page *page, int numpages) 995 { 996 /* 997 * Check if MTE is supported and fall back to clear_highpage(). 998 * get_huge_zero_folio() unconditionally passes __GFP_ZEROTAGS and 999 * post_alloc_hook() will invoke tag_clear_highpages(). 1000 */ 1001 if (!system_supports_mte()) 1002 return false; 1003 1004 /* Newly allocated pages, shouldn't have been tagged yet */ 1005 for (int i = 0; i < numpages; i++, page++) { 1006 WARN_ON_ONCE(!try_page_mte_tagging(page)); 1007 mte_zero_clear_page_tags(page_address(page)); 1008 set_page_mte_tagged(page); 1009 } 1010 return true; 1011 } 1012