1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/bpf_defs.h> 13 #include <linux/extable.h> 14 #include <linux/kfence.h> 15 #include <linux/signal.h> 16 #include <linux/mm.h> 17 #include <linux/hardirq.h> 18 #include <linux/init.h> 19 #include <linux/kasan.h> 20 #include <linux/kprobes.h> 21 #include <linux/uaccess.h> 22 #include <linux/page-flags.h> 23 #include <linux/sched/signal.h> 24 #include <linux/sched/debug.h> 25 #include <linux/highmem.h> 26 #include <linux/perf_event.h> 27 #include <linux/pkeys.h> 28 #include <linux/preempt.h> 29 #include <linux/hugetlb.h> 30 31 #include <asm/acpi.h> 32 #include <asm/bug.h> 33 #include <asm/cmpxchg.h> 34 #include <asm/cpufeature.h> 35 #include <asm/efi.h> 36 #include <asm/exception.h> 37 #include <asm/daifflags.h> 38 #include <asm/debug-monitors.h> 39 #include <asm/esr.h> 40 #include <asm/kprobes.h> 41 #include <asm/mte.h> 42 #include <asm/processor.h> 43 #include <asm/sysreg.h> 44 #include <asm/system_misc.h> 45 #include <asm/tlbflush.h> 46 #include <asm/traps.h> 47 #include <asm/virt.h> 48 49 struct fault_info { 50 int (*fn)(unsigned long far, unsigned long esr, 51 struct pt_regs *regs); 52 int sig; 53 int code; 54 const char *name; 55 }; 56 57 static const struct fault_info fault_info[]; 58 59 static inline const struct fault_info *esr_to_fault_info(unsigned long esr) 60 { 61 return fault_info + (esr & ESR_ELx_FSC); 62 } 63 64 static void data_abort_decode(unsigned long esr) 65 { 66 unsigned long iss2 = ESR_ELx_ISS2(esr); 67 68 pr_alert("Data abort info:\n"); 69 70 if (esr & ESR_ELx_ISV) { 71 pr_alert(" Access size = %u byte(s)\n", 72 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 73 pr_alert(" SSE = %lu, SRT = %lu\n", 74 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 75 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 76 pr_alert(" SF = %lu, AR = %lu\n", 77 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 78 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 79 } else { 80 pr_alert(" ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n", 81 esr & ESR_ELx_ISS_MASK, iss2); 82 } 83 84 pr_alert(" CM = %lu, WnR = %lu, TnD = %lu, TagAccess = %lu\n", 85 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 86 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT, 87 (iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT, 88 (iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT); 89 90 pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n", 91 (iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT, 92 (iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT, 93 (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT, 94 (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT); 95 } 96 97 static void mem_abort_decode(unsigned long esr) 98 { 99 pr_alert("Mem abort info:\n"); 100 101 pr_alert(" ESR = 0x%016lx\n", esr); 102 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", 103 ESR_ELx_EC(esr), esr_get_class_string(esr), 104 (esr & ESR_ELx_IL) ? 32 : 16); 105 pr_alert(" SET = %lu, FnV = %lu\n", 106 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 107 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 108 pr_alert(" EA = %lu, S1PTW = %lu\n", 109 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 110 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 111 pr_alert(" FSC = 0x%02lx: %s\n", (esr & ESR_ELx_FSC), 112 esr_to_fault_info(esr)->name); 113 114 if (esr_is_data_abort(esr)) 115 data_abort_decode(esr); 116 } 117 118 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm) 119 { 120 /* Either init_pg_dir or swapper_pg_dir */ 121 if (mm == &init_mm) 122 return __pa_symbol(mm->pgd); 123 124 return (unsigned long)virt_to_phys(mm->pgd); 125 } 126 127 /* 128 * Dump out the page tables associated with 'addr' in the currently active mm. 129 */ 130 static void show_pte(unsigned long addr) 131 { 132 struct mm_struct *mm; 133 pgd_t *pgdp; 134 pgd_t pgd; 135 136 if (is_ttbr0_addr(addr)) { 137 /* TTBR0 */ 138 mm = current->active_mm; 139 if (mm == &init_mm) { 140 pr_alert("[%016lx] user address but active_mm is swapper\n", 141 addr); 142 return; 143 } 144 } else if (is_ttbr1_addr(addr)) { 145 /* TTBR1 */ 146 mm = &init_mm; 147 } else { 148 pr_alert("[%016lx] address between user and kernel address ranges\n", 149 addr); 150 return; 151 } 152 153 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", 154 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 155 vabits_actual, mm_to_pgd_phys(mm)); 156 pgdp = pgd_offset(mm, addr); 157 pgd = READ_ONCE(*pgdp); 158 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 159 160 do { 161 p4d_t *p4dp, p4d; 162 pud_t *pudp, pud; 163 pmd_t *pmdp, pmd; 164 pte_t *ptep, pte; 165 166 if (pgd_none(pgd) || pgd_bad(pgd)) 167 break; 168 169 p4dp = p4d_offset(pgdp, addr); 170 p4d = READ_ONCE(*p4dp); 171 pr_cont(", p4d=%016llx", p4d_val(p4d)); 172 if (p4d_none(p4d) || p4d_bad(p4d)) 173 break; 174 175 pudp = pud_offset(p4dp, addr); 176 pud = READ_ONCE(*pudp); 177 pr_cont(", pud=%016llx", pud_val(pud)); 178 if (pud_none(pud) || pud_bad(pud)) 179 break; 180 181 pmdp = pmd_offset(pudp, addr); 182 pmd = READ_ONCE(*pmdp); 183 pr_cont(", pmd=%016llx", pmd_val(pmd)); 184 if (pmd_none(pmd) || pmd_bad(pmd)) 185 break; 186 187 ptep = pte_offset_map(pmdp, addr); 188 if (!ptep) 189 break; 190 191 pte = __ptep_get(ptep); 192 pr_cont(", pte=%016llx", pte_val(pte)); 193 pte_unmap(ptep); 194 } while(0); 195 196 pr_cont("\n"); 197 } 198 199 /* 200 * This function sets the access flags (dirty, accessed), as well as write 201 * permission, and only to a more permissive setting. 202 * 203 * It needs to cope with hardware update of the accessed/dirty state by other 204 * agents in the system and can safely skip the __sync_icache_dcache() call as, 205 * like __set_ptes(), the PTE is never changed from no-exec to exec here. 206 * 207 * Returns whether or not the PTE actually changed. 208 */ 209 int __ptep_set_access_flags_anysz(struct vm_area_struct *vma, 210 unsigned long address, pte_t *ptep, 211 pte_t entry, int dirty, unsigned long pgsize) 212 { 213 pteval_t old_pteval, pteval; 214 pte_t pte = __ptep_get(ptep); 215 int level; 216 217 if (pte_same(pte, entry)) 218 return 0; 219 220 /* only preserve the access flags and write permission */ 221 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 222 223 /* 224 * Setting the flags must be done atomically to avoid racing with the 225 * hardware update of the access/dirty state. The PTE_RDONLY bit must 226 * be set to the most permissive (lowest value) of *ptep and entry 227 * (calculated as: a & b == ~(~a | ~b)). 228 */ 229 pte_val(entry) ^= PTE_RDONLY; 230 pteval = pte_val(pte); 231 do { 232 old_pteval = pteval; 233 pteval ^= PTE_RDONLY; 234 pteval |= pte_val(entry); 235 pteval ^= PTE_RDONLY; 236 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 237 } while (pteval != old_pteval); 238 239 /* 240 * Invalidate the local stale read-only entry. Remote stale entries 241 * may still cause page faults and be invalidated via 242 * flush_tlb_fix_spurious_fault(). 243 */ 244 if (dirty) { 245 switch (pgsize) { 246 case PAGE_SIZE: 247 level = 3; 248 break; 249 case PMD_SIZE: 250 level = 2; 251 break; 252 #ifndef __PAGETABLE_PMD_FOLDED 253 case PUD_SIZE: 254 level = 1; 255 break; 256 #endif 257 default: 258 level = TLBI_TTL_UNKNOWN; 259 WARN_ON(1); 260 } 261 262 __flush_tlb_range(vma, address, address + pgsize, pgsize, level, 263 TLBF_NOWALKCACHE | TLBF_NOBROADCAST); 264 } 265 return 1; 266 } 267 268 static bool is_el1_instruction_abort(unsigned long esr) 269 { 270 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 271 } 272 273 static bool is_el1_data_abort(unsigned long esr) 274 { 275 return ESR_ELx_EC(esr) == ESR_ELx_EC_DABT_CUR; 276 } 277 278 static inline bool is_el1_permission_fault(unsigned long addr, unsigned long esr, 279 struct pt_regs *regs) 280 { 281 if (!is_el1_data_abort(esr) && !is_el1_instruction_abort(esr)) 282 return false; 283 284 if (esr_fsc_is_permission_fault(esr)) 285 return true; 286 287 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 288 return esr_fsc_is_translation_fault(esr) && 289 (regs->pstate & PSR_PAN_BIT); 290 291 return false; 292 } 293 294 static bool is_pkvm_stage2_abort(unsigned int esr) 295 { 296 /* 297 * S1PTW should only ever be set in ESR_EL1 if the pkvm hypervisor 298 * injected a stage-2 abort -- see host_inject_mem_abort(). 299 */ 300 return is_pkvm_initialized() && (esr & ESR_ELx_S1PTW); 301 } 302 303 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, 304 unsigned long esr, 305 struct pt_regs *regs) 306 { 307 unsigned long flags; 308 u64 par, dfsc; 309 310 if (!is_el1_data_abort(esr) || !esr_fsc_is_translation_fault(esr)) 311 return false; 312 313 local_irq_save(flags); 314 asm volatile("at s1e1r, %0" :: "r" (addr)); 315 isb(); 316 par = read_sysreg_par(); 317 local_irq_restore(flags); 318 319 /* 320 * If we now have a valid translation, treat the translation fault as 321 * spurious. 322 */ 323 if (!(par & SYS_PAR_EL1_F)) { 324 if (is_pkvm_stage2_abort(esr)) { 325 par &= SYS_PAR_EL1_PA; 326 return pkvm_force_reclaim_guest_page(par); 327 } 328 329 return true; 330 } 331 332 /* 333 * If we got a different type of fault from the AT instruction, 334 * treat the translation fault as spurious. 335 */ 336 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par); 337 return !esr_fsc_is_translation_fault(dfsc); 338 } 339 340 static void die_kernel_fault(const char *msg, unsigned long addr, 341 unsigned long esr, struct pt_regs *regs) 342 { 343 bust_spinlocks(1); 344 345 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 346 addr); 347 348 kasan_non_canonical_hook(addr); 349 350 mem_abort_decode(esr); 351 352 show_pte(addr); 353 die("Oops", regs, esr); 354 bust_spinlocks(0); 355 make_task_dead(SIGKILL); 356 } 357 358 #ifdef CONFIG_KASAN_HW_TAGS 359 static void report_tag_fault(unsigned long addr, unsigned long esr, 360 struct pt_regs *regs) 361 { 362 /* 363 * SAS bits aren't set for all faults reported in EL1, so we can't 364 * find out access size. 365 */ 366 bool is_write = !!(esr & ESR_ELx_WNR); 367 kasan_report((void *)addr, 0, is_write, regs->pc); 368 } 369 #else 370 /* Tag faults aren't enabled without CONFIG_KASAN_HW_TAGS. */ 371 static inline void report_tag_fault(unsigned long addr, unsigned long esr, 372 struct pt_regs *regs) { } 373 #endif 374 375 static void do_tag_recovery(unsigned long addr, unsigned long esr, 376 struct pt_regs *regs) 377 { 378 379 report_tag_fault(addr, esr, regs); 380 381 /* 382 * Disable MTE Tag Checking on the local CPU for the current EL. 383 * It will be done lazily on the other CPUs when they will hit a 384 * tag fault. 385 */ 386 sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, 387 SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF, NONE)); 388 isb(); 389 } 390 391 static bool is_el1_mte_sync_tag_check_fault(unsigned long esr) 392 { 393 unsigned long fsc = esr & ESR_ELx_FSC; 394 395 if (!is_el1_data_abort(esr)) 396 return false; 397 398 if (fsc == ESR_ELx_FSC_MTE) 399 return true; 400 401 return false; 402 } 403 404 static void __do_kernel_fault(unsigned long addr, unsigned long esr, 405 struct pt_regs *regs) 406 { 407 const char *msg; 408 409 /* 410 * Are we prepared to handle this kernel fault? 411 * We are almost certainly not prepared to handle instruction faults. 412 */ 413 if (!is_el1_instruction_abort(esr) && fixup_exception(regs, esr)) 414 return; 415 416 if (is_spurious_el1_translation_fault(addr, esr, regs)) { 417 WARN_RATELIMIT(!is_pkvm_stage2_abort(esr), 418 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr); 419 return; 420 } 421 422 if (is_el1_mte_sync_tag_check_fault(esr)) { 423 do_tag_recovery(addr, esr, regs); 424 425 return; 426 } 427 428 if (is_el1_permission_fault(addr, esr, regs)) { 429 if (esr & ESR_ELx_WNR) 430 msg = "write to read-only memory"; 431 else if (is_el1_instruction_abort(esr)) 432 msg = "execute from non-executable memory"; 433 else 434 msg = "read from unreadable memory"; 435 } else if (addr < PAGE_SIZE) { 436 msg = "NULL pointer dereference"; 437 } else if (is_pkvm_stage2_abort(esr)) { 438 msg = "access to hypervisor-protected memory"; 439 } else { 440 if (esr_fsc_is_translation_fault(esr)) { 441 if (kfence_handle_page_fault(addr, esr & ESR_ELx_WNR, regs)) 442 return; 443 if (bpf_arena_handle_page_fault(addr, esr & ESR_ELx_WNR, regs->pc)) 444 return; 445 } 446 447 msg = "paging request"; 448 } 449 450 if (efi_runtime_fixup_exception(regs, msg)) 451 return; 452 453 die_kernel_fault(msg, addr, esr, regs); 454 } 455 456 static void set_thread_esr(unsigned long address, unsigned long esr) 457 { 458 current->thread.fault_address = address; 459 460 /* 461 * If the faulting address is in the kernel, we must sanitize the ESR. 462 * From userspace's point of view, kernel-only mappings don't exist 463 * at all, so we report them as level 0 translation faults. 464 * (This is not quite the way that "no mapping there at all" behaves: 465 * an alignment fault not caused by the memory type would take 466 * precedence over translation fault for a real access to empty 467 * space. Unfortunately we can't easily distinguish "alignment fault 468 * not caused by memory type" from "alignment fault caused by memory 469 * type", so we ignore this wrinkle and just return the translation 470 * fault.) 471 */ 472 if (!is_ttbr0_addr(current->thread.fault_address)) { 473 switch (ESR_ELx_EC(esr)) { 474 case ESR_ELx_EC_DABT_LOW: 475 /* 476 * These bits provide only information about the 477 * faulting instruction, which userspace knows already. 478 * We explicitly clear bits which are architecturally 479 * RES0 in case they are given meanings in future. 480 * We always report the ESR as if the fault was taken 481 * to EL1 and so ISV and the bits in ISS[23:14] are 482 * clear. (In fact it always will be a fault to EL1.) 483 */ 484 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 485 ESR_ELx_CM | ESR_ELx_WNR; 486 esr |= ESR_ELx_FSC_FAULT; 487 break; 488 case ESR_ELx_EC_IABT_LOW: 489 /* 490 * Claim a level 0 translation fault. 491 * All other bits are architecturally RES0 for faults 492 * reported with that DFSC value, so we clear them. 493 */ 494 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 495 esr |= ESR_ELx_FSC_FAULT; 496 break; 497 default: 498 /* 499 * This should never happen (entry.S only brings us 500 * into this code for insn and data aborts from a lower 501 * exception level). Fail safe by not providing an ESR 502 * context record at all. 503 */ 504 WARN(1, "ESR 0x%lx is not DABT or IABT from EL0\n", esr); 505 esr = 0; 506 break; 507 } 508 } 509 510 current->thread.fault_code = esr; 511 } 512 513 static void do_bad_area(unsigned long far, unsigned long esr, 514 struct pt_regs *regs) 515 { 516 unsigned long addr = untagged_addr(far); 517 518 /* 519 * If we are in kernel mode at this point, we have no context to 520 * handle this fault with. 521 */ 522 if (user_mode(regs)) { 523 const struct fault_info *inf = esr_to_fault_info(esr); 524 525 set_thread_esr(addr, esr); 526 arm64_force_sig_fault(inf->sig, inf->code, far, inf->name); 527 } else { 528 __do_kernel_fault(addr, esr, regs); 529 } 530 } 531 532 static bool fault_from_pkey(struct vm_area_struct *vma, unsigned int mm_flags) 533 { 534 if (!system_supports_poe()) 535 return false; 536 537 /* 538 * We do not check whether an Overlay fault has occurred because we 539 * cannot make a decision based solely on its value: 540 * 541 * - If Overlay is set, a fault did occur due to POE, but it may be 542 * spurious in those cases where we update POR_EL0 without ISB (e.g. 543 * on context-switch). We would then need to manually check POR_EL0 544 * against vma_pkey(vma), which is exactly what 545 * arch_vma_access_permitted() does. 546 * 547 * - If Overlay is not set, we may still need to report a pkey fault. 548 * This is the case if an access was made within a mapping but with no 549 * page mapped, and POR_EL0 forbids the access (according to 550 * vma_pkey()). Such access will result in a SIGSEGV regardless 551 * because core code checks arch_vma_access_permitted(), but in order 552 * to report the correct error code - SEGV_PKUERR - we must handle 553 * that case here. 554 */ 555 return !arch_vma_access_permitted(vma, 556 mm_flags & FAULT_FLAG_WRITE, 557 mm_flags & FAULT_FLAG_INSTRUCTION, 558 false); 559 } 560 561 static bool is_gcs_fault(unsigned long esr) 562 { 563 if (!esr_is_data_abort(esr)) 564 return false; 565 566 return ESR_ELx_ISS2(esr) & ESR_ELx_GCS; 567 } 568 569 static bool is_el0_instruction_abort(unsigned long esr) 570 { 571 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 572 } 573 574 /* 575 * Note: not valid for EL1 DC IVAC, but we never use that such that it 576 * should fault. EL0 cannot issue DC IVAC (undef). 577 */ 578 static bool is_write_abort(unsigned long esr) 579 { 580 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 581 } 582 583 static bool is_invalid_gcs_access(struct vm_area_struct *vma, u64 esr) 584 { 585 if (!system_supports_gcs()) 586 return false; 587 588 if (unlikely(is_gcs_fault(esr))) { 589 /* GCS accesses must be performed on a GCS page */ 590 if (!(vma->vm_flags & VM_SHADOW_STACK)) 591 return true; 592 } else if (unlikely(vma->vm_flags & VM_SHADOW_STACK)) { 593 /* Only GCS operations can write to a GCS page */ 594 return esr_is_data_abort(esr) && is_write_abort(esr); 595 } 596 597 return false; 598 } 599 600 static int __kprobes do_page_fault(unsigned long far, unsigned long esr, 601 struct pt_regs *regs) 602 { 603 const struct fault_info *inf; 604 struct mm_struct *mm = current->mm; 605 vm_fault_t fault; 606 vm_flags_t vm_flags; 607 unsigned int mm_flags = FAULT_FLAG_DEFAULT; 608 unsigned long addr = untagged_addr(far); 609 struct vm_area_struct *vma; 610 int si_code; 611 int pkey = -1; 612 613 if (kprobe_page_fault(regs, esr)) 614 return 0; 615 616 /* 617 * If we're in an interrupt or have no user context, we must not take 618 * the fault. 619 */ 620 if (faulthandler_disabled() || !mm) 621 goto no_context; 622 623 if (user_mode(regs)) 624 mm_flags |= FAULT_FLAG_USER; 625 626 /* 627 * vm_flags tells us what bits we must have in vma->vm_flags 628 * for the fault to be benign, __do_page_fault() would check 629 * vma->vm_flags & vm_flags and returns an error if the 630 * intersection is empty 631 */ 632 if (is_el0_instruction_abort(esr)) { 633 /* It was exec fault */ 634 vm_flags = VM_EXEC; 635 mm_flags |= FAULT_FLAG_INSTRUCTION; 636 } else if (is_gcs_fault(esr)) { 637 /* 638 * The GCS permission on a page implies both read and 639 * write so always handle any GCS fault as a write fault, 640 * we need to trigger CoW even for GCS reads. 641 */ 642 vm_flags = VM_WRITE; 643 mm_flags |= FAULT_FLAG_WRITE; 644 } else if (is_write_abort(esr)) { 645 /* It was write fault */ 646 vm_flags = VM_WRITE; 647 mm_flags |= FAULT_FLAG_WRITE; 648 } else { 649 /* It was read fault */ 650 vm_flags = VM_READ; 651 /* Write implies read */ 652 vm_flags |= VM_WRITE; 653 /* If EPAN is absent then exec implies read */ 654 if (!alternative_has_cap_unlikely(ARM64_HAS_EPAN)) 655 vm_flags |= VM_EXEC; 656 } 657 658 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 659 if (is_el1_instruction_abort(esr)) 660 die_kernel_fault("execution of user memory", 661 addr, esr, regs); 662 663 if (!insn_may_access_user(regs->pc, esr)) 664 die_kernel_fault("access to user memory outside uaccess routines", 665 addr, esr, regs); 666 } 667 668 if (is_pkvm_stage2_abort(esr)) { 669 if (!user_mode(regs)) 670 goto no_context; 671 arm64_force_sig_fault(SIGSEGV, SEGV_ACCERR, far, "stage-2 fault"); 672 return 0; 673 } 674 675 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 676 677 if (!(mm_flags & FAULT_FLAG_USER)) 678 goto lock_mmap; 679 680 vma = lock_vma_under_rcu(mm, addr); 681 if (!vma) 682 goto lock_mmap; 683 684 if (is_invalid_gcs_access(vma, esr)) { 685 vma_end_read(vma); 686 fault = 0; 687 si_code = SEGV_ACCERR; 688 goto bad_area; 689 } 690 691 if (!(vma->vm_flags & vm_flags)) { 692 vma_end_read(vma); 693 fault = 0; 694 si_code = SEGV_ACCERR; 695 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 696 goto bad_area; 697 } 698 699 if (fault_from_pkey(vma, mm_flags)) { 700 pkey = vma_pkey(vma); 701 vma_end_read(vma); 702 fault = 0; 703 si_code = SEGV_PKUERR; 704 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 705 goto bad_area; 706 } 707 708 fault = handle_mm_fault(vma, addr, mm_flags | FAULT_FLAG_VMA_LOCK, regs); 709 if (!(fault & (VM_FAULT_RETRY | VM_FAULT_COMPLETED))) 710 vma_end_read(vma); 711 712 if (!(fault & VM_FAULT_RETRY)) { 713 count_vm_vma_lock_event(VMA_LOCK_SUCCESS); 714 goto done; 715 } 716 count_vm_vma_lock_event(VMA_LOCK_RETRY); 717 if (fault & VM_FAULT_MAJOR) 718 mm_flags |= FAULT_FLAG_TRIED; 719 720 /* Quick path to respond to signals */ 721 if (fault_signal_pending(fault, regs)) { 722 if (!user_mode(regs)) 723 goto no_context; 724 return 0; 725 } 726 lock_mmap: 727 728 retry: 729 vma = lock_mm_and_find_vma(mm, addr, regs); 730 if (unlikely(!vma)) { 731 fault = 0; 732 si_code = SEGV_MAPERR; 733 goto bad_area; 734 } 735 736 if (!(vma->vm_flags & vm_flags)) { 737 mmap_read_unlock(mm); 738 fault = 0; 739 si_code = SEGV_ACCERR; 740 goto bad_area; 741 } 742 743 if (fault_from_pkey(vma, mm_flags)) { 744 pkey = vma_pkey(vma); 745 mmap_read_unlock(mm); 746 fault = 0; 747 si_code = SEGV_PKUERR; 748 goto bad_area; 749 } 750 751 fault = handle_mm_fault(vma, addr, mm_flags, regs); 752 753 /* Quick path to respond to signals */ 754 if (fault_signal_pending(fault, regs)) { 755 if (!user_mode(regs)) 756 goto no_context; 757 return 0; 758 } 759 760 /* The fault is fully completed (including releasing mmap lock) */ 761 if (fault & VM_FAULT_COMPLETED) 762 return 0; 763 764 if (fault & VM_FAULT_RETRY) { 765 mm_flags |= FAULT_FLAG_TRIED; 766 goto retry; 767 } 768 mmap_read_unlock(mm); 769 770 done: 771 /* Handle the "normal" (no error) case first. */ 772 if (likely(!(fault & VM_FAULT_ERROR))) 773 return 0; 774 775 si_code = SEGV_MAPERR; 776 bad_area: 777 /* 778 * If we are in kernel mode at this point, we have no context to 779 * handle this fault with. 780 */ 781 if (!user_mode(regs)) 782 goto no_context; 783 784 if (fault & VM_FAULT_OOM) { 785 /* 786 * We ran out of memory, call the OOM killer, and return to 787 * userspace (which will retry the fault, or kill us if we got 788 * oom-killed). 789 */ 790 pagefault_out_of_memory(); 791 return 0; 792 } 793 794 inf = esr_to_fault_info(esr); 795 set_thread_esr(addr, esr); 796 if (fault & VM_FAULT_SIGBUS) { 797 /* 798 * We had some memory, but were unable to successfully fix up 799 * this page fault. 800 */ 801 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, far, inf->name); 802 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 803 unsigned int lsb; 804 805 lsb = PAGE_SHIFT; 806 if (fault & VM_FAULT_HWPOISON_LARGE) 807 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 808 809 arm64_force_sig_mceerr(BUS_MCEERR_AR, far, lsb, inf->name); 810 } else { 811 /* 812 * The pkey value that we return to userspace can be different 813 * from the pkey that caused the fault. 814 * 815 * 1. T1 : mprotect_key(foo, PAGE_SIZE, pkey=4); 816 * 2. T1 : set POR_EL0 to deny access to pkey=4, touches, page 817 * 3. T1 : faults... 818 * 4. T2: mprotect_key(foo, PAGE_SIZE, pkey=5); 819 * 5. T1 : enters fault handler, takes mmap_lock, etc... 820 * 6. T1 : reaches here, sees vma_pkey(vma)=5, when we really 821 * faulted on a pte with its pkey=4. 822 */ 823 /* Something tried to access memory that out of memory map */ 824 if (si_code == SEGV_PKUERR) 825 arm64_force_sig_fault_pkey(far, inf->name, pkey); 826 else 827 arm64_force_sig_fault(SIGSEGV, si_code, far, inf->name); 828 } 829 830 return 0; 831 832 no_context: 833 __do_kernel_fault(addr, esr, regs); 834 return 0; 835 } 836 837 static int __kprobes do_translation_fault(unsigned long far, 838 unsigned long esr, 839 struct pt_regs *regs) 840 { 841 unsigned long addr = untagged_addr(far); 842 843 if (is_ttbr0_addr(addr)) 844 return do_page_fault(far, esr, regs); 845 846 do_bad_area(far, esr, regs); 847 return 0; 848 } 849 850 static int do_alignment_fault(unsigned long far, unsigned long esr, 851 struct pt_regs *regs) 852 { 853 if (IS_ENABLED(CONFIG_COMPAT_ALIGNMENT_FIXUPS) && 854 compat_user_mode(regs)) 855 return do_compat_alignment_fixup(far, regs); 856 do_bad_area(far, esr, regs); 857 return 0; 858 } 859 860 static int do_bad(unsigned long far, unsigned long esr, struct pt_regs *regs) 861 { 862 return 1; /* "fault" */ 863 } 864 865 static int do_sea(unsigned long far, unsigned long esr, struct pt_regs *regs) 866 { 867 const struct fault_info *inf; 868 unsigned long siaddr; 869 870 inf = esr_to_fault_info(esr); 871 872 if (user_mode(regs) && apei_claim_sea(regs) == 0) { 873 /* 874 * APEI claimed this as a firmware-first notification. 875 * Some processing deferred to task_work before ret_to_user(). 876 */ 877 return 0; 878 } 879 880 if (esr & ESR_ELx_FnV) { 881 siaddr = 0; 882 } else { 883 /* 884 * The architecture specifies that the tag bits of FAR_EL1 are 885 * UNKNOWN for synchronous external aborts. Mask them out now 886 * so that userspace doesn't see them. 887 */ 888 siaddr = untagged_addr(far); 889 } 890 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 891 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 892 893 return 0; 894 } 895 896 static int do_tag_check_fault(unsigned long far, unsigned long esr, 897 struct pt_regs *regs) 898 { 899 /* 900 * The architecture specifies that bits 63:60 of FAR_EL1 are UNKNOWN 901 * for tag check faults. Set them to corresponding bits in the untagged 902 * address if ARM64_MTE_FAR isn't supported. 903 * Otherwise, bits 63:60 of FAR_EL1 are not UNKNOWN. 904 */ 905 if (!cpus_have_cap(ARM64_MTE_FAR)) 906 far = (__untagged_addr(far) & ~MTE_TAG_MASK) | (far & MTE_TAG_MASK); 907 908 do_bad_area(far, esr, regs); 909 return 0; 910 } 911 912 static const struct fault_info fault_info[] = { 913 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 914 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 915 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 916 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 917 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 918 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 919 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 920 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 921 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 0 access flag fault" }, 922 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 923 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 924 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 925 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 0 permission fault" }, 926 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 927 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 928 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 929 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 930 { do_tag_check_fault, SIGSEGV, SEGV_MTESERR, "synchronous tag check fault" }, 931 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 932 { do_sea, SIGKILL, SI_KERNEL, "level -1 (translation table walk)" }, 933 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 934 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 935 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 936 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 937 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 938 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 939 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 940 { do_sea, SIGKILL, SI_KERNEL, "level -1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 941 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 942 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 943 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 944 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 945 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 946 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 947 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 948 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 949 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 950 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 951 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 952 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 953 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 954 { do_bad, SIGKILL, SI_KERNEL, "level -1 address size fault" }, 955 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 956 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level -1 translation fault" }, 957 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 958 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 959 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 960 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 961 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 962 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 963 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 964 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 965 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 966 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 967 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 968 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 969 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 970 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 971 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 972 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 973 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 974 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 975 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 976 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 977 }; 978 979 void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *regs) 980 { 981 const struct fault_info *inf = esr_to_fault_info(esr); 982 unsigned long addr = untagged_addr(far); 983 984 if (!inf->fn(far, esr, regs)) 985 return; 986 987 if (!user_mode(regs)) 988 die_kernel_fault(inf->name, addr, esr, regs); 989 990 /* 991 * At this point we have an unrecognized fault type whose tag bits may 992 * have been defined as UNKNOWN. Therefore we only expose the untagged 993 * address to the signal handler. 994 */ 995 arm64_notify_die(inf->name, regs, inf->sig, inf->code, addr, esr); 996 } 997 NOKPROBE_SYMBOL(do_mem_abort); 998 999 void do_sp_pc_abort(unsigned long addr, unsigned long esr, struct pt_regs *regs) 1000 { 1001 arm64_notify_die("SP/PC alignment exception", regs, SIGBUS, BUS_ADRALN, 1002 addr, esr); 1003 } 1004 NOKPROBE_SYMBOL(do_sp_pc_abort); 1005 1006 /* 1007 * Used during anonymous page fault handling. 1008 */ 1009 struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma, 1010 unsigned long vaddr) 1011 { 1012 gfp_t flags = GFP_HIGHUSER_MOVABLE | __GFP_ZERO; 1013 1014 /* 1015 * If the page is mapped with PROT_MTE, initialise the tags at the 1016 * point of allocation and page zeroing as this is usually faster than 1017 * separate DC ZVA and STGM. 1018 */ 1019 if (vma->vm_flags & VM_MTE) 1020 flags |= __GFP_ZEROTAGS; 1021 1022 return vma_alloc_folio(flags, 0, vma, vaddr); 1023 } 1024 1025 bool tag_clear_highpages(struct page *page, int numpages, bool clear_pages) 1026 { 1027 /* 1028 * Check if MTE is supported and fall back to clear_highpage(). 1029 * get_huge_zero_folio() unconditionally passes __GFP_ZEROTAGS and 1030 * post_alloc_hook() will invoke tag_clear_highpages(). 1031 */ 1032 if (!system_supports_mte()) 1033 return clear_pages; 1034 1035 /* Newly allocated pages, shouldn't have been tagged yet */ 1036 for (int i = 0; i < numpages; i++, page++) { 1037 WARN_ON_ONCE(!try_page_mte_tagging(page)); 1038 if (clear_pages) 1039 mte_zero_clear_page_tags(page_address(page)); 1040 else 1041 mte_clear_page_tags(page_address(page)); 1042 set_page_mte_tagged(page); 1043 } 1044 return false; 1045 } 1046