1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on arch/arm/mm/fault.c 4 * 5 * Copyright (C) 1995 Linus Torvalds 6 * Copyright (C) 1995-2004 Russell King 7 * Copyright (C) 2012 ARM Ltd. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/extable.h> 13 #include <linux/signal.h> 14 #include <linux/mm.h> 15 #include <linux/hardirq.h> 16 #include <linux/init.h> 17 #include <linux/kprobes.h> 18 #include <linux/uaccess.h> 19 #include <linux/page-flags.h> 20 #include <linux/sched/signal.h> 21 #include <linux/sched/debug.h> 22 #include <linux/highmem.h> 23 #include <linux/perf_event.h> 24 #include <linux/preempt.h> 25 #include <linux/hugetlb.h> 26 27 #include <asm/acpi.h> 28 #include <asm/bug.h> 29 #include <asm/cmpxchg.h> 30 #include <asm/cpufeature.h> 31 #include <asm/exception.h> 32 #include <asm/daifflags.h> 33 #include <asm/debug-monitors.h> 34 #include <asm/esr.h> 35 #include <asm/kasan.h> 36 #include <asm/sysreg.h> 37 #include <asm/system_misc.h> 38 #include <asm/pgtable.h> 39 #include <asm/tlbflush.h> 40 #include <asm/traps.h> 41 42 struct fault_info { 43 int (*fn)(unsigned long addr, unsigned int esr, 44 struct pt_regs *regs); 45 int sig; 46 int code; 47 const char *name; 48 }; 49 50 static const struct fault_info fault_info[]; 51 static struct fault_info debug_fault_info[]; 52 53 static inline const struct fault_info *esr_to_fault_info(unsigned int esr) 54 { 55 return fault_info + (esr & ESR_ELx_FSC); 56 } 57 58 static inline const struct fault_info *esr_to_debug_fault_info(unsigned int esr) 59 { 60 return debug_fault_info + DBG_ESR_EVT(esr); 61 } 62 63 static void data_abort_decode(unsigned int esr) 64 { 65 pr_alert("Data abort info:\n"); 66 67 if (esr & ESR_ELx_ISV) { 68 pr_alert(" Access size = %u byte(s)\n", 69 1U << ((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT)); 70 pr_alert(" SSE = %lu, SRT = %lu\n", 71 (esr & ESR_ELx_SSE) >> ESR_ELx_SSE_SHIFT, 72 (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT); 73 pr_alert(" SF = %lu, AR = %lu\n", 74 (esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT, 75 (esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT); 76 } else { 77 pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK); 78 } 79 80 pr_alert(" CM = %lu, WnR = %lu\n", 81 (esr & ESR_ELx_CM) >> ESR_ELx_CM_SHIFT, 82 (esr & ESR_ELx_WNR) >> ESR_ELx_WNR_SHIFT); 83 } 84 85 static void mem_abort_decode(unsigned int esr) 86 { 87 pr_alert("Mem abort info:\n"); 88 89 pr_alert(" ESR = 0x%08x\n", esr); 90 pr_alert(" EC = 0x%02lx: %s, IL = %u bits\n", 91 ESR_ELx_EC(esr), esr_get_class_string(esr), 92 (esr & ESR_ELx_IL) ? 32 : 16); 93 pr_alert(" SET = %lu, FnV = %lu\n", 94 (esr & ESR_ELx_SET_MASK) >> ESR_ELx_SET_SHIFT, 95 (esr & ESR_ELx_FnV) >> ESR_ELx_FnV_SHIFT); 96 pr_alert(" EA = %lu, S1PTW = %lu\n", 97 (esr & ESR_ELx_EA) >> ESR_ELx_EA_SHIFT, 98 (esr & ESR_ELx_S1PTW) >> ESR_ELx_S1PTW_SHIFT); 99 100 if (esr_is_data_abort(esr)) 101 data_abort_decode(esr); 102 } 103 104 static inline bool is_ttbr0_addr(unsigned long addr) 105 { 106 /* entry assembly clears tags for TTBR0 addrs */ 107 return addr < TASK_SIZE; 108 } 109 110 static inline bool is_ttbr1_addr(unsigned long addr) 111 { 112 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ 113 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET; 114 } 115 116 static inline unsigned long mm_to_pgd_phys(struct mm_struct *mm) 117 { 118 /* Either init_pg_dir or swapper_pg_dir */ 119 if (mm == &init_mm) 120 return __pa_symbol(mm->pgd); 121 122 return (unsigned long)virt_to_phys(mm->pgd); 123 } 124 125 /* 126 * Dump out the page tables associated with 'addr' in the currently active mm. 127 */ 128 static void show_pte(unsigned long addr) 129 { 130 struct mm_struct *mm; 131 pgd_t *pgdp; 132 pgd_t pgd; 133 134 if (is_ttbr0_addr(addr)) { 135 /* TTBR0 */ 136 mm = current->active_mm; 137 if (mm == &init_mm) { 138 pr_alert("[%016lx] user address but active_mm is swapper\n", 139 addr); 140 return; 141 } 142 } else if (is_ttbr1_addr(addr)) { 143 /* TTBR1 */ 144 mm = &init_mm; 145 } else { 146 pr_alert("[%016lx] address between user and kernel address ranges\n", 147 addr); 148 return; 149 } 150 151 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", 152 mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K, 153 vabits_actual, mm_to_pgd_phys(mm)); 154 pgdp = pgd_offset(mm, addr); 155 pgd = READ_ONCE(*pgdp); 156 pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd)); 157 158 do { 159 pud_t *pudp, pud; 160 pmd_t *pmdp, pmd; 161 pte_t *ptep, pte; 162 163 if (pgd_none(pgd) || pgd_bad(pgd)) 164 break; 165 166 pudp = pud_offset(pgdp, addr); 167 pud = READ_ONCE(*pudp); 168 pr_cont(", pud=%016llx", pud_val(pud)); 169 if (pud_none(pud) || pud_bad(pud)) 170 break; 171 172 pmdp = pmd_offset(pudp, addr); 173 pmd = READ_ONCE(*pmdp); 174 pr_cont(", pmd=%016llx", pmd_val(pmd)); 175 if (pmd_none(pmd) || pmd_bad(pmd)) 176 break; 177 178 ptep = pte_offset_map(pmdp, addr); 179 pte = READ_ONCE(*ptep); 180 pr_cont(", pte=%016llx", pte_val(pte)); 181 pte_unmap(ptep); 182 } while(0); 183 184 pr_cont("\n"); 185 } 186 187 /* 188 * This function sets the access flags (dirty, accessed), as well as write 189 * permission, and only to a more permissive setting. 190 * 191 * It needs to cope with hardware update of the accessed/dirty state by other 192 * agents in the system and can safely skip the __sync_icache_dcache() call as, 193 * like set_pte_at(), the PTE is never changed from no-exec to exec here. 194 * 195 * Returns whether or not the PTE actually changed. 196 */ 197 int ptep_set_access_flags(struct vm_area_struct *vma, 198 unsigned long address, pte_t *ptep, 199 pte_t entry, int dirty) 200 { 201 pteval_t old_pteval, pteval; 202 pte_t pte = READ_ONCE(*ptep); 203 204 if (pte_same(pte, entry)) 205 return 0; 206 207 /* only preserve the access flags and write permission */ 208 pte_val(entry) &= PTE_RDONLY | PTE_AF | PTE_WRITE | PTE_DIRTY; 209 210 /* 211 * Setting the flags must be done atomically to avoid racing with the 212 * hardware update of the access/dirty state. The PTE_RDONLY bit must 213 * be set to the most permissive (lowest value) of *ptep and entry 214 * (calculated as: a & b == ~(~a | ~b)). 215 */ 216 pte_val(entry) ^= PTE_RDONLY; 217 pteval = pte_val(pte); 218 do { 219 old_pteval = pteval; 220 pteval ^= PTE_RDONLY; 221 pteval |= pte_val(entry); 222 pteval ^= PTE_RDONLY; 223 pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval); 224 } while (pteval != old_pteval); 225 226 flush_tlb_fix_spurious_fault(vma, address); 227 return 1; 228 } 229 230 static bool is_el1_instruction_abort(unsigned int esr) 231 { 232 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 233 } 234 235 static inline bool is_el1_permission_fault(unsigned long addr, unsigned int esr, 236 struct pt_regs *regs) 237 { 238 unsigned int ec = ESR_ELx_EC(esr); 239 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; 240 241 if (ec != ESR_ELx_EC_DABT_CUR && ec != ESR_ELx_EC_IABT_CUR) 242 return false; 243 244 if (fsc_type == ESR_ELx_FSC_PERM) 245 return true; 246 247 if (is_ttbr0_addr(addr) && system_uses_ttbr0_pan()) 248 return fsc_type == ESR_ELx_FSC_FAULT && 249 (regs->pstate & PSR_PAN_BIT); 250 251 return false; 252 } 253 254 static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr, 255 unsigned int esr, 256 struct pt_regs *regs) 257 { 258 unsigned long flags; 259 u64 par, dfsc; 260 261 if (ESR_ELx_EC(esr) != ESR_ELx_EC_DABT_CUR || 262 (esr & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT) 263 return false; 264 265 local_irq_save(flags); 266 asm volatile("at s1e1r, %0" :: "r" (addr)); 267 isb(); 268 par = read_sysreg(par_el1); 269 local_irq_restore(flags); 270 271 if (!(par & SYS_PAR_EL1_F)) 272 return false; 273 274 /* 275 * If we got a different type of fault from the AT instruction, 276 * treat the translation fault as spurious. 277 */ 278 dfsc = FIELD_GET(SYS_PAR_EL1_FST, par); 279 return (dfsc & ESR_ELx_FSC_TYPE) != ESR_ELx_FSC_FAULT; 280 } 281 282 static void die_kernel_fault(const char *msg, unsigned long addr, 283 unsigned int esr, struct pt_regs *regs) 284 { 285 bust_spinlocks(1); 286 287 pr_alert("Unable to handle kernel %s at virtual address %016lx\n", msg, 288 addr); 289 290 mem_abort_decode(esr); 291 292 show_pte(addr); 293 die("Oops", regs, esr); 294 bust_spinlocks(0); 295 do_exit(SIGKILL); 296 } 297 298 static void __do_kernel_fault(unsigned long addr, unsigned int esr, 299 struct pt_regs *regs) 300 { 301 const char *msg; 302 303 /* 304 * Are we prepared to handle this kernel fault? 305 * We are almost certainly not prepared to handle instruction faults. 306 */ 307 if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) 308 return; 309 310 if (WARN_RATELIMIT(is_spurious_el1_translation_fault(addr, esr, regs), 311 "Ignoring spurious kernel translation fault at virtual address %016lx\n", addr)) 312 return; 313 314 if (is_el1_permission_fault(addr, esr, regs)) { 315 if (esr & ESR_ELx_WNR) 316 msg = "write to read-only memory"; 317 else 318 msg = "read from unreadable memory"; 319 } else if (addr < PAGE_SIZE) { 320 msg = "NULL pointer dereference"; 321 } else { 322 msg = "paging request"; 323 } 324 325 die_kernel_fault(msg, addr, esr, regs); 326 } 327 328 static void set_thread_esr(unsigned long address, unsigned int esr) 329 { 330 current->thread.fault_address = address; 331 332 /* 333 * If the faulting address is in the kernel, we must sanitize the ESR. 334 * From userspace's point of view, kernel-only mappings don't exist 335 * at all, so we report them as level 0 translation faults. 336 * (This is not quite the way that "no mapping there at all" behaves: 337 * an alignment fault not caused by the memory type would take 338 * precedence over translation fault for a real access to empty 339 * space. Unfortunately we can't easily distinguish "alignment fault 340 * not caused by memory type" from "alignment fault caused by memory 341 * type", so we ignore this wrinkle and just return the translation 342 * fault.) 343 */ 344 if (!is_ttbr0_addr(current->thread.fault_address)) { 345 switch (ESR_ELx_EC(esr)) { 346 case ESR_ELx_EC_DABT_LOW: 347 /* 348 * These bits provide only information about the 349 * faulting instruction, which userspace knows already. 350 * We explicitly clear bits which are architecturally 351 * RES0 in case they are given meanings in future. 352 * We always report the ESR as if the fault was taken 353 * to EL1 and so ISV and the bits in ISS[23:14] are 354 * clear. (In fact it always will be a fault to EL1.) 355 */ 356 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | 357 ESR_ELx_CM | ESR_ELx_WNR; 358 esr |= ESR_ELx_FSC_FAULT; 359 break; 360 case ESR_ELx_EC_IABT_LOW: 361 /* 362 * Claim a level 0 translation fault. 363 * All other bits are architecturally RES0 for faults 364 * reported with that DFSC value, so we clear them. 365 */ 366 esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; 367 esr |= ESR_ELx_FSC_FAULT; 368 break; 369 default: 370 /* 371 * This should never happen (entry.S only brings us 372 * into this code for insn and data aborts from a lower 373 * exception level). Fail safe by not providing an ESR 374 * context record at all. 375 */ 376 WARN(1, "ESR 0x%x is not DABT or IABT from EL0\n", esr); 377 esr = 0; 378 break; 379 } 380 } 381 382 current->thread.fault_code = esr; 383 } 384 385 static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) 386 { 387 /* 388 * If we are in kernel mode at this point, we have no context to 389 * handle this fault with. 390 */ 391 if (user_mode(regs)) { 392 const struct fault_info *inf = esr_to_fault_info(esr); 393 394 set_thread_esr(addr, esr); 395 arm64_force_sig_fault(inf->sig, inf->code, (void __user *)addr, 396 inf->name); 397 } else { 398 __do_kernel_fault(addr, esr, regs); 399 } 400 } 401 402 #define VM_FAULT_BADMAP 0x010000 403 #define VM_FAULT_BADACCESS 0x020000 404 405 static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, 406 unsigned int mm_flags, unsigned long vm_flags) 407 { 408 struct vm_area_struct *vma = find_vma(mm, addr); 409 410 if (unlikely(!vma)) 411 return VM_FAULT_BADMAP; 412 413 /* 414 * Ok, we have a good vm_area for this memory access, so we can handle 415 * it. 416 */ 417 if (unlikely(vma->vm_start > addr)) { 418 if (!(vma->vm_flags & VM_GROWSDOWN)) 419 return VM_FAULT_BADMAP; 420 if (expand_stack(vma, addr)) 421 return VM_FAULT_BADMAP; 422 } 423 424 /* 425 * Check that the permissions on the VMA allow for the fault which 426 * occurred. 427 */ 428 if (!(vma->vm_flags & vm_flags)) 429 return VM_FAULT_BADACCESS; 430 return handle_mm_fault(vma, addr & PAGE_MASK, mm_flags); 431 } 432 433 static bool is_el0_instruction_abort(unsigned int esr) 434 { 435 return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW; 436 } 437 438 /* 439 * Note: not valid for EL1 DC IVAC, but we never use that such that it 440 * should fault. EL0 cannot issue DC IVAC (undef). 441 */ 442 static bool is_write_abort(unsigned int esr) 443 { 444 return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM); 445 } 446 447 static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, 448 struct pt_regs *regs) 449 { 450 const struct fault_info *inf; 451 struct mm_struct *mm = current->mm; 452 vm_fault_t fault, major = 0; 453 unsigned long vm_flags = VM_READ | VM_WRITE; 454 unsigned int mm_flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; 455 456 if (kprobe_page_fault(regs, esr)) 457 return 0; 458 459 /* 460 * If we're in an interrupt or have no user context, we must not take 461 * the fault. 462 */ 463 if (faulthandler_disabled() || !mm) 464 goto no_context; 465 466 if (user_mode(regs)) 467 mm_flags |= FAULT_FLAG_USER; 468 469 if (is_el0_instruction_abort(esr)) { 470 vm_flags = VM_EXEC; 471 mm_flags |= FAULT_FLAG_INSTRUCTION; 472 } else if (is_write_abort(esr)) { 473 vm_flags = VM_WRITE; 474 mm_flags |= FAULT_FLAG_WRITE; 475 } 476 477 if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, regs)) { 478 /* regs->orig_addr_limit may be 0 if we entered from EL0 */ 479 if (regs->orig_addr_limit == KERNEL_DS) 480 die_kernel_fault("access to user memory with fs=KERNEL_DS", 481 addr, esr, regs); 482 483 if (is_el1_instruction_abort(esr)) 484 die_kernel_fault("execution of user memory", 485 addr, esr, regs); 486 487 if (!search_exception_tables(regs->pc)) 488 die_kernel_fault("access to user memory outside uaccess routines", 489 addr, esr, regs); 490 } 491 492 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); 493 494 /* 495 * As per x86, we may deadlock here. However, since the kernel only 496 * validly references user space from well defined areas of the code, 497 * we can bug out early if this is from code which shouldn't. 498 */ 499 if (!down_read_trylock(&mm->mmap_sem)) { 500 if (!user_mode(regs) && !search_exception_tables(regs->pc)) 501 goto no_context; 502 retry: 503 down_read(&mm->mmap_sem); 504 } else { 505 /* 506 * The above down_read_trylock() might have succeeded in which 507 * case, we'll have missed the might_sleep() from down_read(). 508 */ 509 might_sleep(); 510 #ifdef CONFIG_DEBUG_VM 511 if (!user_mode(regs) && !search_exception_tables(regs->pc)) { 512 up_read(&mm->mmap_sem); 513 goto no_context; 514 } 515 #endif 516 } 517 518 fault = __do_page_fault(mm, addr, mm_flags, vm_flags); 519 major |= fault & VM_FAULT_MAJOR; 520 521 if (fault & VM_FAULT_RETRY) { 522 /* 523 * If we need to retry but a fatal signal is pending, 524 * handle the signal first. We do not need to release 525 * the mmap_sem because it would already be released 526 * in __lock_page_or_retry in mm/filemap.c. 527 */ 528 if (fatal_signal_pending(current)) { 529 if (!user_mode(regs)) 530 goto no_context; 531 return 0; 532 } 533 534 /* 535 * Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk of 536 * starvation. 537 */ 538 if (mm_flags & FAULT_FLAG_ALLOW_RETRY) { 539 mm_flags &= ~FAULT_FLAG_ALLOW_RETRY; 540 mm_flags |= FAULT_FLAG_TRIED; 541 goto retry; 542 } 543 } 544 up_read(&mm->mmap_sem); 545 546 /* 547 * Handle the "normal" (no error) case first. 548 */ 549 if (likely(!(fault & (VM_FAULT_ERROR | VM_FAULT_BADMAP | 550 VM_FAULT_BADACCESS)))) { 551 /* 552 * Major/minor page fault accounting is only done 553 * once. If we go through a retry, it is extremely 554 * likely that the page will be found in page cache at 555 * that point. 556 */ 557 if (major) { 558 current->maj_flt++; 559 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, 560 addr); 561 } else { 562 current->min_flt++; 563 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, 564 addr); 565 } 566 567 return 0; 568 } 569 570 /* 571 * If we are in kernel mode at this point, we have no context to 572 * handle this fault with. 573 */ 574 if (!user_mode(regs)) 575 goto no_context; 576 577 if (fault & VM_FAULT_OOM) { 578 /* 579 * We ran out of memory, call the OOM killer, and return to 580 * userspace (which will retry the fault, or kill us if we got 581 * oom-killed). 582 */ 583 pagefault_out_of_memory(); 584 return 0; 585 } 586 587 inf = esr_to_fault_info(esr); 588 set_thread_esr(addr, esr); 589 if (fault & VM_FAULT_SIGBUS) { 590 /* 591 * We had some memory, but were unable to successfully fix up 592 * this page fault. 593 */ 594 arm64_force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr, 595 inf->name); 596 } else if (fault & (VM_FAULT_HWPOISON_LARGE | VM_FAULT_HWPOISON)) { 597 unsigned int lsb; 598 599 lsb = PAGE_SHIFT; 600 if (fault & VM_FAULT_HWPOISON_LARGE) 601 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); 602 603 arm64_force_sig_mceerr(BUS_MCEERR_AR, (void __user *)addr, lsb, 604 inf->name); 605 } else { 606 /* 607 * Something tried to access memory that isn't in our memory 608 * map. 609 */ 610 arm64_force_sig_fault(SIGSEGV, 611 fault == VM_FAULT_BADACCESS ? SEGV_ACCERR : SEGV_MAPERR, 612 (void __user *)addr, 613 inf->name); 614 } 615 616 return 0; 617 618 no_context: 619 __do_kernel_fault(addr, esr, regs); 620 return 0; 621 } 622 623 static int __kprobes do_translation_fault(unsigned long addr, 624 unsigned int esr, 625 struct pt_regs *regs) 626 { 627 if (is_ttbr0_addr(addr)) 628 return do_page_fault(addr, esr, regs); 629 630 do_bad_area(addr, esr, regs); 631 return 0; 632 } 633 634 static int do_alignment_fault(unsigned long addr, unsigned int esr, 635 struct pt_regs *regs) 636 { 637 do_bad_area(addr, esr, regs); 638 return 0; 639 } 640 641 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs) 642 { 643 return 1; /* "fault" */ 644 } 645 646 static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs) 647 { 648 const struct fault_info *inf; 649 void __user *siaddr; 650 651 inf = esr_to_fault_info(esr); 652 653 /* 654 * Return value ignored as we rely on signal merging. 655 * Future patches will make this more robust. 656 */ 657 apei_claim_sea(regs); 658 659 if (esr & ESR_ELx_FnV) 660 siaddr = NULL; 661 else 662 siaddr = (void __user *)addr; 663 arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); 664 665 return 0; 666 } 667 668 static const struct fault_info fault_info[] = { 669 { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, 670 { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, 671 { do_bad, SIGKILL, SI_KERNEL, "level 2 address size fault" }, 672 { do_bad, SIGKILL, SI_KERNEL, "level 3 address size fault" }, 673 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" }, 674 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" }, 675 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" }, 676 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" }, 677 { do_bad, SIGKILL, SI_KERNEL, "unknown 8" }, 678 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" }, 679 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" }, 680 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 access flag fault" }, 681 { do_bad, SIGKILL, SI_KERNEL, "unknown 12" }, 682 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" }, 683 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" }, 684 { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" }, 685 { do_sea, SIGBUS, BUS_OBJERR, "synchronous external abort" }, 686 { do_bad, SIGKILL, SI_KERNEL, "unknown 17" }, 687 { do_bad, SIGKILL, SI_KERNEL, "unknown 18" }, 688 { do_bad, SIGKILL, SI_KERNEL, "unknown 19" }, 689 { do_sea, SIGKILL, SI_KERNEL, "level 0 (translation table walk)" }, 690 { do_sea, SIGKILL, SI_KERNEL, "level 1 (translation table walk)" }, 691 { do_sea, SIGKILL, SI_KERNEL, "level 2 (translation table walk)" }, 692 { do_sea, SIGKILL, SI_KERNEL, "level 3 (translation table walk)" }, 693 { do_sea, SIGBUS, BUS_OBJERR, "synchronous parity or ECC error" }, // Reserved when RAS is implemented 694 { do_bad, SIGKILL, SI_KERNEL, "unknown 25" }, 695 { do_bad, SIGKILL, SI_KERNEL, "unknown 26" }, 696 { do_bad, SIGKILL, SI_KERNEL, "unknown 27" }, 697 { do_sea, SIGKILL, SI_KERNEL, "level 0 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 698 { do_sea, SIGKILL, SI_KERNEL, "level 1 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 699 { do_sea, SIGKILL, SI_KERNEL, "level 2 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 700 { do_sea, SIGKILL, SI_KERNEL, "level 3 synchronous parity error (translation table walk)" }, // Reserved when RAS is implemented 701 { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, 702 { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, 703 { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, 704 { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, 705 { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, 706 { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, 707 { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, 708 { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, 709 { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, 710 { do_bad, SIGKILL, SI_KERNEL, "unknown 41" }, 711 { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, 712 { do_bad, SIGKILL, SI_KERNEL, "unknown 43" }, 713 { do_bad, SIGKILL, SI_KERNEL, "unknown 44" }, 714 { do_bad, SIGKILL, SI_KERNEL, "unknown 45" }, 715 { do_bad, SIGKILL, SI_KERNEL, "unknown 46" }, 716 { do_bad, SIGKILL, SI_KERNEL, "unknown 47" }, 717 { do_bad, SIGKILL, SI_KERNEL, "TLB conflict abort" }, 718 { do_bad, SIGKILL, SI_KERNEL, "Unsupported atomic hardware update fault" }, 719 { do_bad, SIGKILL, SI_KERNEL, "unknown 50" }, 720 { do_bad, SIGKILL, SI_KERNEL, "unknown 51" }, 721 { do_bad, SIGKILL, SI_KERNEL, "implementation fault (lockdown abort)" }, 722 { do_bad, SIGBUS, BUS_OBJERR, "implementation fault (unsupported exclusive)" }, 723 { do_bad, SIGKILL, SI_KERNEL, "unknown 54" }, 724 { do_bad, SIGKILL, SI_KERNEL, "unknown 55" }, 725 { do_bad, SIGKILL, SI_KERNEL, "unknown 56" }, 726 { do_bad, SIGKILL, SI_KERNEL, "unknown 57" }, 727 { do_bad, SIGKILL, SI_KERNEL, "unknown 58" }, 728 { do_bad, SIGKILL, SI_KERNEL, "unknown 59" }, 729 { do_bad, SIGKILL, SI_KERNEL, "unknown 60" }, 730 { do_bad, SIGKILL, SI_KERNEL, "section domain fault" }, 731 { do_bad, SIGKILL, SI_KERNEL, "page domain fault" }, 732 { do_bad, SIGKILL, SI_KERNEL, "unknown 63" }, 733 }; 734 735 asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, 736 struct pt_regs *regs) 737 { 738 const struct fault_info *inf = esr_to_fault_info(esr); 739 740 if (!inf->fn(addr, esr, regs)) 741 return; 742 743 if (!user_mode(regs)) { 744 pr_alert("Unhandled fault at 0x%016lx\n", addr); 745 mem_abort_decode(esr); 746 show_pte(addr); 747 } 748 749 arm64_notify_die(inf->name, regs, 750 inf->sig, inf->code, (void __user *)addr, esr); 751 } 752 753 asmlinkage void __exception do_el0_irq_bp_hardening(void) 754 { 755 /* PC has already been checked in entry.S */ 756 arm64_apply_bp_hardening(); 757 } 758 759 asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, 760 unsigned int esr, 761 struct pt_regs *regs) 762 { 763 /* 764 * We've taken an instruction abort from userspace and not yet 765 * re-enabled IRQs. If the address is a kernel address, apply 766 * BP hardening prior to enabling IRQs and pre-emption. 767 */ 768 if (!is_ttbr0_addr(addr)) 769 arm64_apply_bp_hardening(); 770 771 local_daif_restore(DAIF_PROCCTX); 772 do_mem_abort(addr, esr, regs); 773 } 774 775 776 asmlinkage void __exception do_sp_pc_abort(unsigned long addr, 777 unsigned int esr, 778 struct pt_regs *regs) 779 { 780 if (user_mode(regs)) { 781 if (!is_ttbr0_addr(instruction_pointer(regs))) 782 arm64_apply_bp_hardening(); 783 local_daif_restore(DAIF_PROCCTX); 784 } 785 786 arm64_notify_die("SP/PC alignment exception", regs, 787 SIGBUS, BUS_ADRALN, (void __user *)addr, esr); 788 } 789 790 int __init early_brk64(unsigned long addr, unsigned int esr, 791 struct pt_regs *regs); 792 793 /* 794 * __refdata because early_brk64 is __init, but the reference to it is 795 * clobbered at arch_initcall time. 796 * See traps.c and debug-monitors.c:debug_traps_init(). 797 */ 798 static struct fault_info __refdata debug_fault_info[] = { 799 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware breakpoint" }, 800 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware single-step" }, 801 { do_bad, SIGTRAP, TRAP_HWBKPT, "hardware watchpoint" }, 802 { do_bad, SIGKILL, SI_KERNEL, "unknown 3" }, 803 { do_bad, SIGTRAP, TRAP_BRKPT, "aarch32 BKPT" }, 804 { do_bad, SIGKILL, SI_KERNEL, "aarch32 vector catch" }, 805 { early_brk64, SIGTRAP, TRAP_BRKPT, "aarch64 BRK" }, 806 { do_bad, SIGKILL, SI_KERNEL, "unknown 7" }, 807 }; 808 809 void __init hook_debug_fault_code(int nr, 810 int (*fn)(unsigned long, unsigned int, struct pt_regs *), 811 int sig, int code, const char *name) 812 { 813 BUG_ON(nr < 0 || nr >= ARRAY_SIZE(debug_fault_info)); 814 815 debug_fault_info[nr].fn = fn; 816 debug_fault_info[nr].sig = sig; 817 debug_fault_info[nr].code = code; 818 debug_fault_info[nr].name = name; 819 } 820 821 /* 822 * In debug exception context, we explicitly disable preemption despite 823 * having interrupts disabled. 824 * This serves two purposes: it makes it much less likely that we would 825 * accidentally schedule in exception context and it will force a warning 826 * if we somehow manage to schedule by accident. 827 */ 828 static void debug_exception_enter(struct pt_regs *regs) 829 { 830 /* 831 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were 832 * already disabled to preserve the last enabled/disabled addresses. 833 */ 834 if (interrupts_enabled(regs)) 835 trace_hardirqs_off(); 836 837 if (user_mode(regs)) { 838 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 839 } else { 840 /* 841 * We might have interrupted pretty much anything. In 842 * fact, if we're a debug exception, we can even interrupt 843 * NMI processing. We don't want this code makes in_nmi() 844 * to return true, but we need to notify RCU. 845 */ 846 rcu_nmi_enter(); 847 } 848 849 preempt_disable(); 850 851 /* This code is a bit fragile. Test it. */ 852 RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work"); 853 } 854 NOKPROBE_SYMBOL(debug_exception_enter); 855 856 static void debug_exception_exit(struct pt_regs *regs) 857 { 858 preempt_enable_no_resched(); 859 860 if (!user_mode(regs)) 861 rcu_nmi_exit(); 862 863 if (interrupts_enabled(regs)) 864 trace_hardirqs_on(); 865 } 866 NOKPROBE_SYMBOL(debug_exception_exit); 867 868 #ifdef CONFIG_ARM64_ERRATUM_1463225 869 DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 870 871 static int __exception 872 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 873 { 874 if (user_mode(regs)) 875 return 0; 876 877 if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) 878 return 0; 879 880 /* 881 * We've taken a dummy step exception from the kernel to ensure 882 * that interrupts are re-enabled on the syscall path. Return back 883 * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions 884 * masked so that we can safely restore the mdscr and get on with 885 * handling the syscall. 886 */ 887 regs->pstate |= PSR_D_BIT; 888 return 1; 889 } 890 #else 891 static int __exception 892 cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 893 { 894 return 0; 895 } 896 #endif /* CONFIG_ARM64_ERRATUM_1463225 */ 897 898 asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, 899 unsigned int esr, 900 struct pt_regs *regs) 901 { 902 const struct fault_info *inf = esr_to_debug_fault_info(esr); 903 unsigned long pc = instruction_pointer(regs); 904 905 if (cortex_a76_erratum_1463225_debug_handler(regs)) 906 return; 907 908 debug_exception_enter(regs); 909 910 if (user_mode(regs) && !is_ttbr0_addr(pc)) 911 arm64_apply_bp_hardening(); 912 913 if (inf->fn(addr_if_watchpoint, esr, regs)) { 914 arm64_notify_die(inf->name, regs, 915 inf->sig, inf->code, (void __user *)pc, esr); 916 } 917 918 debug_exception_exit(regs); 919 } 920 NOKPROBE_SYMBOL(do_debug_exception); 921